Global Patent Index - EP 3201786 A1

EP 3201786 A1 20170809 - CLOCK-FREE DUAL-DATA-RATE LINK WITH BUILT-IN FLOW CONTROL

Title (en)

CLOCK-FREE DUAL-DATA-RATE LINK WITH BUILT-IN FLOW CONTROL

Title (de)

TAKTFREIE VERBINDUNG MIT DOPPELTER DATENRATE UND EINGEBAUTER FLUSSSTEUERUNG

Title (fr)

LIAISON À DOUBLE DÉBIT DE DONNÉES, SANS SIGNAL D'HORLOGE ET À CONTRÔLE DE FLUX INTÉGRÉ

Publication

EP 3201786 A1 20170809 (EN)

Application

EP 15784803 A 20150925

Priority

  • US 201462059798 P 20141003
  • US 201514864586 A 20150924
  • US 2015052351 W 20150925

Abstract (en)

[origin: WO2016053796A1] A dual-data-rate interface is provided that includes a transmitter driving a transmit pin coupled to a receive pin of a receiver. The receiver drives its receive pin with cycles of a fetch clock. The transmitter responds to each edge of the fetch clock by transmitting a bit over the transmit pin to the receiver.

IPC 8 full level

G06F 13/42 (2006.01)

CPC (source: EP KR US)

G06F 1/3234 (2013.01 - US); G06F 1/3243 (2013.01 - KR US); G06F 13/4286 (2013.01 - EP KR US); G06F 13/4295 (2013.01 - EP KR US)

Citation (search report)

See references of WO 2016053796A1

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA ME

DOCDB simple family (publication)

WO 2016053796 A1 20160407; AU 2015324190 A1 20170316; BR 112017006546 A2 20171219; CN 106796568 A 20170531; EP 3201786 A1 20170809; JP 2017531942 A 20171026; KR 20170067745 A 20170616; US 2016098073 A1 20160407; US 9933834 B2 20180403

DOCDB simple family (application)

US 2015052351 W 20150925; AU 2015324190 A 20150925; BR 112017006546 A 20150925; CN 201580052786 A 20150925; EP 15784803 A 20150925; JP 2017516869 A 20150925; KR 20177008953 A 20150925; US 201514864586 A 20150924