EP 3283945 B1 20190724 - MIXED-RADIX CARRY-LOOKAHEAD ADDER ARCHITECTURE
Title (en)
MIXED-RADIX CARRY-LOOKAHEAD ADDER ARCHITECTURE
Title (de)
ARCHITEKTUR EINES MIXED-RADIX-CARRY-LOOKAHEAD-ADDIERERS
Title (fr)
ARCHITECTURE D'ADDITIONNEUR À RETENUE ANTICIPÉE À BASES MÉLANGÉES
Publication
Application
Priority
- US 201514740841 A 20150616
- US 2016037304 W 20160614
Abstract (en)
[origin: WO2016205155A1] Embodiments described herein are directed to mixed-radix carry-lookahead adders and methods performed thereby. The mixed-radix carry-lookahead adder includes an multiple carry-lookahead stages, where each stage may be of a different radix. Each stage operates on input bits, creating and implementing propagate and generate signals for each bit. The carry-lookahead stages also compute an XOR of the inputs that is forwarded to a final carry-lookahead stage. The elements of the initial and subsequent carry-lookahead stages are arranged such that each of the propagate and generate output signals passes through a minimal number of passive transmission lines. The final stage of the mixed-radix carry-lookahead adder includes an XOR logic gate configured to receive the generate output from an intermediate carry-lookahead stage and XOR the generate output received from the intermediate carry-lookahead stage with the computed XOR signal forwarded from the initial carry-lookahead stage to produce a sum of the input bits.
IPC 8 full level
G06F 7/508 (2006.01)
CPC (source: CN EP US)
G06F 7/501 (2013.01 - US); G06F 7/508 (2013.01 - CN EP US)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
DOCDB simple family (publication)
WO 2016205155 A1 20161222; CN 107810473 A 20180316; CN 107810473 B 20210622; EP 3283945 A1 20180221; EP 3283945 B1 20190724; US 10073677 B2 20180911; US 2016371058 A1 20161222
DOCDB simple family (application)
US 2016037304 W 20160614; CN 201680035383 A 20160614; EP 16731480 A 20160614; US 201514740841 A 20150616