Global Patent Index - EP 3455911 A1

EP 3455911 A1 20190320 - III-V CHIP PREPARATION AND INTEGRATION IN SILICON PHOTONICS

Title (en)

III-V CHIP PREPARATION AND INTEGRATION IN SILICON PHOTONICS

Title (de)

III-V-CHIP-HERSTELLUNG UND INTEGRATION IN SILICIUMPHOTONIK

Title (fr)

PRÉPARATION ET INTÉGRATION DE PUCES III-V DANS UNE PHOTONIQUE DE SILICIUM

Publication

EP 3455911 A1 20190320 (EN)

Application

EP 17796852 A 20170511

Priority

  • US 201662334895 P 20160511
  • US 2017032189 W 20170511

Abstract (en)

[origin: CN109417266A] A composite semiconductor laser is made by securing a III-V wafer to a transfer wafer. A substrate of the III-V wafer is removed, and the III-V wafer is etched into a plurality of chips while the III-V wafer is secured to the transfer wafer. The transfer wafer is singulated. A portion of the transfer wafer is used as a handle for bonding the chip in a recess of a silicon device. The chip is used as a gain medium for the semiconductor laser.

IPC 8 full level

H01S 5/02 (2006.01); H01S 5/02375 (2021.01)

CPC (source: EP US)

G02B 6/122 (2013.01 - EP); G02B 6/136 (2013.01 - EP US); G02B 6/4201 (2013.01 - US); H01L 24/03 (2013.01 - US); H01S 5/02257 (2021.01 - US); H01S 5/0236 (2021.01 - US); H01S 5/02375 (2021.01 - EP US); G02B 2006/12097 (2013.01 - EP US); H01S 5/0217 (2013.01 - EP); H01S 5/0234 (2021.01 - EP); H01S 5/0237 (2021.01 - EP); H01S 2301/176 (2013.01 - EP)

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA ME

DOCDB simple family (publication)

CN 109417266 A 20190301; CN 109417266 B 20210507; EP 3455911 A1 20190320; EP 3455911 A4 20200415

DOCDB simple family (application)

CN 201780043053 A 20170511; EP 17796852 A 20170511