EP 3559806 A4 20200902 - ACCELERATING PARA-VIRTUALIZATION NETWORK INTERFACE USING DIRECT MEMORY ACCESS (DMA) REMAPPING
Title (en)
ACCELERATING PARA-VIRTUALIZATION NETWORK INTERFACE USING DIRECT MEMORY ACCESS (DMA) REMAPPING
Title (de)
BESCHLEUNIGUNG EINER PARAVIRTUALISIERUNGSNETZWERKSCHNITTSTELLE MITTELS REMAPPING EINES DIREKTEN SPEICHERZUGANGD (DMA)
Title (fr)
ACCÉLÉRATION D'INTERFACE RÉSEAU DE PARAVIRTUALISATION À L'AIDE DE REMAPPAGE D'ACCÈS DIRECT À LA MÉMOIRE (DMA)
Publication
Application
Priority
CN 2016111463 W 20161222
Abstract (en)
[origin: WO2018112827A1] An example electronic apparatus is for accelerating a para-virtualization network interface. The electronic apparatus includes a descriptor hub performing bi-directionally communication with a guest memory accessible by a guest and with a host memory accessible by a host. The guest includes a plurality of virtual machines. The host includes a plurality of virtual function devices. The virtual machines are communicatively coupled to the electronic apparatus through a central processing unit. The communication is based upon para-virtualization packet descriptors and network interface controller virtual function-specific descriptors. The electronic apparatus also includes a device association table communicatively coupled to the descriptor hub and to store associations between the virtual machines and the virtual function devices. The electronic apparatus further includes an input-output memory map unit (IOMMU) to perform direct memory access (DMA) remapping and interrupt remapping.
IPC 8 full level
G06F 9/455 (2018.01); G06F 9/54 (2006.01)
CPC (source: EP US)
G06F 9/45545 (2013.01 - US); G06F 9/4555 (2013.01 - EP US); G06F 9/45558 (2013.01 - EP US); G06F 9/544 (2013.01 - EP); G06F 12/0802 (2013.01 - US); G06F 13/24 (2013.01 - US); G06F 13/28 (2013.01 - US); G06F 2009/4557 (2013.01 - US); G06F 2009/45579 (2013.01 - EP); G06F 2009/45583 (2013.01 - EP US); G06F 2009/45595 (2013.01 - EP US); G06F 2213/3808 (2013.01 - US)
Citation (search report)
- [Y] US 2016019079 A1 20160121 - CHAWLA GAURAV [US], et al
- [A] US 2015293774 A1 20151015 - PERSSON HAKAN [SE], et al
- [Y] WEI WANG ET AL: "pvFPGA: Accessing an FPGA-based hardware accelerator in a paravirtualized environment", 2013 INTERNATIONAL CONFERENCE ON HARDWARE/SOFTWARE CODESIGN AND SYSTEM SYNTHESIS (CODES+ISSS), IEEE, 29 September 2013 (2013-09-29), pages 1 - 9, XP032524765, DOI: 10.1109/CODES-ISSS.2013.6658997
- See references of WO 2018112827A1
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
DOCDB simple family (publication)
WO 2018112827 A1 20180628; CN 109983438 A 20190705; CN 109983438 B 20240202; EP 3559806 A1 20191030; EP 3559806 A4 20200902; EP 3559806 B1 20220831; US 11853784 B2 20231226; US 2019354387 A1 20191121; US 2024184607 A1 20240606
DOCDB simple family (application)
CN 2016111463 W 20161222; CN 201680091031 A 20161222; EP 16924729 A 20161222; US 201616463473 A 20161222; US 202318388505 A 20231109