Global Patent Index - EP 3698402 A1

EP 3698402 A1 20200826 - 3D COMPUTE CIRCUIT WITH HIGH DENSITY Z-AXIS INTERCONNECTS

Title (en)

3D COMPUTE CIRCUIT WITH HIGH DENSITY Z-AXIS INTERCONNECTS

Title (de)

3D-COMPUTERSCHALTUNG MIT HOCHDICHTEN Z-ACHSENVERBINDUNGEN

Title (fr)

CIRCUIT DE CALCUL 3D À FORTE DENSITÉ D'INTERCONNEXIONS D'AXE Z

Publication

EP 3698402 A1 20200826 (EN)

Application

EP 18803498 A 20181018

Priority

  • US 201762575240 P 20171020
  • US 201762575221 P 20171020
  • US 201762575259 P 20171020
  • US 201762575184 P 20171020
  • US 201715859612 A 20171231
  • US 201715859548 A 20171231
  • US 201715859551 A 20171231
  • US 201715859546 A 20171231
  • US 201862619910 P 20180121
  • US 201815976809 A 20180510
  • US 201862678246 P 20180530
  • US 201816159705 A 20181014
  • US 201816159704 A 20181014
  • US 201816159703 A 20181014
  • US 2018056559 W 20181018

Abstract (en)

[origin: WO2019079625A1] Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers. These connections are also referred to as vertical connections to differentiate them from the horizontal planar connections along the interconnect layers of the IC dies.

IPC 8 full level

H01L 25/18 (2006.01); G06F 13/00 (2006.01); G06F 15/16 (2006.01); H01L 21/60 (2006.01); H01L 21/98 (2006.01); H01L 25/065 (2006.01)

CPC (source: EP)

H01L 24/80 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/80894 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01)

C-Set (source: EP)

H01L 2924/00014 + H01L 2224/13099

Citation (search report)

See references of WO 2019079625A1

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA ME

DOCDB simple family (publication)

WO 2019079625 A1 20190425; CN 111492477 A 20200804; EP 3698402 A1 20200826; TW 201933578 A 20190816; TW I745626 B 20211111

DOCDB simple family (application)

US 2018056559 W 20181018; CN 201880082142 A 20181018; EP 18803498 A 20181018; TW 107136961 A 20181019