Global Patent Index - EP 3857549 A1

EP 3857549 A1 20210804 - ARCHITECTURE TO MITIGATE CONFIGURATION MEMORY IMPRINTING IN PROGRAMMABLE LOGIC

Title (en)

ARCHITECTURE TO MITIGATE CONFIGURATION MEMORY IMPRINTING IN PROGRAMMABLE LOGIC

Title (de)

ARCHITEKTUR ZUR ABSCHWÄCHUNG DER KONFIGURATIONSSPEICHERPRÄGUNG IN PROGRAMMIERBARER LOGIK

Title (fr)

ARCHITECTURE POUR ATTÉNUER L'EMPREINTE EN MÉMOIRE DE CONFIGURATION DANS UNE LOGIQUE PROGRAMMABLE

Publication

EP 3857549 A1 20210804 (EN)

Application

EP 19783768 A 20190920

Priority

  • US 201816141357 A 20180925
  • US 2019052203 W 20190920

Abstract (en)

[origin: US2020097684A1] A method and architecture for mitigating configuration memory imprinting in programmable logic devices. At power-up, a configuration memory inversion control determines whether to operate the current power cycle in normal mode or inversion mode, with an objective of equal time in each mode over the system's lifecycle. A configuration memory (CM) input inversion plane is positioned between a CM controller and the CM cells, and a CM output inversion plane is positioned between the CM cells and the FPGA function blocks. When running in inversion mode, data to/from the CM cells is inverted (0's and 1's are swapped) by the input and output inversion planes. By balancing time individual memory addresses spend in high and low voltage states, the system minimizes differences in memory cell stresses, thus reducing memory imprinting effects. The same concept applied to other architectures, such as a processor's external RAM and internal cache, is also disclosed.

IPC 8 full level

G11C 7/24 (2006.01); G06F 21/60 (2013.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 11/412 (2006.01); H03K 19/173 (2006.01)

CPC (source: EP US)

G06F 11/1004 (2013.01 - US); G06F 12/1408 (2013.01 - US); G06F 21/76 (2013.01 - US); G06F 21/78 (2013.01 - US); G06F 21/79 (2013.01 - EP); G11C 7/1006 (2013.01 - EP); G11C 7/22 (2013.01 - EP); G11C 7/24 (2013.01 - EP); G11C 11/412 (2013.01 - EP)

Citation (search report)

See references of WO 2020068591A1

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA ME

DOCDB simple family (publication)

US 10754993 B2 20200825; US 2020097684 A1 20200326; EP 3857549 A1 20210804; JP 2022502812 A 20220111; JP 7232339 B2 20230302; WO 2020068591 A1 20200402

DOCDB simple family (application)

US 201816141357 A 20180925; EP 19783768 A 20190920; JP 2021540788 A 20190920; US 2019052203 W 20190920