EP 3881355 A1 20210922 - FERROELECTRIC MEMORY DEVICE WITH SELECT GATE TRANSISTOR AND METHOD OF FORMING THE SAME
Title (en)
FERROELECTRIC MEMORY DEVICE WITH SELECT GATE TRANSISTOR AND METHOD OF FORMING THE SAME
Title (de)
FERROELEKTRISCHE SPEICHERVORRICHTUNG MIT AUSWAHL-GATE-TRANSISTOR UND VERFAHREN ZU DEREN HERSTELLUNG
Title (fr)
DISPOSITIF DE MÉMOIRE FERROÉLECTRIQUE AVEC TRANSISTOR À GRILLE DE SÉLECTION ET SON PROCÉDÉ DE FORMATION
Publication
Application
Priority
- US 201916456736 A 20190628
- US 2019068869 W 20191230
Abstract (en)
[origin: US2020411533A1] A memory cell includes a ferroelectric memory transistor, and a select gate transistor which shares a common semiconductor channel, a common source region and a common drain region with the ferroelectric memory transistor. The select gate transistor controls access between the common source region and the common semiconductor channel.
IPC 8 full level
H01L 27/07 (2006.01); G11C 11/22 (2006.01); H01L 27/105 (2006.01)
CPC (source: EP KR US)
G11C 11/223 (2013.01 - EP KR US); G11C 11/2255 (2013.01 - US); G11C 11/2257 (2013.01 - US); G11C 11/2259 (2013.01 - EP KR); G11C 11/2273 (2013.01 - US); H01L 29/40111 (2019.07 - KR US); H01L 29/42368 (2013.01 - US); H01L 29/42376 (2013.01 - US); H01L 29/6684 (2013.01 - EP KR US); H01L 29/78391 (2014.09 - EP KR US); H10B 51/10 (2023.02 - EP KR); H10B 51/20 (2023.02 - US); H10B 51/30 (2023.02 - EP KR US)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
US 10978482 B2 20210413; US 2020411533 A1 20201231; CN 113196480 A 20210730; EP 3881355 A1 20210922; EP 3881355 A4 20220720; KR 102591269 B1 20231020; KR 20210095182 A 20210730; WO 2020263338 A1 20201230
DOCDB simple family (application)
US 201916456736 A 20190628; CN 201980081329 A 20191230; EP 19934798 A 20191230; KR 20217019530 A 20191230; US 2019068869 W 20191230