EP 3896553 A1 20211020 - FORCING CORE LOW POWER STATES IN A PROCESSOR
Title (en)
FORCING CORE LOW POWER STATES IN A PROCESSOR
Title (de)
ERZWINGEN VON NIEDRIGEN KERNLEISTUNGSZUSTÄNDEN IN EINEM PROZESSOR
Title (fr)
FORÇAGE DES ÉTATS DE FAIBLE PUISSANCE DU C UR DANS UN PROCESSEUR
Publication
Application
Priority
- US 201313972569 A 20130821
- EP 14180539 A 20140811
Abstract (en)
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed
IPC 8 full level
G06F 1/32 (2019.01)
CPC (source: EP US)
G06F 1/266 (2013.01 - US); G06F 1/3287 (2013.01 - US); G06F 1/3293 (2013.01 - EP US); G06F 1/3296 (2013.01 - EP US); G06F 9/4893 (2013.01 - US); Y02D 10/00 (2018.01 - EP US); Y02D 30/50 (2020.08 - EP US)
Citation (search report)
- [A] US 2012079290 A1 20120329 - KUMAR PANKAJ [US], et al
- [A] US 2006123251 A1 20060608 - NAKAJIMA JUN [US], et al
- [A] WO 2009120427 A1 20091001 - MICROSOFT CORP [US]
- [A] US 2013007494 A1 20130103 - BRANOVER ALEXANDER [US], et al
- [YA] US 2008168287 A1 20080710 - BERRY ROBERT WALTER [US], et al
- [YA] US 2008250260 A1 20081009 - TOMITA HARUO [JP]
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
DOCDB simple family (publication)
EP 2840461 A1 20150225; EP 2840461 B1 20210526; EP 3896553 A1 20211020; EP 3896553 B1 20231220; US 10310588 B2 20190604; US 2015058650 A1 20150226; US 2017102752 A1 20170413; US 9495001 B2 20161115
DOCDB simple family (application)
EP 14180539 A 20140811; EP 21171073 A 20140811; US 201313972569 A 20130821; US 201615296096 A 20161018