EP 3975237 A4 20220720 - THREE-PHASE INVERSION POWER CHIP AND PREPARATION METHOD THEREFOR
Title (en)
THREE-PHASE INVERSION POWER CHIP AND PREPARATION METHOD THEREFOR
Title (de)
DREIPHASIGER INVERSIONSLEISTUNGSCHIP UND HERSTELLUNGSVERFAHREN DAFÜR
Title (fr)
PUCE DE PUISSANCE D'INVERSION À TRIPHASÉE ET SON PROCÉDÉ DE PRÉPARATION
Publication
Application
Priority
- CN 201910635287 A 20190715
- CN 2020097755 W 20200623
Abstract (en)
[origin: EP3975237A1] The present invention relates to a field of chip technology, and discloses a three-phase inverter power chip and a preparation method therefor. The preparation method includes: forming active areas on a substrate and an isolation area located outside the active areas; forming a source electrode, a drain electrode and a gate electrode of a transistor in each active area; forming a first bond pad, second bond pads, third bond pads and fourth bond pads in the isolation area; the source electrode, the drain electrode and the gate electrode of the chip being extended to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto; and electrically connecting the source electrode, the drain electrode and the gate electrode of the transistor to the first bond pad, the second bond pads, the third bond pads or the fourth bond pads corresponding thereto. The three-phase inverter power chip prepared by the preparation method for the three-phase inverter power chip improves an integration, reduces parasitic inductance in the chip, thereby improving a working efficiency of a circuit.
IPC 8 full level
H01L 21/8252 (2006.01); H01L 27/06 (2006.01); H01L 27/085 (2006.01); H02M 7/00 (2006.01); H01L 23/528 (2006.01); H01L 29/20 (2006.01)
CPC (source: CN EP US)
H01L 21/4846 (2013.01 - CN US); H01L 21/8252 (2013.01 - CN EP US); H01L 23/49844 (2013.01 - CN US); H01L 23/528 (2013.01 - US); H01L 27/0207 (2013.01 - CN US); H01L 27/0605 (2013.01 - EP US); H01L 27/085 (2013.01 - EP US); H01L 27/088 (2013.01 - CN US); H01L 29/0642 (2013.01 - US); H02M 7/003 (2013.01 - CN EP US); H02M 7/53875 (2013.01 - US); H01L 29/1066 (2013.01 - EP US); H01L 29/2003 (2013.01 - EP US); H01L 29/7786 (2013.01 - EP US); Y02B 70/10 (2013.01 - EP)
Citation (search report)
- [I] CN 208739041 U 20190412 - GANPOWER SEMICONDUCTOR FOSHAN CO LTD
- [Y] EP 2775520 A2 20140910 - INT RECTIFIER CORP [US]
- [A] US 2017221814 A1 20170803 - KINOSHITA YUSUKE [JP], et al
- [A] US 2015155377 A1 20150604 - KIM CHE-HEUNG [KR]
- [A] EP 2955755 A1 20151216 - ENKRIS SEMICONDUCTOR INC [CN]
- [Y] UEMOTO Y ET AL: "GaN monolithic inverter IC using normally-off gate injection transistors with planar isolation on Si substrate", ELECTRON DEVICES MEETING (IEDM), 2009 IEEE INTERNATIONAL, IEEE, PISCATAWAY, NJ, USA, 7 December 2009 (2009-12-07), pages 1 - 4, XP031644579, ISBN: 978-1-4244-5639-0
- [A] UEMOTO Y ET AL: "Gate Injection Transistor (GIT)-A Normally-Off AlGaN/GaN Power Transistor Using Conductivity Modulation", IEEE TRANSACTIONS ON ELECTRON DEVICES, IEEE, USA, vol. 54, no. 12, December 2007 (2007-12-01), pages 3393 - 3399, XP011197116, ISSN: 0018-9383
- [A] EFTHYMIOU L ET AL: "On the physical operation and optimization of the p-GaN gate in normally-off GaN HEMT devices", APPLIED PHYSICS LETTERS, AMERICAN INSTITUTE OF PHYSICS, 2 HUNTINGTON QUADRANGLE, MELVILLE, NY 11747, vol. 110, no. 12, 21 March 2017 (2017-03-21), XP012217334, ISSN: 0003-6951, [retrieved on 20170321], DOI: 10.1063/1.4978690
- See references of WO 2021008317A1
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
EP 3975237 A1 20220330; EP 3975237 A4 20220720; CN 112234030 A 20210115; CN 112234030 B 20230721; US 11901840 B2 20240213; US 2022286063 A1 20220908; WO 2021008317 A1 20210121
DOCDB simple family (application)
EP 20840520 A 20200623; CN 201910635287 A 20190715; CN 2020097755 W 20200623; US 202017624930 A 20200623