EP 4038732 A1 20220810 - CIRCUIT ARRANGEMENT FOR ASCERTAINING A TYPE OF AND A VALUE OF AN INPUT VOLTAGE, AND ASSOCIATED METHOD
Title (en)
CIRCUIT ARRANGEMENT FOR ASCERTAINING A TYPE OF AND A VALUE OF AN INPUT VOLTAGE, AND ASSOCIATED METHOD
Title (de)
SCHALTUNGSANORDNUNG ZUM ERMITTELN EINER ART UND EINES WERTS EINER EINGANGSSPANNUNG UND ZUGEHÖRIGES VERFAHREN
Title (fr)
AGENCEMENT DE CIRCUIT POUR DÉTERMINER UN TYPE DE TENSION D'ENTRÉE ET UNE VALEUR D'UNE TENSION D'ENTRÉE, ET PROCÉDÉ ASSOCIÉ
Publication
Application
Priority
- EP 19205873 A 20191029
- EP 2020079929 W 20201023
Abstract (en)
[origin: WO2021083810A1] The invention relates to a circuit arrangement, by means of which a voltage type and a voltage value, in particular an average value, of an input voltage (Ue) of a power supply (SV) or of a switching-mode power supply (SV) is ascertained. The circuit arrangement (ME) is arranged such that the input voltage (Ue) of the power supply (SV) decreases at the input side of the circuit arrangement (ME). The circuit arrangement (ME) comprises at least one differential amplifier (DIF) for converting the input voltage (Ue) into a useful signal (NS), which signal is rectified by a first rectifier unit (GL1) arranged at an output of the differential amplifier (DIF), to which first rectifier unit a first compensation diode (K1) is assigned such that a forward voltage of the first rectifier unit (GL1) is compensated. The circuit assembly also comprises an inverter (INV) which generates an inverted useful signal (negNS) from the useful signal (NS). The inverted useful signal (negNS) is rectified by a second rectifier unit (GL2) arranged at an output of the inverter (INV), to which second rectifier unit a second compensation diode (K2) is assigned such that a forward voltage of the second rectifier unit (GL2) is compensated. The circuit arrangement also comprises a mixer unit (MS), by means of which a first output signal (AS1) is generated from the rectified useful signal (NS) and the rectified inverted useful signal (negNS), from which first output signal a second output signal (AS2) is derived by means of a filter unit. In the process, the voltage type can be determined from the first output signal (AS1), and a voltage value, in particular an average value, of the input voltage (Ue) can be determined from the second output signal (AS2).
IPC 8 full level
H02M 1/10 (2006.01); G01R 19/00 (2006.01); G01R 23/00 (2006.01); H02M 1/32 (2007.01); H02M 3/335 (2006.01)
CPC (source: CN EP US)
G01R 19/003 (2013.01 - CN); G01R 19/0084 (2013.01 - EP US); G01R 23/02 (2013.01 - US); G01R 23/15 (2013.01 - EP); G01R 31/40 (2013.01 - EP); H02M 1/08 (2013.01 - CN); H02M 1/10 (2013.01 - EP); H02M 1/38 (2013.01 - CN); H02M 1/44 (2013.01 - US); H02M 3/24 (2013.01 - US); H02M 7/04 (2013.01 - CN); H02M 1/32 (2013.01 - EP); H02M 3/33523 (2013.01 - EP)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
EP 3817205 A1 20210505; EP 3817205 B1 20240612; CN 114586272 A 20220603; EP 4038732 A1 20220810; US 2022373581 A1 20221124; WO 2021083810 A1 20210506
DOCDB simple family (application)
EP 19205873 A 20191029; CN 202080076107 A 20201023; EP 2020079929 W 20201023; EP 20804450 A 20201023; US 202017772396 A 20201023