Global Patent Index - EP 4092676 A4

EP 4092676 A4 20230125 - DATA READING/WRITING METHOD, MEMORY, STORAGE DEVICE, AND TERMINAL

Title (en)

DATA READING/WRITING METHOD, MEMORY, STORAGE DEVICE, AND TERMINAL

Title (de)

DATENLESE-/SCHREIBVERFAHREN, SPEICHER, SPEICHERVORRICHTUNG UND ENDGERÄT

Title (fr)

PROCÉDÉ DE LECTURE/ÉCRITURE DE DONNÉES, MÉMOIRE, DISPOSITIF DE STOCKAGE, ET TERMINAL

Publication

EP 4092676 A4 20230125 (EN)

Application

EP 20919490 A 20200221

Priority

CN 2020076279 W 20200221

Abstract (en)

[origin: EP4092676A1] A data reading/writing method, a memory, a storage apparatus, and a terminal are provided. The memory includes S storage blocks, N global bitlines, and a signal amplification circuit. Each of the S storage blocks is connected to the N global bitlines, the N global bitlines are connected to the signal amplification circuit, the signal amplification circuit is configured to amplify electrical signals on the N global bitlines, and each storage block includes N columns of storage units, N local bitlines, and N bitline switches. In each storage block, storage units in an i<sup>th</sup> column are connected to an i<sup>th</sup> local bitline, the i<sup>th</sup> local bitline is connected to an i<sup>th</sup> global bitline by using an i<sup>th</sup> bitline switch in the N bitline switches. A memory array is fine-grained, so that i<sup>th</sup> local bitlines in the S storage blocks can share one global bitline. This can shorten the local bitline, reduce parasitic capacitance caused by the local bitline, and reduce a delay of the memory.

IPC 8 full level

G11C 11/413 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 7/02 (2006.01); G11C 7/06 (2006.01); G11C 7/18 (2006.01); G11C 11/4093 (2006.01); G11C 11/4094 (2006.01); G11C 11/4097 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)

CPC (source: EP US)

G11C 5/025 (2013.01 - EP); G11C 5/063 (2013.01 - EP); G11C 7/065 (2013.01 - EP); G11C 7/067 (2013.01 - US); G11C 7/1012 (2013.01 - US); G11C 7/12 (2013.01 - US); G11C 7/18 (2013.01 - EP); G11C 8/08 (2013.01 - US); G11C 11/4093 (2013.01 - EP); G11C 11/4094 (2013.01 - EP); G11C 11/4097 (2013.01 - EP); G11C 11/413 (2013.01 - EP); G11C 11/418 (2013.01 - EP); G11C 11/419 (2013.01 - EP); G11C 16/08 (2013.01 - EP); G11C 16/24 (2013.01 - EP); G11C 16/26 (2013.01 - EP); G11C 7/02 (2013.01 - EP); G11C 2207/005 (2013.01 - EP)

Citation (search report)

  • [XYI] US 2002031007 A1 20020314 - OSADA KENICHI [JP], et al
  • [XYI] EP 0924709 A2 19990623 - SIEMENS AG [DE], et al
  • [YA] US 2001030893 A1 20011018 - TERZIOGLU ESIN [US], et al
  • [XYI] MATTHEW POREMBA ET AL: "Fine-granularity tile-level parallelism in non-volatile memory architecture with two-dimensional bank subdivision", PROCEEDINGS OF THE 53RD ANNUAL DESIGN AUTOMATION CONFERENCE ON, DAC '16, ACM PRESS, NEW YORK, NEW YORK, USA, 5 June 2016 (2016-06-05), pages 1 - 6, XP058259033, ISBN: 978-1-4503-4236-0, DOI: 10.1145/2897937.2898024
  • See also references of WO 2021164032A1

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA ME

Designated validation state (EPC)

KH MA MD TN

DOCDB simple family (publication)

EP 4092676 A1 20221123; EP 4092676 A4 20230125; CN 115039176 A 20220909; US 2022406348 A1 20221222; WO 2021164032 A1 20210826

DOCDB simple family (application)

EP 20919490 A 20200221; CN 2020076279 W 20200221; CN 202080095326 A 20200221; US 202217893067 A 20220822