EP 4114020 A4 20230503 - VIDEO SIGNAL PROCESSING DEVICE, VIDEO SIGNAL PROCESSING METHOD, PROGRAM, AND SIGNAL PROCESSING CIRCUIT
Title (en)
VIDEO SIGNAL PROCESSING DEVICE, VIDEO SIGNAL PROCESSING METHOD, PROGRAM, AND SIGNAL PROCESSING CIRCUIT
Title (de)
VIDEOSIGNALVERARBEITUNGSVORRICHTUNG, VIDEOSIGNALVERARBEITUNGSVERFAHREN, PROGRAMM UND SIGNALVERARBEITUNGSSCHALTUNG
Title (fr)
DISPOSITIF DE TRAITEMENT DE SIGNAL VIDÉO, PROCÉDÉ DE TRAITEMENT DE SIGNAL VIDÉO, PROGRAMME, ET CIRCUIT DE TRAITEMENT DE SIGNAL
Publication
Application
Priority
- JP 2020030744 A 20200226
- JP 2020038655 W 20201013
Abstract (en)
[origin: EP4114020A1] A video signal processing device (10) includes an SoC (100) that receives input of a plurality of video signals, each including a plurality of packets, and multiplexing the video signals to output a multiplexed video signal, and an FPGA (200) that receives input of a multiplexed video signal and demultiplexes the multiplexed video signal to output the plurality of video signals. When deficient data whose size is less than the size of one packet is detected in any of a plurality of video signals, the FPGA (200) performs one of (i) processing for discarding the detected deficient data and (ii) processing for adding dummy data to the detected deficient data to make the size of the deficient data equal to the size of an integral multiple of one packet.
IPC 8 full level
H04N 21/426 (2011.01); H04N 21/418 (2011.01); H04N 21/434 (2011.01); H04N 21/436 (2011.01); H04N 21/438 (2011.01); H04N 21/4385 (2011.01)
CPC (source: EP US)
H04N 21/2343 (2013.01 - US); H04N 21/4181 (2013.01 - EP); H04N 21/4183 (2013.01 - EP); H04N 21/4344 (2013.01 - EP); H04N 21/4346 (2013.01 - EP); H04N 21/4347 (2013.01 - EP); H04N 21/43607 (2013.01 - EP); H04N 21/4383 (2013.01 - EP); H04N 21/4385 (2013.01 - US); H04N 21/4385 (2013.01 - EP)
Citation (search report)
- [Y] EP 3217675 A1 20170913 - PANASONIC IP MAN CO LTD [JP]
- [Y] JP 2007096737 A 20070412 - OKI ELECTRIC IND CO LTD
- [A] US 2003002577 A1 20030102 - PINDER HOWARD G [US]
- [A] US 6937618 B1 20050830 - NODA TATSUSHI [JP], et al
- [AD] EP 2757796 A1 20140723 - PANASONIC CORP [JP]
Citation (examination)
- US 2017118317 A1 20170427 - HASEGAWA TERUAKI [JP], et al
- See also references of WO 2021171687A1
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
Designated validation state (EPC)
KH MA MD TN
DOCDB simple family (publication)
EP 4114020 A1 20230104; EP 4114020 A4 20230503; JP 7573217 B2 20241025; JP WO2021171687 A1 20210902; US 12015822 B2 20240618; US 2023090807 A1 20230323; WO 2021171687 A1 20210902
DOCDB simple family (application)
EP 20921795 A 20201013; JP 2020038655 W 20201013; JP 2022503080 A 20201013; US 202017799834 A 20201013