EP 4158630 A1 20230405 - MEMRISTOR-BASED FULL ADDER AND METHOD FOR THE OPERATION THEREOF
Title (en)
MEMRISTOR-BASED FULL ADDER AND METHOD FOR THE OPERATION THEREOF
Title (de)
MEMRISTOR-BASIERTE VOLLADDIERER UND VERFAHREN ZU DEREN BETRIEB
Title (fr)
ADDITIONNEUR FONDÉ SUR UN MEMRISTOR ET PROCÉDÉ DE FONCTIONNEMENT CORRESPONDANT
Publication
Application
Priority
- DE 102020206796 A 20200529
- EP 2021064270 W 20210527
Abstract (en)
[origin: WO2021239911A1] The invention relates to a device for implementing one or more logical operations according to one embodiment. Each of the one or more logical operations has one or more binary input variables and has a binary output value dependent on the logical operation executed and dependent on the one or more binary input variables. The device comprises one or more switchable elements (111, 112). The device is configured to execute write operations and read operations. More specifically, the device is configured to execute each of the write operations in such a manner that a write bias is applied to one of the one or more switchable elements (111, 112), which write bias switches the switchable element into a first state or into a second state dependent on the write bias, the second state being different from the first state. The device is further configured to execute each of the read operations in such a manner that a read bias is applied to one of the one or more switchable elements (111, 112), to determine whether the switchable element has been switched to a first state or to the second state. The device is configured to select, for each of the one or more binary input variables of each of the one or more binary operations, the write bias of at least one of the write operations dependent on said binary input variables. The device is further configured to determine the binary output value of each of the one or more logical operations by applying the read voltage of one of the read operations dependent on the state in which one of the one or more switchable elements (111, 112), to which the read voltage is applied, has been switched.
IPC 8 full level
G11C 7/10 (2006.01); G11C 13/00 (2006.01)
CPC (source: EP)
G11C 7/1006 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01)
Citation (search report)
See references of WO 2021239911A1
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
Designated validation state (EPC)
KH MA MD TN
DOCDB simple family (publication)
DE 102020206796 A1 20211202; EP 4158630 A1 20230405; WO 2021239911 A1 20211202
DOCDB simple family (application)
DE 102020206796 A 20200529; EP 2021064270 W 20210527; EP 21729858 A 20210527