EP 4232833 A1 20230830 - HIGH-THROUGHPUT SCAN ARCHITECTURE
Title (en)
HIGH-THROUGHPUT SCAN ARCHITECTURE
Title (de)
SCAN-ARCHITEKTUR MIT HOHEM DURCHSATZ
Title (fr)
ARCHITECTURE DE BALAYAGE À HAUT DÉBIT
Publication
Application
Priority
US 2022011310 W 20220105
Abstract (en)
[origin: WO2023132825A1] Methods, systems, and apparatus, for a high throughput scan architecture. The scan architecture can include a clock controller, a decompressor, a scan chain, and a compressor. In some implementations, a set of values that represents a particular data pattern is received. A first data signal is generated using at least a portion of the values in the set of values, where the first data signal has a first frequency. A first series of latches and a second series of latches are used to extract alternating values of the at least portion of values from the first data signal, where the first series and second series of latches extract the alternating values at a second frequency that is a fraction of the first frequency. Outputs of the first and second series of latches are combined to generate a second data signal, where the second data signal has the first frequency.
IPC 8 full level
G01R 31/3185 (2006.01)
CPC (source: EP KR)
G01R 31/318547 (2013.01 - KR); G01R 31/318552 (2013.01 - EP KR); G01R 31/318555 (2013.01 - EP KR); G01R 31/318563 (2013.01 - EP KR); G01R 31/318575 (2013.01 - KR); G01R 31/318547 (2013.01 - EP); G01R 31/318575 (2013.01 - EP)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
Designated validation state (EPC)
KH MA MD TN
DOCDB simple family (publication)
WO 2023132825 A1 20230713; CN 118633029 A 20240910; EP 4232833 A1 20230830; KR 20240128091 A 20240823; TW 202329626 A 20230716
DOCDB simple family (application)
US 2022011310 W 20220105; CN 202280090941 A 20220105; EP 22701469 A 20220105; KR 20247026048 A 20220105; TW 111129538 A 20220805