Global Patent Index - EP 4379781 A1

EP 4379781 A1 20240605 - METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

Title (en)

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

Title (de)

VERFAHREN ZUR HERSTELLUNG VON HALBLEITERBAUELEMENTEN UND ZUGEHÖRIGES HALBLEITERBAUELEMENT

Title (fr)

PROCÉDÉ DE FABRICATION DE DISPOSITIFS SEMI-CONDUCTEURS ET DISPOSITIF SEMI-CONDUCTEUR CORRESPONDANT

Publication

EP 4379781 A1 20240605 (EN)

Application

EP 23212509 A 20231128

Priority

IT 202200024642 A 20221130

Abstract (en)

One or more semiconductor dice (14) are arranged on a die pad (12A) of a leadframe (12) having an array of electrically conductive leads (12B) around the die pad (12A). A pattern of electrically conductive wires (16) is provided to couple the semiconductor die or dice (14) with electrically conductive leads (12B) in the array around the die pad (12A). An encapsulation of insulating material (18A, 18B) is provided to encapsulate the semiconductor die or dice (14) arranged on the die pad (12A) and the pattern of electrically conductive wires. Providing the encapsulation comprises:a first encapsulation step wherein a first mass of encapsulation material (18A) is transferred onto the semiconductor die or dice (14) arranged on the die pad (12A) and onto the pattern of electrically conductive wires (16) to form a core portion (100, 18A) of the encapsulation that fully encapsulates the die or dice (14) and the electrically conductive wires (16), that are thus retained in position by the first mass of encapsulation material (18A), anda second encapsulation step wherein a second mass of encapsulation material (18B) is molded onto the core portion (100, 18A) of the encapsulation to provide a shell portion (200, 18B) of the encapsulation around the core portion (100, 18A) of the encapsulation.

IPC 8 full level

H01L 21/56 (2006.01); H01L 23/31 (2006.01)

CPC (source: CN EP US)

H01L 21/4825 (2013.01 - US); H01L 21/56 (2013.01 - CN EP); H01L 21/566 (2013.01 - EP US); H01L 23/24 (2013.01 - CN); H01L 23/3107 (2013.01 - EP US); H01L 23/3121 (2013.01 - CN); H01L 23/3135 (2013.01 - CN EP); H01L 23/49503 (2013.01 - US); H01L 23/4952 (2013.01 - US); H01L 24/46 (2013.01 - EP)

Citation (applicant)

  • L.ROTH ET AL.: "Wire Encapsulation Improves Fine-Pitch Device Yield", SEMICONDUCTOR INTERNATIONAL, vol. 27, no. 11, October 2004 (2004-10-01)
  • Y.F. YAO ET AL.: "New encapsulation development for fine pitch IC devices", MICROELECTRONICS, vol. 45, 2005, pages 1222 - 1229, XP004935797, DOI: 10.1016/j.microrel.2004.10.008
  • P. SERRA ET AL.: "Laser-Induced Forward Transfer: Fundamentals and Applications", ADVANCED MATERIALS TECHNOLOGIES, vol. 4

Citation (search report)

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC ME MK MT NL NO PL PT RO RS SE SI SK SM TR

Designated extension state (EPC)

BA

Designated validation state (EPC)

KH MA MD TN

DOCDB simple family (publication)

EP 4379781 A1 20240605; CN 118116813 A 20240531; US 2024178007 A1 20240530

DOCDB simple family (application)

EP 23212509 A 20231128; CN 202311619391 A 20231130; US 202318516745 A 20231121