Electronic organs have been known for years. Early electronic organs used various electrical mechanical devices for generating electrical oscillations corresponding to musical tones. Various types of electronic oscillators have also been used to provide such oscillations. Some organs have used an independent oscillator or generator for each tone. In the past the use of such independent oscillators have been quite expensive, and for cost saving reasons it has become common practice to provide twelve oscillators to provide the semi tones of the top octaves, and to use divide-by-two circuits to provide the tones in lower octaves. More recently it has beocme well known to use a singel radio frequency oscillator with divider circuits of different divider ratios to produce the top octave of tones. This system is sometines known as a top octave synthesizer (TOS). Strings of divide-by-two circuits ahve been used to provide the__notes in lower octaves of the organs.
With the advent of reliable large scale integrated circuits (LSI) chips efforts have been made to construct electronic organs utilizing digital techniques akin to those used in computers. It is relatively simple to construct LSI chips that will handle digital techniques whereas it is relatively very difficult to utilize analog technuques with such SLI chips.
Digital type circuits can readily be adapted to produce output waves of 50% duty cycle having a rectangular wave shape.
An output of this type is well adapted to producing reed tones such as those of a clarinet. However, only the odd harmonics are present, and various schemes have been adopted for combining waves to provide the missing harmonics. In a case of flute tones there are substantially no harmonics. Otherwise stated, the tones of a flute are substantially pure sine waves. Square waves (50% duty cycle rectangular waves), can be filtered to remove the harmonics. Filtering on a note-by-note basis would produce excellent flute tones, but the expense would be very high. Filtering a large number of output waves at the same time is very inefficient in producing proper flute tones. Keys near the upper corner frequency of a filter will produce excellent flute tones, while those toward the center and lower corner of the pass band of the filter will have progressively more harmonics, and thus be poor flute tones.
It is an object of the present invention to provide an electronic organ or the like with a plurality of LSI chips, each of which has six frequency generators that can be assigned to desired keys on the keyboard, there being enough of such chips connected seriatim so that the outputs of each chip are restricted to half octave, whereby very effective filtering for flute tones can be implemented.
In a practical utilizaiton of the foregoing and other objects of the present invention an electronic organ is produced on a modular, expandable basis utilizing a plurality of integrated circuit chips of similar and of diverse characteristics in combination with multiplexing of the organ keyboards. Multiplexing is utilized in computers and generally in digital type organs to eliminate redundancy of frequency generators and of wiring. This is utilized to a large extent in the modular organ now under consideration. However, in a specific embodiment, redundancy is deliberately utilized to produce one chip for each half octave of the entire organ gamut, and there are six oscillators or frequency generators per chip. Thus, the number of frequency generators is equal to, and in may even exceed the number of keys on an organ keyboard with which the system of chips is connected. Accordingly, output frequencies are grouped in half octaves, whereby very effective filtering thereof to produce excellent flute tones can be effected.
The principles of the present invention and implementation thereof will best be understood with reference to the following specificaton and to the accompanying drawings, wherein:
Fig. 1 comprises a block diagram illustrating the congregation of chips forming the subject matter of the present invention; and
Fig. 2 is a block diagram illustrating certain characteristics of the present LSI chip.
Fig. 3 is a circuit diagram showing steering of the serial data line to effect half octave per chip tone generation.
The present invention represents a portion of a modular, expandable organ system disclosed and claimed in the copending patent application of Harold 0. Schwartz, Dennis E. Kidd, and William R. Hoskinson filed on June 20, 1978, under SN 917,310 (attorney's docket number 688E). The present application related to the B-1 chip shown in the aforesaid application. It is similar to the B-4 chip shown in the application just identified and specifically disclosed and claimed in Harold 0. Schwartz and William R. Hoskinson's patent application filed June 20, 1978 under SN 917, 314 (attorney's docket number 688J), and partakes of some of the principles of the B-2 chip specifically disclosed 'and claimed in the copending application of Harold 0. Schwartz and Dennis E. Kidd filed on June 20, 1978 under SN 917,313 (attorney's docket number 6881).
A plurality of like B-1 chips is shown in Fig. 1 and respectively identified with even numbers 10 through 30. ,Eleven of the chips are shown in combination, since for one half octave a piece it will take eleven chips to provide sixty-six notes, sufficient to cover a full organ sixty-one note keyboard. Obviously, lesser numbers could be used for spinet organs of forty-four or thirty-seven keys. Indeed, if one wished to sacrifice the half octave filtering of flute tones, one chip could suffice for an entire octave of an organ keyboard, since each tone generator on the chip is capable of being tuned to produce a.proper frequency for any note in an octave span of keyboard. Each chip receives serial data in from the multiplexed keyboard at 32 by way of a 1/2 octave assignor 52 and leads 32a and 32b, respectively. A system strobe signal is applied at 34 to the first B-1 chip 10 and also to the number 7 chip which is assigned to the second half octave of which chip number 1 comprises the first half. This acts to identify the chips 10 and 22 as the first chips in the cascaded systems. The manner in which this is done is explained in some detail in the aforesaid application of Harold 0. Schwartz and Dennis E. Kidd (attorney's docket number 6881). After one count a signal is passed over a conductor 36 from a position-out pin on the first chip 10 to the position-in pin on the second chip 12. This continues seriatim for each octave of chips to assign each chip its place in the cascade.
Additional circuitry as shown in Fig. 3 and hereinafter to be described assigns each chip to half octave of keyboard information. Each chip has additional input information as will be set forth hereinafter with regard to Fig. 2. Each chip also has an output at 38 which actually comprises a plurality of outputs as set forth hereinafter to accompanying sets of filters 40 for filtering in half octave groups of tones. Each of the_filters 40 has an output at 42 to a common output line 44 leading to an amplifier 46 and a loud speaker 48.
In Fig. 2 certain of the aspects of the chips are illus---- trated, specifically the chip 10 being shown, although the others are identical. The chip has on it six frequency generators all identified by the numeral 50, but respectively indicated as generators -1 through 6. There are also eight keyers all numbered 54, but respectively identified as keyer number one through keyer number eight. The keyers receive proper frequency signals from a generator 50 and when activated key the signals out of the chip.
There are additional inputs to the chip over and above the serial data input at 32 previously mentioned. The system strobe 34 keys each and every chip in the organ system at the start of a keyboard scan to assure proper timed operation of all parts of the organ. A data clock input also is provided at 58. The data clock operates a multiplexing circuit, and therefore insures proper timed operation of the chip with the multiplexed serial data. There is a high frequency input at 60 accompanied by an adjacent drop clock input 62. The use of the drop clock in conjunction with the high frequency clock to avoid locking of generators together is set forth in full in the copending application of Anthony C. Ipplito and William R. Hoskinson filed June 20, 1978 under SN 917,296 (attorney's docket number 688K). In very brief summary, the drop clock operates at a much lower frequency than the high frequency, and functions to drop a pulse from the high frequency every so often on order to detune each oscillator slightly form its nominal frequency, and each by a different amount.
There is a position-in input 64 as previously noted, which is the case of the first B-1 chip 10 and chip number 22 receives the system strobe to provide information that this is to be the first chip in the cascade. Subsequent chips receive a pulse delayed one count from a position-out connector 66. Each chip must be delayed one count from the preceding chip which operates with the one half octave assignor 52 to assign the chip to its proper frequency range. The manner in which the respective generators are assigned to different frequency outputs is disclosed in the copending Patent Application SN 917,313 filed June 20, 1978. The attack and decay of each generator is determined by the charge and discharge time of a plurality of six capacitors 68, one interconnected with each generator 50 as to one side or plate of each capacitor, the other sides or plates being connected to ground at 70. It will be understood that the reference to "ground" deos not necessarily mean exactly zero potential, since it is common practice in the integrated circuits arts to use a fixed potential which may be above or below zero, but which acts as a reference, and therefore is conveniently referred to as ground. The manner in which attack and decay is produced is set forth fully in the copending application of William R. Hoskinson filed June 20, 1978 under SN 917,308 (attorney's docket number 688B). An attack clock input 72 and a decay clock input 74 are provided for the chip. In very brief summary the time in which a capacitor charges is determined by the duty cycle of the attack clock, while the discharge time is determined by the duty cycle of the decay clock. This is user settable as to duty cycle, and in other-instances it is possilbe to have different attack and decay characteristics for different generators on the same chip. However, in the present instance then is only one attack clock, whereby all of the frequencies from the chip attack and decay exactly the same.
The chip also is provided with a plurality of outputs. There is a sixteen foot output at 76, an eight foot output at 78, and a five and one third foot output 80, a four foot output 82, and a two and two thirds output 84, and a two foot output 86, and one and one third output 88 and a one foot output 90. All of the outputs are 50% duty cycle rectangular waveforms.
The one-half octave assignor 52 is shown in detail in Fig. 3. The data clock 58 is connected through a resistor 92 to the base of an N-P-N transistor 94. The emitter of the transistor 94 is connected to ground, while the collector is connected through a resistor 96 to positive potential. The emitter also .is connected to the "clock A" input of a divide-by-six counter 98 known comercially as number 7492. Output A of the counter 98 is connected by a conductor 100 to the "clock B" input. System storbe 34 is connected through a resistor 102 to the base of another NPN transistor 104, the emitter thereof being grounded. The collector is connected through a resistor 106 to positive potential, and also is connected to the reset input of the counter 98.
The D output of the counter 98 is connected through a resistor 108 to the base of another NPN transistor 110. The emitter of this transistor is grounded and the collector is connected through a resistor 112 to a positive voltage. The collector is also connected to a line 114 which is connected directly to one input of an OR gate 116. The line 114 also is connected through an inverter 115 to one input of a second OR gate 118. MUX G is connected at 117 as the second input of each of the OR gates 116 and 118. Output line 120 from the OR gate 116 is connected as one input to an AND gate 124, while the output line 122 of the OR gate 118 is connected as one input ot an AND gate 126. The output lines 32A and 32B, respectively, are connected to the number 1 and number 7 B-1 chip as heretofore set forth in connection with Fig. 1.
The divide-by-six counter 98 is reset by systems strobe 34 and counts by sixes with the D output thereof alternating on the rising edge of each sixth data clock pulse. The D output is used to allow alternately the passage of serial data through and AND gates. When MUX G goes high at count 64 then the serial data, which is now chip control information rather than keyboard data, is passed to both sets of chips.
Seven multiplexed outputs are provided for the entire system, including keyboards, pedal board, and stop tablets. 27
provides 128 counts for the system. "MUX G" is the most significant bit from count 0 to count 63 MUX G equals 0. From count 64 through count 127 MUX G equals 1. Thus, output from the OR gates 116 and 118 is alternatively controlled.
The present chip is valuable in that with the proper input frequency on the order of 3 MHz the mutation stops indicated are produced. The chip is of particular im- partance in having six generators thereof, so that with the proper number of chips, one per half octave, the frequencies can be filtered by half octave groups to afford a very high quality of flute tone. It will also be appreciated that half the number of chips could be provided, e.g., one per octave, in which case there would be six notes per octave. This would provide enough notes per octave for the playing of any music, while the filtering would have to be on an octave group, and much less effective than a half octave group.
Various changes from the illustrative embodiment of the invention will no doubt occur to those skilled in the art, and will be understood as forming a part of the present invention insofar as they fall within the spirit and scope of the appended claims.
NaN. 1. In an organ or the like having a keyboard with a plurality of key switches characterized in the provision of a plurality of frequency generators (50) each capable of producing a frequency corresponding to any note within a given range of notes, means (32) interconnected with said key switches and said frequency generators to cause said generators to operate at particular frequencies within the given range, and means (54) connected to said frequency generators for keying the frequencies generated out of said chip.
NaN. 2. The organ as set forth in claim 1 further characterized in the provision of a plurality of like LSI chips (10-30) of the type set forth in claim 1 and each comprising six frequency generators (e.g. 50) each of which is capable of producing a frequency corresponding to any note on the keyboard, means (52) assigning the generators of each chip to production of notes in a given half octave group of notes, and a plurality of filters (40) respectively connected to each of said chips for filtering frequencies in one-half octave groups.
NaN. 3. The organ set forth in claim 1 and further characterized in the provision of a first plurality of like LSI chips (10-20) of the type set forth in claim 1 and a second plurality of like LSI chips (22-30) of the type set forth in claim 1, each chip comprising six frequency generators each of which is capable of producing a frequency corresponding to any note on the keyboard, external means comprising data clock means (58) and means (34) supplying a strobe signal simultaneously to the first chip (10) of said first plurality of chips (10-20) and to the first chip (22) of said second plurality of chips (22-30) external connecting means (e.g. 36) interconnecting seriatim said first chip (10;22) and successive chips (12-20; 24-30) of said first plurality of chips (10-20) and of said second plurality of chips (22-30) respectively, each chip having means (64,66) for delaying said strobe signal by one count of said data clock means said delaying means being connected to said external interconnecting means (e.g. 36) whereby successive chips are strobed-successively, means (52) assigning the generators of each chip to a half octave group of notes, and a plurality of filters (40) respectively connected to each of said chips (10-30) for filtering frequencies in one-half octave groups.
NaN. 4. The organ set forth in claim 3, further characterized in that the means (52) assigning the generators of each chip to a half octave group of notes comprises a pair of logic gates (124, 126) having outputs respectively connected to said first plurality of chips (10-20) and to said second plurality of chips (22-30), said gates (124,126) each having a first input (32) for receiving multiplexed serial data from the organ key switches, and a second input (120,122) connected to the output of one of a second pair of logic gates (116,118) having inputs coupled to a counter (98) controlled by a data clock (58) and by a source (117) providing either a 0 or a 1 depending on the. count within a multiplexed scan.
NaN. 5. The organ set forth in claim 4 further characterized- in that the second pair of logic gates (116,118) comprise a pair of OR gates each having two inputs, one input of each OR gate being coupled to means (114,115) causing one such input to be at a logic 1 level while the other is at a logic 0 level; the other input of each of said OR getes being connected in common to the source (117) providing either a logic 0 or a logic 1 depending on the count position in a multiplex scan, and that the first pair of logic gates (124,126) comprises a pair of AND gates each having at least two inputs, one input of each AND gate being connected in common to serial data (32) from multiplexed keyboard means, a second input of each AND gate being respectively connected to the outputs (120,122) of said OR gates (116,118) and each of said AND (124,126) gates having an output (32a,32b).