(19)
(11)EP 2 372 323 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
03.08.2016 Bulletin 2016/31

(21)Application number: 11250336.2

(22)Date of filing:  18.03.2011
(51)International Patent Classification (IPC): 
G01J 1/46(2006.01)
H04N 5/33(2006.01)

(54)

Light sensor circuit and driving method thereof

Lichtsensorschaltung und Ansteuerungsverfahren dafür

Circuit de capteur de lumière et son procédé de commande


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 23.03.2010 KR 20100025659

(43)Date of publication of application:
05.10.2011 Bulletin 2011/40

(73)Proprietor: Samsung Display Co., Ltd.
Gyeonggi-do (KR)

(72)Inventors:
  • Kim, Do-Youb
    Gyunggi-Do 446-711 (KR)
  • Park, Yong-Sung
    Gyunggi-Do 446-711 (KR)
  • Kim, Tae-Jin
    Gyunggi-Do 446-711 (KR)
  • Choi , Deok-Young
    Gyunggi-Do 446-711 (KR)
  • Jeong, Joo-Hyeon
    Gyunggi-Do 446-711 (KR)
  • Ahn, Soon-Sung
    Gyunggi-Do 446-711 (KR)
  • Choi, In-Ho
    Gyunggi-Do 446-711 (KR)
  • Jang, Brent
    Gyunggi-Do 446-711 (KR)
  • Im, Ki-Ju
    Gyunggi-Do 446-711 (KR)

(74)Representative: Mounteney, Simon James 
Marks & Clerk LLP 90 Long Acre
London WC2E 9RA
London WC2E 9RA (GB)


(56)References cited: : 
EP-A2- 1 939 847
US-A1- 2005 269 487
EP-A2- 1 940 161
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND


    1. Field



    [0001] The invention relates to a light sensor circuit, particularly a light sensor circuit that expands the range of sensible ambient light and improves resolution at low illumination, and a method of driving the light sensor circuit.

    2. Description of the Related Art



    [0002] Flat panel displays include organic light emitting displays, liquid crystal displays, and plasma displays, etc. Flat panel displays are thinner, lighter, and consume less power than CRTs (Cathode Ray Tube), such that they have rapidly replaced the CRTs. Of the flat panel displays, organic light emitting displays and liquid crystal displays can be easily manufactured in a small size and can be used for a long period of time with a battery, such that they are selected for the display of many portable electronic devices.

    [0003] However, although a user can adjust the brightness of existing organic light emitting displays and liquid crystal displays, these displays are designed to display images at a uniform luminance irrespective of ambient light. Therefore, visibility for these displays is an issue, because the uniform luminance appears too high in a dark place and too low in a bright place, e.g., in sunlight.

    [0004] Further, since flat panel displays are set to be uniform in luminance of a picture in the related art as described above, they are disadvantageous in that the luminance of a picture is unnecessarily high and accordingly power consumption increases, when being used for a long period of time in a relatively dark place with relatively small luminance of ambient light. In order to overcome this issue, some displays may automatically adjust luminance by sensing ambient light using a light sensor circuit.

    [0005] EP1940161 discloses a light sensor circuit, comprising a first transistor having first and second electrodes and a gate electrode; a first switch having a first terminal connected to the gate electrode of the first transistor and a second terminal connected to the second electrode of the first transistor, the first switch being controlled by a first control signal; a second switch having a first terminal connected to a first reference voltage and a second terminal connected to the first electrode of the first transistor, the second switch being controlled by a second control signal; a third switch having a first terminal connected to the second electrode of the first transistor and a second electrode connected to a second reference voltage, the third switch being controlled by an inverted second control signal; a light receiving element having an anode connected to the second reference voltage; a first capacitor having a first and a second electrode, the second electrode connected to the second reference voltage; a fourth switch having a first terminal connected to the cathode of the light receiving element and a second electrode connected to the first electrode of the first capacitor, the fourth switch being controlled by a third control signal; and a second capacitor connected between the gate electrode of the first transistor and the first electrode of the first capacitor via a fifth switch.

    SUMMARY



    [0006] The present invention provides a light sensor circuit according to claim 1.

    [0007] The light sensor circuit may include a seventh transistor connected between the first electrode of the first transistor and a first side of an output load, the seventh transistor including a gate electrode receiving a fourth control signal, and an eighth transistor connected between an output signal line extending to a second side of the output load and the first power source, the eighth transistor including a gate electrode receiving an initializing signal.

    [0008] The light receiving element may be any one of a p-i-m(p-intrinsic-metal) diode, a PIN diode, a PN diode, and a photo coupler.

    [0009] The first reference voltage and the second reference voltage may have a high-level voltage value.

    [0010] The third reference voltage VREF3 and the second power source VSS may be implemented by low-level voltage or a grounding power source GND.

    [0011] At least one of the second transistor, the fifth transistor, and the sixth transistor may be a dual gate type.

    [0012] The light sensor circuit may include a ninth transistor supplied with the first control signal inverted by the gate electrode, the ninth transistor having first and second electrodes connected with the gate electrode of eh first transistor, and a tenth transistor supplied with a third control signal inverted by the gate electrode, the tenth transistor having first and second electrodes connected with a first electrode of the first capacitor.

    [0013] A further aspect of the invention provides a method according to claim 8 of driving a light sensor circuit according to claim 1.

    [0014] Implementing the light receiving element may include receiving a first control signal as a selection signal, initializing the voltage of a gate electrode node of the first transistor into a second power source, and after initializing the voltage, receiving the first control signal and a second control signal as selection signal, and charging the gate electrode node of the first transistor with "first reference voltage - threshold voltage of the first transistor".

    [0015] Discharging the first capacitor may include providing a third control signal as a selection signal to turn on a sixth transistor to then correspondingly decrease the voltage of the gate electrode node of the first transistor is by up to the amount of voltage change of the first capacitor.

    [0016] Discharging the first capacitor may further include receiving an initializing signal as a selection signal and turning on an eighth transistor in a predetermined period of the second period, and then charging an output line with a first power source.

    [0017] Outputting information may include providing a fourth signal as a selection signal to turn on a seventh transistor is turned on to then discharge the voltage in accordance with the light leakage current is output to an output signal line through the seventh transistor.

    [0018] Embodiments of the invention provide a method of driving a light sensor circuit in which one frame is composed of a plurality of sub-frames, the sub-frames are divided into three periods t1, t2, and t3 and the light sensor circuit according to claim 1 operates in the periods, the method including implementing a light receiving element in a reverse bias state by storing threshold voltage of a first transistor in a second capacitor and charging the cathode of the light receiving element to second reference voltage in the first period, discharging the first capacitor, which stores voltage by the light leakage current generated in accordance with the amount of light traveling into the light receiving element, to correspond to light leakage current in the second period, and outputting information on the voltage discharged in accordance with the light leakage current to an output signal line in the third period, wherein the second period of each of the sub-frame is sequentially shortened by a multiple of 2 from a second period time T0 of the first sub-frame.

    [0019] Low-luminance light may be sensed in the first sub-frame having the longest second period and high-luminance light is sensed in the last sub-frame having the shortest second period.

    [0020] Implementing the light receiving element in a reverse bias state may include receiving a first control signal as a selection signal, initializing the voltage of a gate electrode node of the first transistor into a second power source, receiving the first control signal and a second control signal as selection signals after initializing, and charging the gate electrode node of the first transistor with "first reference voltage-threshold voltage of the first transistor."

    [0021] Discharging the first capacitor may include providing a third control signal as a selection signal to turn on a sixth transistor is turned on then to decrease the voltage of the gate electrode node of the first transistor by up to the amount of voltage change of the first capacitor.

    [0022] Discharging the first capacitor may further include receiving an initializing signal as a selection signal to turn on an eighth transistor in a predetermined period of the second period, and then charging an output line with a first power source.

    [0023] Outputting information may include providing a fourth signal as a selection signal to turn on a seventh transistor is turned on, and then the voltage discharged in accordance with the light leakage current is output to an output signal line through the seventh transistor.

    [0024] Embodiments of the invention provide a method of sensing light using a light sensor circuit including providing another light sensor circuit, shielding the another light sensor circuit from light, and subtracting an output of the another light sensor circuit from an output of the light sensor circuit to provide a corrected output.

    [0025] At least some of the above and other features of the invention are set out in the claims.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0026] The above and other features and advantages will become more apparent to those of ordinary skill in the art upon making reference to the following embodiments of the invention which are described with reference to the attached drawings, in which:

    FIG. 1A and FIG. 1B illustrate circuit diagrams of the configuration of light sensor circuit according to embodiments of the invention;

    FIG. 2 illustrates a timing diagram showing the operation of the light sensor circuit shown in FIGS. 1A or 1B; and

    FIG. 3 illustrates a timing diagram showing the operation of a light sensor circuit according to another embodiment of the invention.


    DETAILED DESCRIPTION



    [0027] Embodiments of the inventionwill now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

    [0028] FIG. 1A and FIG. 1B illustrate circuit diagrams of a light sensor circuit according to the invention. This light sensor circuit is a source follower type of sensor circuit, which has the advantage of having good linear input/output characteristics.

    [0029] Referring to FIG. 1A first, the light sensor circuit according includes first to eighth transistors P1 to P8, first and second capacitors C1 and C2, and a light receiving element PD. While the first to eighth transistors P1 to P8 were implemented as P-type transistors in this embodiment of the present invention, this is just one example and embodiments are not limited thereto.

    [0030] The first transistor P1 has a gate electrode connected to a first node N1 and first and second electrodes are electrically connected to a first reference voltage VREF1 and a second power source VSS, respectively. In this configuration, the first reference voltage VREF1 is a high-level voltage value and the second power source VSS is implemented by a low-level voltage value or a ground power source GND. In this embodiment, the first transistor P1 operates in a source follower type, in which the first electrode electrically connected with the first reference voltage VREF1 serves as a source electrode and the second electrode connected with the second power source VSS serves as a drain electrode.

    [0031] The second transistor P2 is connected between the gate electrode and the second electrode (drain electrode) of the first transistor P1, such that when the second transistor P2 is turned on, the first transistor P1 is diode connected. In particular, first and second electrodes of the second transistor P2 are connected with the gate electrode and the second electrode of the first transistor P1, respectively. A gate electrode of the second transistor P2 is connected with a first control signal line CS1.

    [0032] A third transistor P3 is connected between the first electrode (source electrode) of the first transistor P1 and the first reference voltage VREF1, such that when the third transistor P3 is turned on, the first electrode of the first transistor P1 is electrically connected with the first reference voltage VREF1. In particular, first and second electrodes of the third transistor P3 are connected with the reference voltage and the first electrode of the first transistor, respectively. A gate electrode of the third transistor P3 is connected with a second control signal line CS2.

    [0033] A fourth transistor P4 is connected between the second electrode (drain electrode) of the first transistor P1 and the second power source VSS, such that when the fourth transistor P4 is turned on, the second electrode of the first transistor P1 is electrically connected with the second power source VSS. In particular, first and second electrodes of the fourth transistor P4 are connected with the second electrode of the first transistor and the second power source VSS. A gate electrode of the fourth transistor P4 is connected with a second control signal line CS2b. In this configuration, the control signal applied to the second control signal line CS2, is inverted and transmitted to the 2-2 control signal line CS2b.

    [0034] The light receiving element PD is connected between a second reference voltage VREF2 and a third reference voltage VREF3, and discharges the second capacitor C2 to a predetermined voltage by flowing light leakage current corresponding to the magnitude of external light in reverse bias. In particular, a cathode of the light receiving element PD is electrically connected with the second reference voltage VREF2 and an anode of the light receiving element PD is connected with the third reference voltage VREF3.

    [0035] A fifth transistor P5 is connected between the cathode of the light receiving element PD and the second reference voltage VREF2, such that the cathode of the light receiving element PD is electrically connected with the second reference voltage VREF2 only when the fifth transistor P5 is turned on. In particular, first and second electrodes of the fifth transistor P5 are connected with the second reference voltage VREF2 and the cathode of the light receiving element PD, respectively. A gate electrode of the fifth transistor P5 is connected with the first control signal line CS1.

    [0036] The light receiving element PD may be any one selected from a p-i-m (p-intrinsic-metal) diode, a PIN diode, a PN diode, a photo coupler, and an equivalent. The second reference voltage VREF2 is a high-level voltage value and the second power source VSS is may be implemented by a low-level voltage value or a ground power source GND.

    [0037] The second capacitor C2 stores the voltage applied to the gate electrode of the first transistor P1, such that it compensates the threshold voltage of the first transistor P1. Therefore, the first electrode of the second capacitor C2 is connected with the first node N1, where the gate electrode of the first transistor P1 is connected, and the second electrode is connected with the second node N2.

    [0038] The first capacitor C1 is connected between the second node N2 and the third reference voltage VREF3. The first capacitor C1 is connected in parallel with the light receiving element PD and improves signal maintaining characteristics by improving the reverse bias capacity of the light receiving element. In particular, the first electrode of the first capacitor C1 is electrically connected with the cathode electrode of the light receiving element PD and the second electrode is connected with the anode electrode.

    [0039] A sixth transistor P6 is connected between the cathode of the light receiving element PD and the first electrode of the first capacitor C1, such that the cathode of the light receiving element PD is electrically connected with the first electrode of the first capacitor C1, only when the sixth transistor P6 is turned on. In particular, first and second electrodes of the sixth transistor P6 are connected with the cathode of the light receiving element PD and the second node N2, respectively. A gate electrode of the sixth transistor P6 is connected with a third control signal line CS3.

    [0040] A seventh transistor P7 has first and second electrodes connected between the first electrode of the first transistor P1 and one side of an output load, and a gate electrode of the seventh transistor P7 is connected with a fourth control signal line CS4.

    [0041] An eighth transistor P8 is connected to an output signal line OUT extending to the other side of the output load, in which a first electrode of the eighth transistor P8 is connected to the output signal line OUT, a second electrode is connected with a first power source VDD having a high-level voltage value, and a gate electrode is connected to an initializing signal line pre.

    [0042] In this configuration, the output load may be, e.g., an internal load of an analog-digital converter. In this configuration, all of the first reference voltage VREF1, the second reference voltage VREF2, and the first power source VDD have a high-level voltage value and can be implemented at the same level. In this configuration, both the third reference voltage VREF3 and the second power source VSS are implemented by a low level or a ground power source and may have the same voltage value.

    [0043] Next, referring to FIG. 1B, a light sensor circuit according to another embodiment of the invention is shown. The embodiment of FIG. 1B includes all of the elements of the embodiment shown in FIG. 1A. Therefore, the same components are represented by the same reference numeral and detailed description of them is not repeated.

    [0044] In particular, the embodiment shown in FIG. 1B is different from the embodiment shown in FIG. 1A in that a ninth transistor P9 and a tenth transistor P10 are further included, and the second transistor P2, the fifth transistor P5, and the sixth transistor P6 are implemented in a dual gate type.

    [0045] In this configuration, the ninth transistor P9 and the tenth transistor P10 are provided to reduce switching noise generated by the second transistor P2 and the sixth transistor P6, respectively. Therefore, the ninth transistor P9 has a gate electrode connected to a first control signal line CS1b to which an inverted first control signal is applied, and first and second electrode connected to the first node N1. Further, the tenth transistor P10 has a gate electrode connected to a third control signal line CS3b to which an inverted third control signal is applied, and first and second electrodes connected to the second node N2.

    [0046] Since the switching noise generated by the second transistor P2 and the sixth transistor P6 may largely influence the gate electrode of the first transistor P1, in order to overcome this problem, the ninth transistor P9 and the tenth transistor P10 connected with the first and second electrodes (source and drain electrodes) are provided to minimize the switching noise.

    [0047] Further, the second transistor P2 and the sixth transistor P6 are implemented in a dual gate type to prevent the leakage current generated from each of the transistors itself from influencing the gate node of the first transistor P1, and the fifth transistor P5 is implemented in a dual gate type to prevent the leakage current of itself from influencing the light leakage current generated from the light receiving element PD.

    [0048] Otherwise, the basic operations of the light sensing operations the embodiments shown in FIG. 1A and FIG. 1B are generally the same.

    [0049] FIG. 2 is a timing diagram for illustrating the operation of the light sensor circuit shown in FIG. 1A.

    [0050] Since the transistors included in the light sensor circuit shown in FIG. 1A are implemented as P-type transistors, control signals, selection signals turning on the transistors, are applied at a low level. In contrast, when the transistors are implemented as N-type transistors, they would be turned on when the control signals are applied as selection signals at a high level.

    [0051] As shown in FIG. 2, a light sensor circuit according to this embodiment of operates in by dividing a period of one frame into three periods t1, t2, and t3. In this configuration, the gate electrode of the first transistor P1 is initialized in the first period (t1, Reset), changes in light due to the light receiving element PD is sensed in the second period (t2, Integration), and voltage values changed by sensing the light is output through an output terminal in the third period (t3, Readout).

    [0052] In this configuration, first to fourth control signals CS1 to CS4 and an initial signal pre, first to third reference voltages VREF1, VREF2, and VREF3 and first power source VDD, and a second power source VSS are applied to the light sensor circuit, respectively, in order to achieve the above operations in the periods t1, t2, and t3.

    [0053] In this configuration, the first and second reference voltages VREF1, VREF2 and the first power source VDD have a high-level voltage value, and the third reference voltage VREF3 and the second power source VSS may have a low-level voltage value or may be by a grounding power source. All of the high-level voltage value and both of the low-level voltage values may be set at the same level, respectively.

    [0054] The first period t1 may be divided into a 1-1 period t1-1 and a 1-2 period tl-2. During the 1-1 period t1-1, the first control signal CS1 is provided at a low level and the second control signal CS2 is provided at a high level. During the 1-2 period t1-2, the first and second control signals CS1 and CS2 are both provided at a low level, or the first control signal CS1 is provided at a high level and the second control signal CS2 is provided at a low level.

    [0055] In the 1-1 period t1-1, since the first control signal CS1 is applied at a low level, the second transistor P2 and the fifth transistor P5 are turned on. In the 1-1 period t1-1, since the second control signal CS2 is applied at a high level, the third transistor P3 is turned off. In the 1-1 period t1-1, since an inverted second control signal CS2b is applied to the fourth transistor P4, the fourth transistor P4 is turned on.

    [0056] As the second transistor P2 and the fourth transistor P4 are turned on, the gate electrode node of the first transistor P1, i.e., the first node N1, is discharged to the second power source VSS. Further, as the fifth transistor P5 is turned on, the cathode electrode of the light receiving element PD is charged to the second reference voltage VREF2.

    [0057] Thereafter, in the 1-2 period t1-2, since the second controls signal CS2 is applied at a low level, the inverted second control signal CSb becomes at a high level, such that the fourth transistor P4 is turned off and the third transistor P3 is turned on. Accordingly, the gate electrode node of the first transistor P1 is charged to a voltage of "first reference voltage VREF1 - threshold voltage of the first transistor VTH, P1".

    [0058] In other words, the gate electrode of the first transistor P1 is gradually increased from the second power source VSS by the source follower operation and charged up to the voltage "VREF1 - VTH, P1".

    [0059] Therefore, the second node N2 is charged to the second reference voltage VREF2 and the first node N1 is charged to "first reference voltage VREF1 - threshold voltage of the first transistor VTH, P1", and the second capacitor C2 connected between the first node N1 and the second node N2 is charged with the voltage corresponding to the difference voltage.

    [0060] Further, the first capacitor C1 connected between the second node N2 and the third reference voltage VREF3 is charged with voltage of "VREF2- VREF3".

    [0061] Next, in the second period t2, the third control signal CS3 is applied at a low level and the other control signals are all applied at a high level. In other words, only the sixth transistor P6 is turned on and the other transistors are all turned off.

    [0062] In this configuration, since the cathode electrode of the light receiving element PD was charged to the high-level second reference voltage VREF2 in the first period, the light receiving element PD operates in a reverse bias state. Therefore, the voltage stored in the first capacitor C1 by the light leakage current generated in accordance with the amount of light traveling into the light receiving element PD is discharged as much as the light leakage current.

    [0063] Further, since the sixth transistor P6 is turned on, the cathode electrode of the light receiving element PD is connected with the gate electrode of the first transistor P1 through the second capacitor C2, such that the voltage of the gage electrode node N1 of the first transistor P1 reduces as much as the amount of voltage change of the first capacitor C1.

    [0064] Assuming that the voltage discharged corresponding to the light leakage current is ΔV, the voltage of the gate electrode node N1 of the first transistor reduces to "VREF1 - VTH, P1 -ΔV". However, ΔV changes in accordance with the brightness of ambient light and the time of the second period t2.

    [0065] Further, as shown in FIG. 2, a low-level initializing signal pre is applied to the gate electrode of the eighth transistor P8 at a specific period before the second period t2 is finished, and accordingly, the eighth transistor P8 is turned on and the output signal line OUT is charged by the high-level first power source VDD. The time point where the low-level initializing signal pre is applied may be a predetermined period within the second period t2. As the example shown in FIG. 2, this embodiment exemplifies when the initializing signal is applied at the later half period of the second period t2.

    [0066] After the output signal line OUT is charged to VDD, during the third period t3, the third control signal CS3 is applied at a high level and the fourth control signal CS4 is applied at a low level. (third period t3). Accordingly, the sixth transistor P6 is turned off and the seventh transistor P7 is turned on.

    [0067] Further, since the first transistor P1, as described above, operates in the source follower type, as the seventh transistor P7 is turned on, the first electrode (source electrode) of the first transistor P1 is connected with the output signal line OUT through the seventh transistor P7, and as described above, the output signal line has been charged by VDD. In other words, the voltage applied to the gate electrode of the first transistor P1, that is, VREF1 - VTH, P1 -ΔV is lower than the voltage VDD of the source electrode, such that it is turned on.

    [0068] In this state, since the first transistor P1 operates in the source follower type, the output signal line is discharged up to VG,P1 + VTH, P1 and the VG,P1 is VREF1 - VTH, P1-ΔV. As a result, VREF1 -ΔV with the threshold voltage VTH, P1 of the first transistor P1 compensated is transmitted to the output signal.

    [0069] Further, since ΔV may be changed due to the light leakage current during the third period t3 where the output voltage is transmitted, as described above, it is possible to remove the influence from the light leakage current by keeping the sixth transistor P6 turned off.

    [0070] However, the electric signal output from the source follower type of light sensor circuit is Δ, which limits the range of ambient light that can be sensed by a predetermined Integration time (second period) and the size of the first capacitor C1.

    [0071] ΔV can be expressed by

    where IPHOTO is light leakage current and t2 is Integration time (second period).

    [0072] In other words, when the first capacitor C1 has large electrostatic capacitance or the Integration time (second period) decreases, it is possible to sense high-luminance ambient light, whereas the resolution of sensed signals decreases in low-luminance ambient. On the contrary, when the first capacitor C1 has low electrostatic capacitance or the Integration time (second period) increases, the resolution of sensed signals in low-luminance ambient light increases, whereas it is impossible to sense high-luminance ambient light.

    [0073] Further, although the source follower type of light sensor circuit has linear output characteristics, the light receiving element, e.g. p-i-m (p-intrinsic-metal diode), and the first capacitor C1 has non-linear discharge characteristics, such that non-linear output characteristics appear, depending on the luminance.

    [0074] Therefore, another embodiment proposes a multi-frame driving method to increase the range over which ambient light may be sensed and increase resolution at low luminance, by removing the disadvantages.

    [0075] FIG. 3 is a timing diagram illustrating the operation of a light sensor circuit according to another embodiment of the invention. The operation of the embodiment shown in FIG. 3 may be realized using the configuration of the light sensor circuit shown in FIG. 1A or FIG. 1B. Further, although five sub-frames are shown in FIG. 3, this is just an example, and embodiments are not limited thereto.

    [0076] Referring to FIG. 3, the multi-frame driving method performs m sub-frame operations for one frame period and implements the operations of the three periods (first period (t1, Reset), second period (t2, Integration), third period (t3, Readout)) described above for each sub-frame.

    [0077] In other words, while one frame in the embodiment shown in FIG. 2 has a fixed Integration time, the multi-frame driving method has m different Integration times. Within each sub-frame of FIG. 3, the three period of each sub-frame are the same as those described in association with FIG. 2.

    [0078] The Integration times (second period, t2) for sub-frames shown in FIG. 3 may differ for the previous sub-frame by a factor of two. That is, when the Integration time of the first sub-frame is To, the Integration time of the n-th sub-frame is



    [0079] In this configuration, low-luminance ambient light is sensed in the first sub-frame (SF1) period having the longest Integration time, while high-luminance ambient light is sensed in the fifth sub-frame (SF5) period having the shortest Integration time.

    [0080] According to the multi-frame method shown in FIG. 3, each of m sub-frames having different Integration times performs m Integrations for one frame period, such that it is possible to sense the magnitude of ambient light in a wide range, without saturation of output voltage, and maintain the resolution at a high level even in low-luminance ambient light. In addition, it is possible to output high-bit ambient light signals, using a low-bit ADC.

    [0081] Further, the analog signals output by the multi-frame driving method shown in FIG. 3 is interpolated by high-bit digital output through multiplication with an analog-digital converter ADC.

    [0082] In other words, analog voltage output for each sub-frame is converted into a digital signal, for example, through a 12-bit ADC, and the digital signal converted for each sub-frame is multiplied by a coefficient of 2n.

    [0083] That is, when the output signal of the n-th sub-frame is multiplied by a coefficient of 2n,

    Vn: the output signal of n-th sub-frame and IPHOTO: light leakage current), such that the same result as the output signal of the first sub-frame is obtained. It is possible to acquire a 16-bit digital signal by interpolation using the digital output signal for sub-frames which are obtained by the calculation.

    [0084] Further, the light leakage current of the light receiving element (e.g. p-i-m(p-intrinsic-metal) diode) depends on the magnitude of incident light in the reverse bias state. The light leakage current is larger than a thermal leakage current component of the light receiving element itself, such that light can be sensed.

    [0085] However, when the glass substrate with the light sensor circuit increases in temperature, the thermal leakage current may correspondingly rapidly increases, which may cause malfunction of the source follower type of light sensor circuit.

    [0086] Accordingly, an embodiment may overcome the problem by removing the thermal leakage current component in the leakage current components of the light receiving element.

    [0087] In other words, in order to remove only the thermal leakage current component, a light sensor circuit (second light sensor circuit) using a light receiving element having a light-shielding layer is required, other than the light sensor circuit (first light sensor circuit) shown in FIG. 1 and a difference in signals output from the first and second light sensor circuits should be calculated.

    [0088] In this configuration, the light receiving element of the second light sensor circuit has a light-shielding layer at the outside, such that it is not influenced by external light and generates only leakage current according to temperature. However, the configuration of the second light sensor circuit is the same as the light sensor circuit shown in FIG. 1A and FIG. 1B described above, except that the light receiving element is equipped with the light-shielding layer, and the operation is the same. Therefore, the detailed description is not provided.

    [0089] The principle of removing the thermal leakage current component can be expressed as the following equations,





    where ΔVNOBLK is a signal output from the first light sensor circuit without a light-shielding layer and ΔVNOBLK is a signal output from the second light sensor circuit with a light-shielding layer.

    [0090] Therefore, as can be seen from the equations, the leakage current output from the light receiving element of the first light sensor circuit includes the light leakage current and thermal leakage current components, whereas the leakage current output from the light receiving element of the second light sensor circuit includes only the thermal leakage current component.

    [0091] Further, the output of the first and second light sensor circuits is achieved by subtraction in a differential amplifier and converted into a digital signal by the ADC. However, it may be possible to obtain a difference in two signals, using a digital subtractor directly through the ADC, without using the differential amplifier.

    [0092] Accordingly, a 16-bit linear output signal is finally output through the interpolation of the multi-frame driving described above, by using the converted digital signal and the temperature information.

    [0093] Therefore, it is possible to prevent the output current of the light sensor circuit from being changed by the temperature leakage current, by calculating the difference in the signals output from the first and second light sensor circuits such that the temperature leakage current component is removed without using a specific temperature sensor.

    [0094] By way of summation and review, in the related art, a light sensor, a substrate, and a circuit need to be mounted on a separate substrate, i.e., other than the main substrate having a flat display panel, in manufacturing the light sensor circuit, and electrically connect the separate substrate with the main substrate. Therefore, the flat panel displays increase in size, thickness, complexity and power consumption.

    [0095] Further, in the light sensor circuit of the flat panel displays of the related art, the output current is changed by light leakage current in the light sampling period, such that it may fail to accurately sample ambient light. Further, in the light sensor circuit of the related art, as ambient temperature increases, the output current of the light sensor circuit is changed by temperature leakage current, such that it is hard to accurately sense the ambient light.

    [0096] According to embodiments of the invention, resolution at low luminance may be improved and the range of sensible ambient light may be increased by divisionally driving a frame period, in which light is sensed, into a plurality of sub-frames.

    [0097] Further, according to embodiments of the invention, by removing a temperature leakage current component, using a light receiving element equipped with a light-shielding layer, without using a specific temperature sensor, such that output current of the light sensor circuit is prevented from being changed by temperature leakage current, thereby preventing malfunction of a light sensor circuit.

    [0098] Embodiments of the invention have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the scope of the present invention as set forth in the following claims.


    Claims

    1. A light sensor circuit, comprising:

    a first transistor (P1) having first and second electrodes and a gate electrode;

    a second transistor (P2) having a first electrode connected to the gate electrode of the first transistor (P1) and a second electrode connected to the second electrode of the first transistor (P1), the second transistor (P2) including a gate electrode connected to receive a first control signal (CS1);

    a third transistor (P3) having a first electrode connected to a first reference voltage (VREF1) and a second electrode connected to first electrode of the first transistor (P1), the third transistor (P3) including a gate electrode connected to receive a second control signal (CS2);

    a fourth transistor (P4) having a first electrode connected to the second electrode of the first transistor (P1) and a second electrode connected to a second power source (VSS), the fourth transistor (P4) including a gate electrode connected to receive an inverted second control signal (CS2b);

    a light receiving element (PD) having an anode connected to a third reference voltage (VREF3);

    a fifth transistor (P5) having a first electrode connected to a second reference voltage (VREF2) and a second electrode connected to a cathode of the light receiving element (PD), the fifth transistor (P5) including a gate electrode connected to receive the first control signal (CS1);

    a first capacitor (C1) having a first and a second electrode, the second electrode connected to the third reference voltage (VREF3);

    a sixth transistor (P6) having a first electrode connected to the cathode of the light receiving element (PD) and a second electrode connected to the first electrode of the first capacitor (C1), the sixth transistor including a gate electrode connected to receive a third control signal (CS3); and

    a second capacitor (C2) connected between the gate electrode of the first transistor (P1) and the first electrode of the first capacitor (C1).


     
    2. A light sensor circuit as claimed in claim 1, further comprising:

    a seventh transistor (P7) connected between the first electrode of the first transistor (P1) and a first side of an output load, the seventh transistor (P7) including a gate electrode receiving a fourth control signal (CS4); and

    an eighth transistor (P8) connected between an output signal line (OUT) extending to a second side of the output load and a first power source (VDD), the eighth transistor (P8) including a gate electrode receiving an initializing signal (pre).


     
    3. A light sensor circuit as claimed in claim 1 or 2, wherein the light receiving element (PD) is any one of a p-i-m(p-intrinsic-metal) diode, a PIN diode, a PN diode, and a photo coupler.
     
    4. A light sensor circuit as claimed in any preceding claim, wherein the first reference voltage (VREF1) and the second reference voltage (VREF2) have a high-level voltage value.
     
    5. A light sensor circuit as claimed in any preceding claim, wherein the third reference voltage (VREF3) and the second power source (VSS) are implemented by low-level voltage or a grounding power source (GND).
     
    6. a light sensor circuit as claimed in any preceding claim, wherein at least one of the second transistor (P2), the fifth transistor (P5), and the sixth transistor (P6) is a dual gate type.
     
    7. A light sensor circuit as claimed in any preceding claim, further comprising:

    a ninth transistor (P9) supplied with the first control signal (CS1b) inverted by the gate electrode, the ninth transistor (P9) having first and second electrodes connected with the gate electrode of the first transistor (P1); and

    a tenth transistor (P10) supplied with a third control signal (CS3b) inverted by the gate electrode, the tenth transistor (P10) having first and second electrodes connected with a first electrode of the first capacitor (C1).


     
    8. A method of driving a light sensor circuit according to claim 1, wherein one frame is composed of a plurality of sub-frames, the sub-frames are divided into three periods (t1, t2, and t3); the method comprising:

    implementing the light receiving element (PD) in a reverse bias state by storing a threshold voltage of the first transistor (P1) in the second capacitor (C2) and charging the cathode of the light receiving element (PD) to the second reference voltage (VREF2)in the first period (t1);

    discharging the first capacitor (C1), which stores voltage by the light leakage current generated in accordance with the amount of light traveling into the light receiving element (PD), to correspond to light leakage current in the second period (t2); and

    outputting information on the voltage discharged in accordance with the light leakage current to an output signal line (OUT) in the third period (t3),

    wherein the second period of each of the sub-frames is sequentially shortened by a multiple of 2 from a second period time T0 of the first sub-frame.


     
    9. A method as claimed in claim 8, wherein low-luminance light is sensed in the first sub-frame having the longest second period and high-luminance light is sensed in the last sub-frame having the shortest second period.
     
    10. A method as claimed in claims 8 or 9 wherein implementing the light receiving element (PD) includes:

    the second (P2) transistor receiving the first control signal (CS1) as a selection signal and, in combination with the fourth transistor (P4) which receives the inverted second control signal (CS2b), initializes the voltage of a gate electrode node of the first transistor (P1) into the second power source (VSS); and

    after receiving the first control signal (CS1) and initializing the voltage, the third transistor (P3) receives the second control signal (CS2) as a selection signal, which charges the gate electrode node of the first transistor (P1) with a voltage equal to the difference between the first reference voltage and the threshold voltage of the first transistor.


     
    11. A method of as claimed in one of claims 8 to 10, wherein discharging the first capacitor (C1) includes providing the third control signal (CS3) as a selection signal to turn on the sixth transistor (P6) to then correspondingly decrease the voltage of the gate electrode node of the first transistor (P1) by up to the amount of voltage change of the first capacitor (C1).
     
    12. A method as claimed in one of claims 8 to 11, wherein discharging the first capacitor (C1) further includes receiving an initializing signal as a selection signal and turning on an eighth transistor (P8) in a predetermined period of the second period (t2), and then charging an output line with a first power source (VDD).
     
    13. A method as claimed in one of claims 8 to 12, wherein outputting information includes providing a fourth control signal (CS4) as a selection signal to turn on a seventh transistor (P7) and discharge the voltage in accordance with the light leakage current that is output to an output signal line (OUT) through the seventh transistor (P7).
     
    14. A method of sensing light using a light sensor circuit as claimed in one of claims 8 to 13, the method comprising:

    providing another light sensor circuit;

    shielding the another light sensor circuit from light; and

    subtracting an output of the another light sensor circuit from an output of the light sensor circuit to provide a corrected output.


     


    Ansprüche

    1. Lichtsensorschaltung, umfassend:

    einen ersten Transistor (P1) mit ersten und zweiten Elektroden und einer Gate-Elektrode;

    einen zweiten Transistor (P2) mit einer ersten Elektrode, die mit der Gate-Elektrode des ersten Transistors (P1) verbunden ist und einer zweiten Elektrode, die mit der zweiten Elektrode des ersten Transistors (P1) verbunden ist, wobei der zweite Transistor (P2) eine Gate-Elektrode beinhaltet, die verbunden ist, um ein erstes Steuerungssignal (CS1) zu empfangen;

    einen dritten Transistor (P3) mit einer ersten Elektrode, die mit einer ersten Referenzspannung (VREF1) verbunden ist und einer zweiten Elektrode, die mit der ersten Elektrode des ersten Transistors (P1) verbunden ist, wobei der dritte Transistor (P3) eine Gate-Elektrode beinhaltet, die verbunden ist, um ein zweites Steuerungssignal (CS2) zu empfangen;

    einen vierten Transistor (P4) mit einer ersten Elektrode, die mit der zweiten Elektrode des ersten Transistors (P1) verbunden ist und einer zweiten Elektrode, die mit einer zweiten Stromquelle (VSS) verbunden ist, wobei der vierte Transistor (P4) eine Gate-Elektrode beinhaltet, die verbunden ist, um ein invertiertes zweites Steuerungssignal (CS2b) zu empfangen;

    ein Lichtempfangselement (PD) mit einer Anode, die mit einer dritten Referenzspannung (VREF3) verbunden ist;

    einen fünften Transistor (P5) mit einer ersten Elektrode, die mit einer zweiten Referenzspannung (VREF2) verbunden ist und einer zweiten Elektrode, die mit einer Kathode des Lichtempfangselements (PD) verbunden ist, wobei der fünfte Transistor (P5) eine Gate-Elektrode beinhaltet, die verbunden ist, um ein erstes Steuerungssignal (CS1) zu empfangen;

    einen ersten Kondensator (C1) mit einer ersten und einer zweiten Elektrode, wobei die zweite Elektrode mit der dritten Referenzspannung (VREF3) verbunden ist;

    einen sechsten Transistor (P6) mit einer ersten Elektrode, die mit der Kathode des Lichtempfangselements (PD) verbunden ist und einer zweiten Elektrode, die mit der ersten Elektrode des ersten Kondensators (C1) verbunden ist, wobei der sechste Transistor eine Gate-Elektrode beinhaltet, die verbunden ist, um ein drittes Steuerungssignal (CS3) zu empfangen; und

    einen zweiten Kondensator (C2), der zwischen der Gate-Elektrode des ersten Transistors (P1) und der ersten Elektrode des ersten Kondensators (C1) verbunden ist.


     
    2. Lichtsensorschaltung nach Anspruch 1, weiter umfassend:

    einen siebten Transistor (P7), der zwischen der ersten Elektrode des ersten Transistors (P1) und einer ersten Seite einer Ausgangslast verbunden ist, wobei der siebte Transistor (P7) eine Gate-Elektrode beinhaltet, die ein viertes Steuerungssignal (CS4) empfängt; und

    einen achten Transistor (P8), der zwischen einer Ausgangssignalleitung (OUT), die sich zu einer zweiten Seite der Ausgangslast erstreckt, und einer ersten Stromquelle (VDD) verbunden ist, wobei der achte Transistor (P8) eine Gate-Elektrode beinhaltet, die ein initialisierendes Signal (pre) empfängt.


     
    3. Lichtsensorschaltung nach Anspruch 1 oder 2, wobei das Lichtempfangselement (PD) eines von einer p-i-m-(p-intrinsisch-Metall)-Diode, einer PIN-Diode, einer PN-Diode und einem Fotokoppler ist.
     
    4. Lichtsensorschaltung nach einem der vorhergehenden Ansprüche, wobei die erste Referenzspannung (VREF1) und die zweite Referenzspannung (VREF2) einen Hochspannungswert haben.
     
    5. Lichtsensorschaltung nach einem der vorhergehenden Ansprüche, wobei die dritte Referenzspannung (VREF3) und die zweite Stromquelle (VSS) durch Niedrigspannung oder eine erdende Stromquelle (GND) umgesetzt werden.
     
    6. Lichtsensorschaltung nach einem der vorhergehenden Ansprüche, wobei mindestens einer von dem zweiten Transistor (P2), dem fünften Transistor (P5) und dem sechsten Transistor (P6) ein Dual-Gate-Typ ist.
     
    7. Lichtsensorschaltung nach einem der vorhergehenden Ansprüche, weiter umfassend:

    einen neunten Transistor (P9), versorgt mit dem ersten, durch die Gate-Elektrode invertierten Steuerungssignal (CS1b), wobei der neunte Transistor (P9) eine erste und eine zweite Elektrode aufweist, die mit der Gate-Elektrode des ersten Transistors (P1) verbunden sind; und

    einen zehnten Transistor (P10), versorgt mit einem dritten, durch die Gate-Elektrode invertierten Steuerungssignal (CS3b), wobei der zehnte Transistor (P10) eine erste und eine zweite Elektrode aufweist, die mit einer ersten Elektrode des ersten Kondensators (C1) verbunden sind.


     
    8. Verfahren zum Ansteuern einer Lichtsensorschaltung nach Anspruch 1, wobei ein Rahmen aus einer Vielzahl von Teilrahmen besteht, wobei die Teilrahmen in drei Zeiträume (t1, t2 und t3) unterteilt sind; wobei das Verfahren Folgendes umfasst:

    Umsetzen des Lichtempfangselements (PD) in einem Sperrvorspannungszustand, indem im ersten Zeitraum (t1) eine Schwellenspannung des ersten Transistors (P1) im zweiten Kondensator (C2) gespeichert wird und die Kathode des Lichtempfangselements (PD) auf die zweite Referenzspannung (VREF2) geladen wird;

    Entladen des ersten Kondensators (C1), der Spannung speichert durch den in Übereinstimmung mit der Menge an Licht, die in das Lichtempfangselement (PD) gelangt, erzeugten Schwachableitstrom, um Schwachableitstrom zu entsprechen, im zweiten Zeitraum (t2); und

    Ausgeben von Informationen über die in Übereinstimmung mit dem Schwachableitstrom entladene Spannung an eine Ausgangssignalleitung (OUT) im dritten Zeitraum (t3),

    wobei der zweite Zeitraum jedes der Teilrahmen sequentiell durch ein Vielfaches von 2 aus einem zweiten Zeitraum T0 des ersten Teilrahmens verkürzt wird.


     
    9. Verfahren nach Anspruch 8, wobei Niedrigleuchtstärkelicht im ersten Teilrahmen mit dem längsten zweiten Zeitraum gespürt wird und Hochleuchtstärkelicht im letzten Teilrahmen mit dem kürzesten zweiten Zeitraum gespürt wird.
     
    10. Verfahren nach Anspruch 8 oder 9, wobei das Umsetzen des Lichtempfangselements (PD) Folgendes beinhaltet:

    der zweite Transistor (P2) empfängt das erste Steuerungssignal (CS1) als ein Auswahlsignal und initialisiert in Kombination mit dem vierten Transistor (P4), der das invertierte zweite Steuerungssignal (CS2b) empfängt, die Spannung eines Gate-Elektrodenknotens des ersten Transistors (P1) in die zweite Stromquelle (VSS); und

    nach dem Empfangen des ersten Steuerungssignals (CS1) und Initialisieren der Spannung empfängt der dritte Transistor (P3) das zweite Steuerungssignal (CS2) als ein Auswahlsignal, wodurch der Gate-Elektrodenknoten des ersten Transistors (P1) mit einer Spannung gleich dem Unterschied zwischen der ersten Referenzspannung und der Schwellenspannung des ersten Transistors geladen wird.


     
    11. Verfahren nach einem der Ansprüche 8 bis 10, wobei das Entladen des ersten Kondensators (C1) das Bereitstellen des dritten Steuerungssignals (CS3) als ein Auswahlsignal beinhaltet, um den sechsten Transistor (P6) anzuschalten, um dann entsprechend die Spannung des Gate-Elektrodenknotens des ersten Transistors (P1) um bis zur Menge der Spannungsänderung des ersten Kondensators (C1) zu reduzieren.
     
    12. Verfahren nach einem der Ansprüche 8 bis 11, wobei das Entladen des ersten Kondensators (C1) weiter das Empfangen eines initialisierenden Signals als ein Auswahlsignal und Anschalten eines achten Transistors (P8) in einem zuvor festgelegten Zeitraum des zweiten Zeitraums (t2) und dann das Laden einer Ausgangsleitung mit einer ersten Stromquelle (VDD) beinhaltet.
     
    13. Verfahren nach einem der Ansprüche 8 bis 12, wobei das Ausgeben von Informationen das Bereitstellen eines vierten Steuerungssignals (CS4) als ein Auswahlsignal zum Anschalten eines siebten Transistors (P7) und Entladen der Spannung in Übereinstimmung mit dem Schwachableitstrom, der an eine Ausgangssignalleitung (OUT) durch den siebten Transistor (P7) ausgegeben wird, beinhaltet.
     
    14. Verfahren zum Fühlen von Licht unter Verwendung einer Lichtsensorschaltung nach einem der Ansprüche 8 bis 13, wobei das Verfahren Folgendes umfasst:

    Bereitstellen einer weiteren Lichtsensorschaltung;

    Abschirmen der weiteren Lichtsensorschaltung vor Licht; und

    Subtrahieren eines Ausgangs der weiteren Lichtsensorschaltung von einem Ausgang der Lichtsensorschaltung, um einen korrigierten Ausgang bereitzustellen.


     


    Revendications

    1. Circuit de capteur de lumière, incluant :

    un premier transistor (P1) présentant des première et seconde électrodes et une électrode grille ;

    un deuxième transistor (P2) présentant une première électrode connectée à l'électrode grille du premier transistor (P1) et une seconde électrode connectée à la seconde électrode du premier transistor (P1), le deuxième transistor (P2) incluant une électrode grille connectée pour recevoir un premier signal de commande (CS1) ;

    un troisième transistor (P3) présentant une première électrode connectée à une première tension de référence (VREF1) et une seconde électrode connectée à la première électrode du premier transistor (P1), le troisième transistor (P3) incluant une électrode grille connectée pour recevoir un deuxième signal de commande (CS2) ;

    un quatrième transistor (P4) présentant une première électrode connectée à la seconde électrode du premier transistor (P1) et une seconde électrode connectée à une seconde source d'énergie (VSS), le quatrième transistor (P4) incluant une électrode grille connectée pour recevoir un deuxième signal de commande inversé (CS2b) ;

    un élément de réception de lumière (PD) présentant une anode connectée à une troisième tension de référence (VREF3) ;

    un cinquième transistor (P5) présentant une première électrode connectée à une deuxième tension de référence (VREF2) et une seconde électrode connectée à une cathode de l'élément de réception de lumière (PD), le cinquième transistor (P5) incluant une électrode grille connectée pour recevoir le premier signal de commande (CS1) ;

    un premier condensateur (C1) présentant une première électrode et une seconde électrode, la seconde électrode étant connectée à la troisième tension de référence (VREF3) ;

    un sixième transistor (P6) présentant une première électrode connectée à la cathode de l'élément de réception de lumière (PD) et une seconde électrode connectée à la première électrode du premier condensateur (C1), le sixième transistor incluant une électrode grille connectée pour recevoir un troisième signal de commande (CS3) ; et

    un deuxième condensateur (C2) connecté entre l'électrode grille du premier transistor (P1) et la première électrode du premier condensateur (C1).


     
    2. Circuit de capteur de lumière selon la revendication 1, comportant en outre :

    un septième transistor (P7) connecté entre la première électrode du premier transistor (P1) et un premier côté d'une charge de sortie, le septième transistor (P7) incluant une électrode grille recevant un quatrième signal de commande (CS4) ; et

    un huitième transistor (P8) connecté entre une ligne de signal de sortie (OUT) s'étendant jusqu'à un second côté de la charge de sortie et une première source d'énergie (VDD), le huitième transistor (P8) incluant une électrode grille recevant un signal d'initialisation (pre).


     
    3. Circuit de capteur de lumière selon la revendication 1 ou 2, dans lequel l'élément de réception de lumière (PD) correspond à l'un quelconque des éléments parmi une diode p-i-m (métal intrinsèque p), une diode PIN, une diode PN, et un photo-coupleur.
     
    4. Circuit de capteur de lumière selon l'une quelconque des revendications précédentes, dans lequel la première tension de référence (VREF1) et la deuxième tension de référence (VREF2) présentent une valeur de tension de haut niveau.
     
    5. Circuit de capteur de lumière selon l'une quelconque des revendications précédentes, dans lequel la troisième tension de référence (VREF3) et la seconde source d'énergie (VSS) sont mises en oeuvre par une tension de bas niveau ou par une source d'énergie de mise à la terre (GND).
     
    6. Circuit de capteur de lumière selon l'une quelconque des revendications précédentes, dans lequel au moins l'un parmi le deuxième transistor (P2), le cinquième transistor (P5) et le sixième transistor (P6) est un transistor de type à double grille.
     
    7. Circuit de capteur de lumière selon l'une quelconque des revendications précédentes, comportant en outre :

    un neuvième transistor (P9) alimenté avec le premier signal de commande (CS1b) inversé par l'électrode grille, le neuvième transistor (P9) présentant des première et seconde électrodes connectées à l'électrode grille du premier transistor (P1) ; et

    un dixième transistor (P10) alimenté avec un troisième signal de commande (CS3b) inversé par l'électrode grille, le dixième transistor (P10) présentant des première et seconde électrodes connectées à une première électrode du premier condensateur (C1).


     
    8. Procédé de commande d'un circuit de capteur de lumière selon la revendication 1, dans lequel une trame est composée d'une pluralité de sous-trames, et dans lequel les sous-trames sont divisées en trois périodes (t1, t2, et t3) ; le procédé comportant les étapes ci-dessous consistant à :

    mettre en oeuvre l'élément de réception de lumière (PD) dans un état de polarisation inverse, en stockant une tension de seuil du premier transistor (P1) dans le second condensateur (C2), et charger la cathode de l'élément de réception de lumière (PD) à la deuxième tension de référence (VREF2) dans la première période (t1) ;

    décharger le premier condensateur (C1), lequel stocke une tension par le courant de fuite de lumière généré selon la quantité de lumière se propageant dans l'élément de réception de lumière (PD), en vue d'une correspondance avec un courant de fuite de lumière dans la deuxième période (t2) ; et

    générer en sortie des informations sur la tension déchargée selon le courant de fuite de lumière vers une ligne de signal de sortie (OUT) dans la troisième période (t3) ;

    dans lequel la deuxième période de chacune des sous-trames est raccourcie de manière séquentielle par un multiple de deux à partir d'un second instant de période T0 de la première sous-trame.


     
    9. Procédé selon la revendication 8, dans lequel une lumière de faible luminance est détectée dans la première sous-trame présentant la deuxième période la plus longue, et une lumière de haute luminance est détectée dans la dernière sous-trame présentant la deuxième période la plus courte.
     
    10. Procédé selon la revendication 8 ou 9, dans lequel l'étape de mise en oeuvre de l'élément de réception de lumière (PD) comprend les étapes ci-dessous dans lesquelles :

    le deuxième transistor (P2) reçoit le premier signal de commande (CS1) sous la forme d'un signal de sélection et, en combinaison avec le quatrième transistor (P4) qui reçoit le deuxième signal de commande inversé (CS2b), initialise la tension d'un noeud d'électrode grille du premier transistor (P1) dans la seconde source d'énergie (VSS) ; et

    suite à la réception du premier signal de commande (CS1) et à l'initialisation de la tension, le troisième transistor (P3) reçoit le deuxième signal de commande (CS2) sous la forme d'un signal de sélection, lequel charge le noeud d'électrode grille du premier transistor (P1) avec une tension égale à la différence entre la première tension de référence et la tension de seuil du premier transistor.


     
    11. Procédé selon l'une quelconque des revendications 8 à 10, dans lequel l'étape de décharge du premier condensateur (C1) inclut l'étape consistant à fournir le troisième signal de commande (CS3) sous la forme d'un signal de sélection pour mettre sous tension le sixième transistor (P6) en vue de diminuer ensuite de façon correspondante la tension du noeud d'électrode grille du premier transistor (P1) à hauteur de la quantité de changement de tension du premier condensateur (C1).
     
    12. Procédé selon l'une quelconque des revendications 8 à 11, dans lequel l'étape de décharge du premier condensateur (C1) inclut en outre l'étape consistant à recevoir un signal d'initialisation sous la forme d'un signal de sélection, et à mettre sous tension un huitième transistor (P8) dans une période prédéterminée de la deuxième période (t2), et à charger ensuite une ligne de sortie avec une première source d'énergie (VDD).
     
    13. Procédé selon l'une quelconque des revendications 8 à 12, dans lequel l'étape de génération en sortie d'informations inclut l'étape consistant à fournir un quatrième signal de commande (CS4) sous la forme d'un signal de sélection en vue de mettre sous tension un septième transistor (P7) et de décharger la tension selon le courant de fuite de lumière qui est généré en sortie vers une ligne de signal de sortie (OUT) par l'intermédiaire du septième transistor (P7).
     
    14. Procédé de détection de lumière au moyen d'un circuit de capteur de lumière selon l'une quelconque des revendications 8 à 13, le procédé comportant les étapes ci-dessous consistant à :

    fournir un autre circuit de capteur de lumière ;

    protéger l'autre circuit de capteur de lumière contre la lumière ; et

    soustraire une sortie de l'autre circuit de capteur de lumière d'une sortie du circuit de capteur de lumière, en vue de fournir une sortie corrigée.


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description