| (11) | EP 1 014 453 B1 |
(12) | EUROPEAN PATENT SPECIFICATION |
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(54) | SEMICONDUCTOR DEVICE HALBLEITERVORRICHTUNG DISPOSITIF SEMI-CONDUCTEUR |
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Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention). |
TECHNICAL FIELD
BACKGROUND ART
DISCLOSURE OF INVENTION
BRIEF DESCRIPTION OF DRAWINGS
Fig. 1 is a longitudinal cross section illustrating the structure of a diode in a first preferred embodiment of this invention.
Fig. 2 is a diagram schematically showing a SR measuring method.
Fig. 3 is a diagram showing the result of SR measurement of a diode when the 25 conventional third technique is applied.
Fig. 4 is a diagram showing the result of SR measurement of the diode of the first preferred embodiment.
Fig. 5 is a longitudinal cross section illustrating a simulation model in this invention.
Fig. 6 is a diagram showing the result of a simulation to the model of Fig. 5.
Fig. 7 is a diagram showing the result of a prototype of the diode in the first preferred embodiment.
Fig. 8 is a diagram showing the result of SR measurement when a recovery peak current has the minimum value in the result of Fig. 7.
Fig. 9 is a diagram showing the result of the prototype of the diode in the first preferred embodiment.
Fig. 10 is a diagram showing the result of measurement of a conventional diode, for comparison with Fig. 9.
Fig. 11 is a cross section illustrating a method of manufacturing a diode in a first example.
Fig. 12 is another cross section illustrating the method of manufacturing a diode in the first example.
Fig. 13 is another cross section illustrating the method of manufacturing a diode in the first example.
Fig. 14 is another cross section illustrating the method of manufacturing a diode in the first example.
Fig. 15 is a flowchart illustrating manufacturing steps in a second preferred embodiment of this invention.
Fig. 16 is a cross section partially illustrating the second step in Fig. 15.
Fig. 17 is a cross section illustrating the structure of a conventional general diode.
Fig. 18 is a diagram showing output characteristic of a diode.
Fig. 19 is a diagram showing reverse recovery characteristic of a diode.
Fig. 20 is a cross section illustrating an example of the structure of a diode when the conventional second technique is applied.
Fig. 21 is a cross section illustrating an example of the structure of a diode when the conventional fourth technique is applied.
Fig. 22 is a diagram showing the relationship between proton dose, breakdown voltage, and recovery peak current, in a diode to which the conventional fourth technique is applied.
Fig. 23 is a diagram showing the result of measurement of breakdown voltage and recovery peak current when helium ions are implanted.
BEST MODE FOR CURRYING OUT THE INVENTION
(First Preferred Embodiment)
(1) Fig. 1 is a longitudinal cross section of a diode according to the first preferred embodiment of this invention. In Fig. 1, a first semiconductor layer (N type substrate) of a first conductivity 1 comprises a cathode N+ layer 1A and N- layer 1B formed thereon. In this embodiment, N type conductivity type corresponds to the first conductivity type.
Formed on a first main surface of the first semiconductor layer 1 is a second semiconductor layer 2 having the same N type conductivity type in a state of being damaged by implantation of a light ion (e.g., He ion). A first main surface of the second semiconductor layer 2 and the first main surface of the first semiconductor layer 1 form a first interface S1. The second semiconductor layer 2 is a feature of this embodiment and, as can be understood later from the following description, the layer 2 is a region that has (i) a lifetime (called second lifetime) τ2 shorter or smaller than a lifetime τ1 (called first lifetime time) of carriers in the first semiconductor layer 1; and (ii) a resistance value that decreases monotonically. Hereinafter, the second semiconductor layer 2 is called "low lifetime layer or low lifetime region."
Disposed on the second main surface of the low lifetime layer 2 (opposed to the first main surface) is a third semiconductor layer (which corresponds to an anode layer, and is called anode P layer hereinafter) 3 formed by diffusion of impurity of a second conductivity type (P type herein). The second main surface of the layer 2 and the second main surface of the layer 3 form a second interface S2. Here, thickness of the anode P layer 3 is set to a small value, namely, approximately 3 µm.
Further, an anode electrode (first main electrode) 5 is formed on the first main surface of the anode P layer 3, and a cathode electrode (second main electrode) 6 is formed on the second main surface corresponding to the rear surface of the cathode N+ layer 1A.
Hereat, for example, diffusion of a heavy metal such as Pt or Au in the mentioned first conventional technique, is applied to this diode, and diffusion time or diffusion temperature of the heavy metal is controlled such that the lifetime τ1 of carriers in the first semiconductor layer 1 is longer than that (τ2) of the low lifetime layer 2, thereby increasing the carrier density of the cathode side. Strictly, since the diffusion coefficient of the heavy metal in the first semiconductor layer 1 has a slight slope, the lifetime (τ1A) on the cathode N+ layer 1A side is slightly longer than the lifetime (τ1B) of the N- layer 1B. This technique is, of course, for increasing the recovery current dissipation time Trr shown in Fig. 19.
Also, from the point of view of that the recovery peak current Irr has a smaller value than it had conventionally, and no influence is exerted on an extension of the recovery current dissipation time Trr that is obtained by application of the technique of diffusion of a heavy metal, thickness of the low lifetime layer 2 or depth d from the second interface S2 is controlled to a value in a predetermined range as described later.
(2) Operation of a diode of this embodiment is described as below.
In the structure of Fig. 1, a predetermined anode voltage VAK is applied between the anode electrode 5 and cathode electrode 6, as forward bias (see Fig. 18) and, when the anode voltage VAK exceeds a threshold value (∼0.6 V), holes are injected from the anode electrode 5 into the N- layer 1B via the low lifetime layer 2, and thus the diode conducts. When the anode voltage VAK is equal to the on state voltage value Vf shown in Fig. 18, a rated current If flows. On the other hand, when a predetermined anode voltage VKA is applied between the cathode electrode 6 and anode electrode 5, as reverse bias (see Fig. 18), only the low lifetime layer 2 is formed in the diode unless the anode voltage VKA exceeds a breakdown voltage Vr.
The low lifetime layer 2 has no influence on the breakdown voltage of a PN junction, as described later. Therefore, the diode of this structure produces the advantage that ③ breakdown voltage has lesser reduction than that of a diode in which a low lifetime layer 2 is not formed. In addition, since the low lifetime layer 2 is formed on the anode side, the carrier density in the vicinity of the anode is reduced considerably. Thereby, there are obtained, at the same time, ① the advantage that the recovery peak current Irr at the time of recovery (see Fig. 19) can be further reduced than the mentioned first to fourth conventional techniques. In this diode, a heavy metal is previously diffused in the first semiconductor layer 1 as in the first conventional technique. By controlling the quantity of diffusion, the lifetime on the cathode N+ layer 1A side is extended to increase the carrier density on the cathode side. It is therefore possible that ② the recovery current dissipation time Trr (see Fig. 19) is extended by lowing on state voltage Vf during on state (see Fig. 18).
(3) To prove the advantage of the diode structure of Fig. 1, as to proton implantation in the mentioned conventional fourth technique and helium ion implantation in this embodiment, the influence of their respective implantation upon breakdown voltage has been investigated this time. The investigation has been performed by measuring, after implanting a charged particle (H+, He+), a spread resistance (hereinafter called SR) of each sample subjected to heat treatment. Here, SR measurement means to perform the following measurement. Specifically, for example, a semiconductor element is polished obliquely as schematically illustrated in Fig. 2 (of course, it may be polished vertically), and two electrode needles are brought into contact wit a polished surface SS and moved along a direction D1, to measure resistance caused by a spread SP between the needles (i.e., spreading resistance). This is a method of finding a resistance value or resistivity within the semiconductor element, which is a known measuring technique.
The result of SR measurement obtained by performing a conventional proton implantation, and the result of SR measurement of the device subjected to He ion implantation, are shown in Figs. 3 and 4, respectively. The measurements shown in Figs. 3 and 4 were carried out by using a measuring instrument of SOLID STATE MEASUREMENTS, INC., USA. The abscissa of Figs. 3 and 4 corresponds to a position where a charged particle is implanted, which is given as depth L from a first main surface of the anode P layer 3 in Fig. 1. In Figs. 3 and 4, the results of measurement R, ρ and N designate a spreading resistance, resistivity of an element, and impurity concentration, respectively. For silicon, there are a known reduced value between spreading resistance R and resistivity ρ or impurity concentration N. Therefore, if only spreading resistance R is measured, by using the reduced value, the value of resistivity ρ, and then impurity concentration N can be calculated automatically. The ordinate of Figs. 3 and 4 is indicated by logarithmic scale. Samples which were used in the measurements of Figs. 3 and 4 were produced by using the same substrate and material, and the sole difference therebetween was a radiation source (namely, whether H+ or He+). Their respective dose was controlled such that both had the same electric characteristic (recovery characteristic). The dose was a practical value in the range of about 10 to 100 cm-3, in the relative values in Fig. 22.
In the case of proton implantation, as shown in symbol R1 in Fig. 3, measurement is made on a low resistance region between a high resistance part damaged by proton implantation and an N- layer of a wafer. Here, the term "damage" is understood to mean that the resistance of a semiconductor layer is increased by implantation of a light ion. The reason for this seems that a damaged layer formed by proton is turned to be a donor (impurity) by the subsequent heat treatment. This donar phenomenon is considered to occur in practice across the damaged layer. Hence, breakdown voltage decreases with proton implantation.
On the other hand, in the case of helium ion implantation shown in Fig. 4, as best shown by comparison with Fig. 3, such a donor phenomenon as indicated by a region R1 of Fig. 3 is not caused, and a spreading resistance R or resistivity ρ decreases monotonically with increasing depth L from the first main surface of the anode P layer 3 or the depth from the interface S2. That is, the damaged part formed by helium ion implantation is measured as a high resistance region, and it can be judged that such a donor phenomenon as in proton implantation is not caused. Accordingly, with helium ion implantation, only a damage due to implantation is formed within an n layer in the vicinity of a junction, and thus no reduction in breakdown voltage Vr (Fig. 18) is caused by implantation. Of course, this does not depend upon helium ion dose.
Fig. 23 shows the result of measurement as to characteristics of breakdown voltage Vr and recovery peak current Irr, to helium ion dose. The left and right ordinates of Fig. 23 indicate breakdown voltage Vr and relative ratio (Irr/If), respectively, as in Fig. 22. As best shown of Fig. 22 with Fig. 23, for helium ion implantation, hardly or no change in breakdown voltage Vr is observed even when implanting helium ions of a dose of approximately 10 to 100 cm-3 (relative value) with which a sufficiently small recovery current value Irr can be realized in practice.
As stated above, the formation of the low lifetime region 2 by means of helium ion implantation effects the action of preventing the N- layer part subjected to implantation from becoming donor even after heat treatment, thereby making breakdown voltage Vr unchanged.
(4) Description will now be made of reverse recovery characteristic of the diode of the structure of Fig. 1.
In this diode, the low lifetime region 2 damaged by helium ion implantation is formed in the vicinity of the anode, namely, around the interface S2 that is a PN junction surface. Therefore, ① the carrier density in the vicinity of the anode decreases markedly, and recovery peak current Irr lowers markedly. In addition, ③ there occurs no deterioration in breakdown voltage Vr due to implantation, as stated in the item (3).
Also, in this diode, a damage due to helium implantation is locally formed in the vicinity of the anode alone. Thus, as compared with a conventional diode in which such a damage is not formed, it is necessary to extend the lifetime of carriers in other regions whereat no damage is formed, namely, the N- layer 1B and cathode N+ layer 1A in Fig. 1. The reason for this is that, since the low lifetime region 2 is locally formed in the N- layer 1B, if the lifetime of other N type layers is set to the same value as in the case where the region 2 is not formed, on state voltage Vf during on state is increased to cause loss. To avoid this, it is necessary to control the lifetime of other N type layers such as to be extended for reducing on state voltage Vf. This can be realized by optimizing thickness d of the low lifetime region 2, and applying the mentioned technique of diffusing a heavy metal. The realization of the long lifetime increases the carrier density in the vicinity of the cathode, so that a recovery current dissipation time Trr is extended.
(5) Fig. 5 shows a simulation model for analyzing reverse recovery characteristic of a diode formed with the low lifetime region 2. In Fig. 5, the same symbol as in Fig. 1 denotes the same part. Note that in this model the region corresponding to the low lifetime region 2 of Fig. 1 is divided into a region 2S and a region 2S1 of Fig. 5. Of these, one region 2S is the region that is set in consideration of the half width of helium ion beam (≒10µm), and thickness d1 of the region 2S is set to have an amount equivalent to the half width. Therefore, the other region 2S1 part in the model of Fig. 5 must be actually a damaged part subjected to helium ion implantation, however, for convenience in simulation, the region 2S1 is merely handled as an N type semiconductor layer having the same lifetime as the N- layer 1B. In actual, both regions 2S and 2S1 are the layer damaged by helium ion implantation. Thus, the following relationship seems to be established: τ1 > τ 2S1 > τ2S, wherein the lifetime of the regions 2S and 2S1 are τ2S and τ 2S1, respectively. Accordingly, in Fig. 1, both regions 2S and 2S1 of Fig. 5 are defined integrally as the second semiconductor layer (low lifetime layer) 2.
In performing this simulation, each parameter is set as follows. Specifically, the model diode is set to a diode in the breakdown voltage of 600 V class, and the specific resistance and thickness of the N- layer 1B are set to 30 Ω. cm and 30 µm, respectively. Note that the model is set to one which has a concentration slope part of an approximately 100 µm between the N- layer 1B and N+ layer (N+ substrate) in order to correspond to the actual use of a diffused wafer. Depth or thickness of the anode P layer 3 is set to 3 µm such as to correspond to the actual diode, and its surface concentration is set to le 17. As to the lifetime of a diode having no low lifetime region, namely, corresponding to the conventional technique shown in Fig. 17, its entire region is set to 50 n sec. On the other hand, when a low lifetime region is present, width d1 of the low lifetime region 2S in the model of Fig. 5 is set to 10 µm such as to correspond to the half width of helium ion beam, the lifetime of the region 2S is set to 8 n sec. (< 1/10 × 200 n sec.), and the lifetime of other regions (2S1, 1B, and 1A) is set to 200 n sec. Then, a simulation of recovery characteristic has been executed by changing the position from the interface S2 of the low lifetime region 2 or 2S, or depth d.
The simulation has been conducted with respect to on state voltage Vf shown in Fig. 18 and reverse recovery characteristic (Irr, Trr) shown in Fig. 19, by using a commercially available simulator Medici. The obtained result of the simulation is shown in Fig. 6.
In Fig. 6, the respective characteristics Trr, Irr and Vf are indicated as a standard value of each characteristic, which is obtained when all regions have the same carrier lifetime (that is, in the absence of a region 2S). Accordingly, when a relative ratio is 1, the device shows the same characteristic as that of a conventional one (e.g., one which is shown in Fig. 17).
Under consideration of the simulation result of Fig. 6, the following points can be understood. Firstly, on state voltage Vf increases as the low lifetime region 2S is formed more deeply within the N type substrate. On the other hand, recovery peak current Irr is minimized when its formation depth is 20 µm, and increases when the position of irradiation is apart from the position at that time. As opposed to on state voltage Vf, recovery current dissipation time Trr decreases as the low lifetime region 2S is formed more deeply. These results show that, as the low lifetime region 2S is formed more deeply from the interface S2, the carrier density in the vicinity of the anode is decreased to increase on state voltage Vf. The reason why the recovery peak current Irr has a minimum value is considered that since the regions 2S1 and 2S are set in the model of Fig. 5, as the low lifetime region 2S becomes deeper, on the contrary, the number of carriers in the vicinity of the anode, namely, the number of carriers in the region 2S1 increases. Further, since the number of carriers on the cathode side is decreased as the low lifetime region 2S is formed more deeply, recovery current dissipation time Trr is reduced as the low lifetime region 2S becomes deeper.
To achieve the mentioned objects ① to ③ of the invention, it is necessary to set thickness of the low lifetime region 2 or 2S, or depth d, such as to establish the relationships of Vf≒1 (no change in on state voltage Vf, i.e., an extension of time Trr), Irr<1, and Trr>1, in the relative value in the simulation of Fig. 6. Especially, it should be regarded as significant to establish the relationship of Irr<1. If evaluated the simulation result of Fig. 6 in view of the foregoing, it is understood that superior soft recovery characteristics than was previously possible can be obtained when thickness d of the low lifetime region 2 or 2S is controlled in the range of 10 µm to 30 µm.
In addition, there was investigated the carrier density in on state when helium ion implantation position d is set to the implantation position of 30 µm of Fig. 6 where the time Trr equals that of a conventional one. As a result, the depth of the point where a density distribution of holes injected from the anode electrode 5 and a concentration distribution on the side of the N substrate 1 cross, that is, the position at which the impurity concentration of the first semiconductor layer 1 in on state equals the concentration of carriers injected into the first semiconductor layer 1, is located at the position of 58 µm when viewed from the interface S2. The helium ion implantation position d is therefore controlled in the range of from 10 µm to 30 µm, as stated earlier. Thus, by setting the helium ion implantation position d to not more than half of the depth of the point where the holes injected from the anode electrode 5 and the N substrate 1 cross, it is possible to set the recovery current dissipation time Trr to the time (the relative value of time Trr>1) longer than that of the conventional case where no diffusion of a heavy metal nor irradiation of electron beam is performed (Fig. 17).
(6) Thereafter, in view of the simulation result, a diode has been prepared experimentally in practice. In the preparation, to a pin structure in which a lifetime control to the whole has been weakened than a conventional diode, the mentioned helium ion implantation has been carried out, followed by heat treatment (anneal). Then, like the mentioned simulation, investigation has been made as to how the respective characteristics Vf, Irr and Trr depend upon helium ion implantation position. Herein, the helium ion implantation position is indicated by depth L (see Fig. 1), including the anode P layer 3 (approximately 3 µm thick). Helium ion implantation has been performed under the condition that half width of irradiated beam is 10 µm, as in the simulation, and its dose is about 10 to 100 cm-3 (see Fig. 22) in a practical relative value level. In the experimental preparation, the result of SR measurement of the diode subjected to heat treatment is also evaluated (see Figs. 4 and 8), and the point where the resistivity change of the damaged low lifetime region and the resistivity change of the N substrate cross, which corresponds to a point P in the examples of Figs. 4 and 8, is defined as helium ion implantation position L. The result of the manufactured prototype is shown in Fig. 7. Like Fig. 6, the ordinate of Fig. 7 is given as a relative value to the characteristic of a conventional structure in the absence of a region 2 (see Fig. 17).
As shown in Fig. 7, the prototype result is also almost the same as the simulation result of Fig. 6, and on state voltage Vf increases as the low lifetime region 2 (Fig. 1) becomes deeper. Recovery peak current Irr is minimized when depth L is 28 µ m, and increases when the helium ion irradiation position L is apart from that depth (=28 µm). As opposed to on state voltage Vf, recovery current dissipation time Trr decreases as position L of the low lifetime region 2 becomes deeper. In Figs. 6 and 7, even when thickness of the anode P layer 3 is reduced, there occurs a difference in the change of the recovery peak current Irr in the vicinity of the minimum value of recovery peak current Irr, with respect to the helium ion implantation position (in Fig. 7, the change of recovery current Irr is small). This seems to be caused by the fact that in the simulation of Fig. 6, the region 2S1 of Fig. 5 is treated as a non-damaged region. Therefore, it is found that the region 2S1 of Fig. 5 has to be regarded in practice as a damaged region.
From the prototype result of Fig. 7, as compared with the conventional case, recovery characteristic is improved than was previously possible, by setting position L of the low lifetime region 2 to the range of 15 µm to 40 µm (which especially gives the result that: recovery peak current Irr<1).
Fig. 8 shows the result of SR measurement obtained when a prototype has been manufactured by controlling helium ion implantation position L from the first main surface of the anode P layer 3 such as to be 28 µm in Fig. 7. As apparent from Fig. 8, the resistance of the damaged low lifetime region is over about 50 times of that before it is damaged. It is therefore desirable that the resistivity of the low lifetime region 2 is set to not less than 50 times of that of the first semiconductor layer 1. As to lifetime, in view of setting of the mentioned simulation conditions, it is desirable to establish the relationship of: (lifetime τ2 of the low lifetime region 2)< 1/10 × (lifetime τ1 of the first semiconductor layer 1). This enables to optimize the carrier density of the N type substrate 1.
Fig. 9 shows recovery characteristic obtained when helium ion implantation position L has been controlled to the position of 28 µm at which recovery peak current Irr is minimized, to form the low lifetime region 2. Fig. 10 shows the result of reverse recovery characteristic of a diode to which no helium ion implantation has been performed. In Figs. 9 and 10, symbol Ik denotes anode-cathode current. Other symbols are as described earlier. As best shown by comparison of Fig. 9 with Fig. 10, the diode of the invention in Fig. 9 has a smaller recovery peak current Irr and a longer recovery current dissipation time Trr.
(7) The foregoing description is made on the case where in a pin structure, the N type substrate 1 and anode P layer 3 are taken as a first semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type, respectively, an intermediate layer sandwitched therebetween is taken as the low lifetime region 2, and the anode electrode 5 and cathode electrode 6 are taken as first and second main electrodes, respectively (see Fig. 1). The invention is, however, not limited thereto and applicable to a semiconductor device in which (i) a p type semiconductor substrate is taken as the first semiconductor layer of the first conductivity, (ii) a p type semiconductor layer formed thereon which has a shorter lifetime and resistivity that decreases monotonically, is taken as the second semiconductor layer of the first conductivity type, (iii) a cathode n layer formed thereon is taken as the third semiconductor layer of the second conductivity type, and (iv) a cathode electrode and an anode electrode are taken as the first and second main electrodes, respectively. In this case, the second semiconductor layer is a mere damaged region upon receipt of implantation of a predetermined ion such as helium ion, and has the property of not becoming acceptor even by the subsequent heat treatment (thus, causing a monotonic decrease in resistivity).
(8) The diodes of Figs. 1, 6 and 7 have the structure based on the assumption that prior to helium ion implantation, a heavy metal such as platinum is previously diffused into the N- layer 1B and N+ layer 1A. Semiconductor fabrication techniques are, however, not limited thereto and applicable to a diode in which a low lifetime region 2 is formed by helium ion implantation, when the heavy metal is not previously diffused. Such a diode does not fall under the claimed invention. In this case, the effect owing to the heavy metal diffusion, namely, the mentioned effect ② (an increase in the carrier density on the cathode side, no change in on state voltage Vf (to a conventional diode subjected to a heavy metal diffusion), and retention of an extension of dissipation time Trr) cannot not obtained, however, the mentioned characteristic effects ① (a further decrease in current Irr) and ③ (no change in breakdown voltage) can be obtained. Accordingly, even such a structure provides a beneficial technique.
(9) The foregoing description based on Fig. 1 is made on the case where the low lifetime region 2 of Fig. 1 is formed by utilizing helium ion as a representative of light ions or predetermined ions. One other than helium ion may be utilized as a light ion. Here, the term "light ion" is used in a wider sense to comprise ions of relatively light atoms, which includes ions of atoms from helium whose atomic number is 2, to oxygen whose atomic number is 8, except for hydrogen ion, namely, proton. It is especially effective to use, as a predetermined ion, the ion of an atom such as He, Li and Be, belonging to the class of constituting no semiconductor impurity generally called donor or acceptor, to silicon.
(First Example)
(Second Preferred Embodiment)
(Summary)
INDUSTRIAL APPLICABILITY
- a first semiconductor layer (1) of a first conductivity type;
- a second semiconductor layer (2) of the first conductive type comprising both a first main surface forming interface (S1) together with a main surface of the first semiconductor layer (1) and a second main surface opposed to the first main surface,
- a third semiconductor layer (3) of a second conductivity type comprising a main surface which forms a second interface (S2) together with the second main surface of the second semiconductor layer (2), wherein a second lifetime (τ2) of carriers in the second semiconductor layer (2) is smaller than a first lifetime (τ1) of carriers in the first semiconductor layer (1) and is obtained by diffusion of a heavy metal through the semiconductor device, wherein
- a resistance value in the second semiconductor layer (2) decreases monotonically from the second interface (S2) to the first interface (S1), and is obtained by ion implantation of an ion of an atom with an atomic number from 2 to 8.
- eine erste Halbleiterschicht (1) von einem ersten Leitfähigkeitstyp;
- eine zweite Halbleiterschicht (2) von dem ersten Leitfähigkeitstyp, die sowohl eine erste Hauptoberfläche, die zusammen mit einer Hauptoberfläche der ersten Halbleiterschicht (1) eine Grenzfläche (S1) bildet, als auch eine zweite Hauptoberfläche aufweist, die der ersten Hauptoberfläche gegenüberliegt,
- eine dritte Halbleiterschicht (3) von einem zweiten Leitfähigkeitstyp, die eine Hauptoberfläche aufweist, die zusammen mit der zweiten Hauptoberfläche der zweiten Halbleiterschicht (2) eine zweite Grenzfläche (S2) bildet, wobei eine zweite Lebensdauer (τ2) von Ladungsträgern in der zweiten Halbleiterschicht (2) geringer ist als eine erste Lebensdauer (τ1) von Ladungsträgern in der ersten Halbleiterschicht (1), was durch eine Diffusion eines Schwermetalls durch die Halbleitervorrichtung erreicht wird,
- wobei der Widerstandswert in der zweiten Halbleiterschicht (2) von der zweiten Grenzfläche (S2) zu der ersten Grenzfläche (S1) monoton abnimmt, was durch eine Ionenimplantation von Ionen von Atomen mit einer Ordnungszahl von 2 bis 8 erreicht wird.
- une première couche semiconductrice (1) d'un premier type de conductivité;
- une seconde couche semiconductrice (2) du premier type de conductivité comprenant à la fois une première surface principale formant interface (S1) ensemble avec une surface principale de la première couche semiconductrice (A) et une seconde surface principale opposée à la première surface principale;
- une troisième couche semiconductrice (3) d'un second type de conductivité comprenant une surface principale qui forme une seconde interface (S2) ensemble avec la seconde surface principale de la seconde couche semiconductrice (2), dans lequel une seconde durée de vie (τ2) de porteurs dans la seconde couche semiconductrice (2) est plus courte qu'une première durée de vie (τ1) de porteurs dans la première couche semiconductrice (A) et est obtenue par diffusion d'un métal lourd à travers le dispositif semi-conducteur,
dans lequel une valeur de résistance dans la seconde couche semiconductrice (2) diminue de façon monotone depuis la seconde interface (S2) vers la première interface (S1), et est obtenue par implantation ionique d'un ion d'un atome avec un numéro atomique de 2 à 8.REFERENCES CITED IN THE DESCRIPTION
Patent documents cited in the description
Non-patent literature cited in the description