(19)
(11)EP 2 680 312 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
03.08.2016 Bulletin 2016/31

(43)Date of publication A2:
01.01.2014 Bulletin 2014/01

(21)Application number: 13173277.8

(22)Date of filing:  21.06.2013
(27)Previously filed application:
 29.06.2012 US 201213537619
(51)International Patent Classification (IPC): 
H01L 29/78(2006.01)
H01L 21/336(2006.01)
H01L 29/10(2006.01)
H01L 29/06(2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30)Priority: 29.06.2012 US 201213537619

(71)Applicant: Freescale Semiconductor, Inc.
Austin, TX 78735 (US)

(72)Inventors:
  • Yang, Hongning
    Chandler, AZ Arizona 85249 (US)
  • Blomberg, Daniel J
    Chandler, AZ Arizona 85224 (US)
  • Zuo, Jiang-Kai
    Chandler, AZ Arizona 85249 (US)

(74)Representative: Freescale law department - EMEA patent ops 
NXP Semiconductors, 134 avenue du Général Eisenhower BP 72329
31023 Toulouse Cedex 1
31023 Toulouse Cedex 1 (FR)

  


(54)High breakdown voltage LDMOS device


(57) A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).







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