(19)
(11)EP 0 899 741 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
15.12.1999 Bulletin 1999/50

(43)Date of publication A2:
03.03.1999 Bulletin 1999/09

(21)Application number: 98116222.5

(22)Date of filing:  27.08.1998
(51)International Patent Classification (IPC)6G11C 7/00
(84)Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
Designated Extension States:
AL LT LV MK RO SI

(30)Priority: 28.08.1997 JP 232849/97

(71)Applicant: NEC CORPORATION
Tokyo (JP)

(72)Inventor:
  • Kawaguchi, Yasunari NEC IC Microcomp. Systems, Ltd
    Kawasaki-shi, Kanagawa (JP)

(74)Representative: Glawe, Delfs, Moll & Partner 
Patentanwälte Postfach 26 01 62
80058 München
80058 München (DE)

  


(54)Burst mode type semiconductor memory device


(57) In a semiconductor memory device having a burst function, a memory circuit (2) inputs and outputs information corresponding to an external input signal (A1-A10) in synchronization with an internal clock signal (S4). A burst operation control circuit receives an external reference clock signal (CX) and an enable signal (E1) for switching a burst operation mode and a stand-by mode, so as to suspend supplying of the external input signal in the burst operation mode and suspend generation of the first internal clock signal in the stand-by mode.







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