(19)
(11)EP 1 058 194 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
10.03.2010 Bulletin 2010/10

(43)Date of publication A2:
06.12.2000 Bulletin 2000/49

(21)Application number: 00120146.6

(22)Date of filing:  19.07.1996
(51)Int. Cl.: 
G06F 15/80  (2006.01)
G06F 15/173  (2006.01)
(84)Designated Contracting States:
AT BE CH DE DK ES FI FR GB GR IE IT LI NL PT SE

(30)Priority: 21.07.1995 US 505513

(62)Application number of the earlier application in accordance with Art. 76 EPC:
96924569.5 / 0842473

(71)Applicant: Reed, Coke S.
Princeton, NJ 08540 (US)

(72)Inventor:
  • Reed, Coke S.
    Princeton, NJ 08540 (US)

(74)Representative: Gill, David Alan 
W.P. Thompson & Co. 55 Drury Lane
London WC2B 5SQ
London WC2B 5SQ (GB)

  


(54)Multiple level minimum logic network


(57) A network or interconnect structure utilizes a data flow technique that is based on timing and positioning of messages communicating through the interconnect structure. Switching control is distributed throughout multiple nodes in the structure so that a supervisory controller providing a global control function and complex logic structures are avoided. The interconnect structure operates as a "deflection" or "hot potato" system in which processing and storage overhead at each node is minimized. Elimination of a global controller and buffering at the nodes greatly reduces the amount of control and logic structures in the interconnect structure, simplifying overall control components and network interconnect components and improving speed performance of message communication.