(19)
(11)EP 1 126 652 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
25.02.2009 Bulletin 2009/09

(43)Date of publication A2:
22.08.2001 Bulletin 2001/34

(21)Application number: 01102886.7

(22)Date of filing:  14.02.2001
(51)Int. Cl.: 
H04L 1/00  (2006.01)
(84)Designated Contracting States:
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
Designated Extension States:
AL LT LV MK RO SI

(30)Priority: 14.02.2000 JP 2000035584

(71)Applicant: NEC CORPORATION
Tokyo (JP)

(72)Inventors:
  • Kazuo, Takagi
    Minato-ku, Tokyo (JP)
  • Naoya, Henmi
    Minato-ku, Tokyo (JP)
  • Shinobu, Sasaki
    Minato-ku, Tokyo (JP)
  • Kurenai, Murakami
    Minato-ku, Tokyo (JP)
  • Motoo, Nishihara
    Minato-ku, Tokyo (JP)
  • Yoshinori, Rokugou
    Minato-ku, Tokyo (JP)

(74)Representative: Vossius & Partner 
Siebertstrasse 4
81675 München
81675 München (DE)

  


(54)Method and system for transmission and reception of asynchronously multiplexed signals


(57) A storage circuit (14) defines a first field for storing first header bits of a first payload signal of a first data unit, a second field, and a third field for storing the first payload signal. The first header bits are equal in number to second header bits of a second payload signal of a second data unit. A division circuit (15, 16) divides the first header bits by a generator polynomial G(x) to produce a first error check code. The same generator polynomial is used to divide the second header bits to produce a second error check code. A remainder of division of hypothetical header bits by the generator polynomial G(x) is summed to the first error check code to produce a sum which is inserted into the second field of the storage circuit. The hypothetical header bits are greater in number than a total number of bits in the first and second fields, so that the first and second data units can be distinguished from each other by different error check results of the first and second data units.