(19)
(11)EP 1 291 906 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.11.2009 Bulletin 2009/45

(21)Application number: 01915802.1

(22)Date of filing:  27.03.2001
(51)Int. Cl.: 
H01L 21/3205  (2006.01)
H01L 21/768  (2006.01)
H01L 21/3213  (2006.01)
H01L 21/60  (2006.01)
(86)International application number:
PCT/JP2001/002437
(87)International publication number:
WO 2001/080299 (25.10.2001 Gazette  2001/43)

(54)

FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE

VERFAHREN ZUR HERSTELLUNG EINES HALBLEITERBAUELEMENTS

PROCEDE DE FABRICATION D'UN DISPOSITIF SEMI-CONDUCTEUR


(84)Designated Contracting States:
BE DE FR GB IT NL

(30)Priority: 19.04.2000 JP 2000118227

(43)Date of publication of application:
12.03.2003 Bulletin 2003/11

(73)Proprietors:
  • Toyo Kohan Co., Ltd.
    Tokyo 102-8447 (JP)
  • Suga, Tadatomo
    Tokyo 153-0041 (JP)

(72)Inventors:
  • SUGA, Tadatomo
    Meguro-ku, Tokyo 153-0041 (JP)
  • SAIJO, K., TOYO KOHAN CO., LTD
    Kudamatsu-shi, Yamaguchi 744-8611 (JP)
  • OHSAWA, S., TOYO KOHAN CO., LTD
    Kudamatsu-shi Yamaguchi 744-8611 (JP)
  • OKAMOTO, H., TOYO KOHAN CO., LTD.
    Kudamatsu-shi, Yamaguchi 744-8611 (JP)
  • YOSHIDA, K, TOYO KOHAN CO., LTD.
    Kudamatsu-shi, Yamaguchi 744-8611 (JP)

(74)Representative: Vossius & Partner 
Siebertstrasse 4
81675 München
81675 München (DE)


(56)References cited: : 
EP-A- 0 734 065
JP-A- 2000 243 774
JP-A- 2001 093 928
WO-A-00/11715
JP-A- 2001 093 905
  
  • PATENT ABSTRACTS OF JAPAN vol. 1996, no. 05, 31 May 1996 (1996-05-31) -& JP 08 005664 A (HITACHI CHEM CO LTD), 12 January 1996 (1996-01-12)
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical Field



[0001] This invention concerns a chip-size semiconductor device formed with conductor wirings for re-arranging electrodes on an IC chip and it, particularly, relates to a fabrication method capable of collective processing at the wafers.

Background Art



[0002] In recent years, size-reduction, enhancement for function, higher integration degree and multiple pin arrangement have been progressed remarkably for IC package. Further, CSP as a package of a size identical with a chip-size has been developed recently.

[0003] JP-A-11-121507 proposes a method of packaging in a state of wafer and fabricating a chip-size package. However, in this method, bumps for connecting an IC package with the outside are formed at electrode positions in IC. In recent trend for the reduction of chip-size and multiple pin arrangement, the pitch for arranging electrodes of the chip has been narrowed more and more and it is necessary to re-arrange the electrodes on the IC chip to expand the electrode pitch for facilitating subsequent mounting.

[0004] This invention intends to solve the foregoing problems in the prior art and provide a method of fabricating a chip-size package in which the electrode pitch is extended by forming conductor wirings on the side of the electrode forming surface of a semiconductor element efficiently and at a reduced cost and, particularly, to provide a method capable of forming wirings and bumps easily.

[0005] The present inventors have found that the foregoing object can be solved by laminating a wiring-forming metal foil on the side of forming electrodes of a semiconductor wafer formed at the surface thereof with circuit elements by using a bonding technique between a metal foil and ceramics previously filed by the present inventors (refer to International Publication No. WO99/58470), and then etching the metal foil to form wirings and dividing the same into individual elements.

Disclosure of the Invention



[0006] It has been found for the formation of bumps that bumps can be formed by laminating a wiring-forming multi-layered metal foil to a semiconductor wafer formed at the surface thereof with circuit elements on the side of the electrode forming surface and by merely etching the wirings having bumps thereon.

[0007] This invention is described in claim 1.

[0008] According to this invention, the method of fabricating a semiconductor device includes a step of laminating a wiring-forming multi-layer metal foil comprising a bump-forming layer, an etching stopper layer and a wiring-forming layer to a semiconductor wafer formed at the surface thereof with circuit elements on the electrode forming surface side, a step of forming a bump-forming resist wiring pattern on the bump-forming layer, a step of selectively etching the bump-forming layer down to the etching stopper layer, a step of removing the exposed portion of the etching stopper layer, a step of forming a wiring-forming resist wiring pattern, a step of forming wirings by etching of the wiring-forming layer, a step of removing the wiring-forming resist, and a step of dividing into individual elements.

[0009] In the fabrication method of the semiconductor device, it is preferred that the wiring-forming multi-layered metal foil is a metal laminate comprising the three layers of a bump forming copper or solder foil layer, an etching stopper layer of nickel and a wiring forming copper foil layer. Further, it is preferred that the thickness of the bump-forming copper or soldering foil is 10 to 100 µm. Further, the etching stopper layer nickel is preferably formed by nickel plating of 0.5 to 3 µm thickness or is a nickel foil clad of 1 to 10 µm thickness. Further, it is preferred that the thickness of the wiring-forming copper foil is 1 to 100 µm.

[0010] Further, in the method of fabricating the semiconductor device, the semiconductor wafer formed at the surface thereof with circuit elements is preferably a semiconductor wafer formed at the surface thereof with a thin metal film.

[0011] Preferably method of fabricating the semiconductor device according to this invention includes a step of coating an insulative resin and polishing the surface thereof, and a step of forming solder bumps between the step of removing the wiring-forming resist and the step of dividing into individual elements.

Brief Description of the Drawings



[0012] Fig. 1 is a view showing an example of a circuit forming step for a first embodiment and a second embodiment outside this invention (step of laminating a wiring copper foil on a semiconductor wafer). Fig. 2 is a view showing an example of a circuit forming step in a first embodiment and a second embodiment outside this invention (step of forming conductor wirings on the wiring copper foil). Fig. 3 is a view showing an example of a circuit forming step in the first embodiment outside this invention (step of cutting into individual elements). Fig. 4 is a view showing an example of a circuit forming step in the first embodiment outside this invention (element after cutting). Fig. 5 is a view showing an example of a circuit forming step in the second embodiment outside this invention (step of forming solder bumps on wiring copper foil). Fig. 6 is a view showing an example of a circuit forming step in the second embodiment outside this invention (step of cutting into individual elements). Fig. 7 is a view showing an example of a circuit forming step in the second embodiment outside this invention (element after cutting). Fig. 8 is a view showing an example of a circuit forming step in a first embodiment according to this invention (step of laminating a wiring copper foil on a semiconductor wafer). Fig. 9 is a view showing an example of a circuit forming step in the first embodiment according to this invention (forming bumps). Fig. 10 is a view showing an example of a circuit forming step in the first embodiment according to this invention (selective etching of etching stopper layer nickel). Fig. 11 is a view showing an example of a circuit forming step in the first embodiment according to this invention (selective etching of wiring-forming copper foil). Fig. 12 is a view showing an example of a circuit forming step in the first embodiment according to this invention (step of cutting into individual elements) . Fig. 13 is a view showing an example of a circuit forming step in the first embodiment according to this invention (element after cutting). Fig. 14 is a view showing a step of coating an insulative resin and surface polishing in a further embodiment according to this invention. Fig. 15 is a view showing a step of forming solder bumps in the further embodiment according to this invention. Fig. 16 is a view showing a step of cutting into individual elements in the further embodiment according to this invention. Fig. 17 is a view showing an element after cutting in the further embodiment according to this invention. Fig. 18 is a front elevational view of an element after cutting in the first or further embodiment according to this invention.

Best Mode for Practicing the Invention



[0013] At first, a first embodiment outside this invention is to be described.

[0014] The first embodiment concerns a semiconductor device comprising a semiconductor wafer formed at the surface thereof with circuit elements, and conductor wirings on the semiconductor element formed by etching a wiring-forming metal foil.

[0015] As the semiconductor, a semiconductor wafer or the like used ordinarily can be used and, as the wiring-forming metal foil, a foil preferably formed of copper with a thickness of 1 to 100 µmcan be used. The conductor wirings can be formed appropriately into a desired shape.

[0016] The semiconductor device in the first embodiment can be fabricated by a method of fabricating a semiconductor device including a step of laminating a wiring-forming metal foil to a semiconductor wafer formed at the surface thereof with circuit elements on the electrode-forming surface side, a step of forming a resist wiring pattern on the metal foil, a step of etching the metal foil and a step of dividing into individual elements.

[0017] As the substrate, those used ordinarily such as a semiconductor wafer formed at the surface thereof with circuit elements can be used. As the wiring-forming metal foil, a foil preferably formed of copper and of 1 to 100 µm thickness can be used as described above

[0018] Depending on the case, a thin metal film can be provided on the semiconductor wafer formed at the surface thereof with circuit elements by using a sputtering method, a vapor deposition method or the like after surface cleaning. This can facilitate lamination of the metal foil on the semiconductor wafer. As the metal forming the thin film, Cr, Mo, W or the like is used as a barrier metal in a case where the chip electrode of the semiconductor is Al, but the subsequent removal by etching is difficult. Then, with a view point for the ease of etching elimination, use of nickel is preferred.

[0019] Lamination of the wiring-forming metal foil to the semiconductor wafer can be conducted by using the technique described in International Publication No. WO99/58470 previously filed by the present inventors (Fig. 1).

[0020] After lamination, a resist is coated on the wiring forming metal foil and then exposure and development are conducted to form a resist wiring pattern. The resist wiring pattern is formed preferably such that it can be easily divided subsequently into individual elements and it can adopt, for example, a method of not coating the resist to portions for the division.

[0021] A series of procedures such as resist coating, exposure and development can be conducted based on the ordinary method.

[0022] Then, the wiring-forming metal foil is etched. In a case where the metal foil is copper, a commercially available alkali type copper etching solution can be used as the etching solution.

[0023] Successively, the resist is removed to form wirings (Fig. 2)

[0024] Finally, it is divided into individual elements that is, as described above, in a case where the portions for the division formed upon resist wiring pattern formation for indicating the boundary between each of individual element regions are made distinct, it is divided into individual elements with reference to the portions (Fig. 3, 4).

[0025] Division is conducted by using a diamond blade, laser or the like.

[0026] A second embodiment outside this invention is to be described.

[0027] The second embodiment concerns a semiconductor device comprising a semiconductor element, conductor wirings on the semiconductor element formed by etching a wire-forming metal foil and solder bumps.

[0028] The semiconductor, the wiring-forming metal foil and the conductor wirings are identical with those described for the first embodiment.

[0029] The semiconductor device described above can be fabricated by a method of fabricating a semiconductor device including a step of laminating a wiring-forming metal foil to a semiconductor wafer formed at the surface thereof with circuit elements on the electrode forming surface side, a step of forming a resist wiring pattern on the metal foil, a step of etching the metal foil, a step of forming solder bumps and a step of dividing into individual elements.

[0030] As the substrate, a semiconductor wafer formed at the surface thereof with circuit elements can be used usually and, depending on the case, a thin metal film can be provided after surface cleaning of the semiconductor wafer or the like. Further, lamination of the wiring-forming metal foil to the semiconductor wafer can be conducted in the same manner as in the first embodiment of this invention, by using the technique described in International Publication No. WO99/58470 previously filed by the present inventors (Fig. 1).

[0031] After the lamination, like the first embodiment, a resist is coated on the wiring-forming metal foil and then exposure and development are conducted to form a resist wiring pattern and, successively, the wiring-forming metal foil is etched and then the resist is removed to form wirings (Fig. 2). The resist wiring pattern is preferably applied so as to be divided easily into individual elements subsequently like the first embodiment.

[0032] In the second embodiment, solder bumps are successively formed (Fig. 5). The solver bumps are formed at the positions for re-arranging electrodes.

[0033] Finally, it is divided into individual elements (Fig. 6, 7). Division is identical with that in the first embodiment.

[0034] Successively, a first embodiment according to this invention is to be explained.

[0035] The first embodiment of this invention concerns forming a semiconductor device comprising a semiconductor element, and conductor wirings having bumps on the semiconductor element formed by etching the wiring-forming multi-layered metal foil.

[0036] The semiconductor device, the wiring-forming metal foil and the conductor wirings are identical with those described for the first embodiment and the second embodiment outside this invention.

[0037] The thickness of the conductor wirings is 1 to 100 µm as described above, and for the etching stopper layer, nickel plating of 0. 5 to 3 µm thickness, preferably, 1 to 2 µm thickness, or nickel foil clad of 1 to 10 µm thickness, preferably, 2 to 5 µm thickness can be used.

[0038] The thickness of the bump is 10 to 100 µm, preferably, 10 to 50 µm

[0039] The semiconductor device can be fabricated by a method of fabricating a semiconductor device including a step of laminating a wiring-forming multi-layered metal foil comprising a bump-forming layer, an etching stopper layer and a wiring-forming layer to a semiconductor wafer formed at the surface thereof with circuit elements on the electrode forming surface side, a step of forming a bump-forming resist wiring pattern on the bump-forming layer, a step of selectively etching the bump-forming layer down to the etching stopper layer, a step of removing the exposed portions of the etching stopper layer, a step of forming a wiring-forming resist wiring pattern, a step of forming wirings by etching of the wiring forming layer, a step of removing the wiring-forming resist, and a step of dividing into individual elements.

[0040] At first, a wiring-forming metal laminate is laminated to the semiconductor wafer formed at the surface thereof with circuit elements on the electrode forming surface side (Fig. 8). For the wiring-forming metal laminate, a metal laminate comprising, for example, a bump-forming copper or solder foil (10 to 100µm thickness)/etching stopper layer nickel (0.5 to 3 µm thickness in a case of plating and 1 to 10 µm thickness in a case of foil)/wiring copper foil (1 to 100 µm) is used.

[0041] Lamination can be conducted in the same manner as described for the portion of the first embodiment and the second embodiment outside of this invention.

[0042] After the lamination, resist is coated on the metal laminate and then exposure and development are conducted to form a bump-forming resist pattern.

[0043] Then, the bump forming layer in the metal laminate is selectively etched (Fig. 9). In a case where the bump-forming layer is a copper foil, etching is conducted by using a selective copper etching solution such a commercially available alkali type copper etching solution to form bumps.

[0044] Successively, the etching stopper layer is removed.

[0045] In a case where the etching stopper layer is nickel plating or foil, a commercially available nickel removing solution (for example, N-950, manufactured by Mertex Co.) can be used (Fig. 10).

[0046] Further, a wiring-forming resist wiring pattern is formed. In this case, the resist wiring pattern is preferably applied so as to indicate the boundary between each of element regions corresponding to the division into individual element regions to be described later, which is identical with that for the first embodiment and the second embodiment outside of this invention.

[0047] Successively, the wiring layer is etched. In a case where the wiring layer is copper, a commercially available alkali type copper etching solution or the like can be used. After forming wirings by etching, the resist is removed (Fig. 11).

[0048] Finally, it is divided into individual elements (Fig. 12, 13). Division can be conducted by the same means as in the first and the second embodiments outside of this invention.

(Example)


Example 1 (First Embodiment outside of This Invention)


(1) Material



[0049] A semiconductor wafer 1 formed at the surface thereof with circuit elements and a wiring-forming copper foil (15 µm thickness) 2 laminated by the method disclosed in International Publication WO99/58470 were used as a substrate (Fig. 1).

[0050] Before lamination, a thin metal film (nickel) was provided on the semiconductor wafer by using, for example, a sputtering method or a vapor deposition method.

(2) Formation of wirings



[0051] After coating a resist on the copper foil, exposure and development were conducted to form a resist wiring pattern. Then, copper was etched to form wirings 3 (Fig. 2).

(3) It was divided into individual elements (Figs. 3, 4, 18)


Example 2 (Second Embodiment outside of This Invention)


(1) Material



[0052] A semiconductor wafer 1 formed at the surface thereof with circuit elements and a wiring-forming copper foil (15 µm thickness) 2 laminated in the same manner as in Example 1 were used as a substrate (Fig. 1).

(2) Formation of wirings



[0053] After coating a resist on the copper foil, exposure and development were conducted to form a wiring-forming resist wiring pattern. Then, copper was etched to form wirings 3 (Fig. 2).

(3) Formation of solder bumps



[0054] Solder bumps 4 were formed on wirings at the positions for re-arranging electrodes (Fig. 5).

(4) It was divided into individual elements (Figs 6, 7, 18).


Example 3 (First Embodiment of This Invention)


(1) Material



[0055] A metal laminate comprising bump forming copper foil (35 µm thickness) 5/etching stopper layer of nickel (plating thickness of 1 µm) 6/wiring-forming copper foil (15 µm) 1 was laminated to a semiconductor wafer formed at the surface thereof with circuit elements (identical with that used in Example 1. (Fig. 8).

(2) Pattern formation



[0056] After coating a resist on the metal laminate, exposure and development were conducted to form a bump-forming resist wiring pattern.

(3) Etching



[0057] Copper was selectively etched by using a commercially available copper etching solution such as an alkali type copper etching solution to form bumps 7 (Fig. 9).

(4) Removal of etching stopper layer



[0058] The etching stopper layer of nickel 6 was removed by using a commercially available nickel removing solution (N-950, manufactured by Mertex Co.) (Fig. 10)

(5) A wiring-forming resist wiring pattern was formed.


(6) Etching was conducted by using a copper etching solution such as an alkali type copper etching solution to form wirings 3 and then the resist was removed (Fig. 11).


(7) It was divided into individual elements (Fig. 12, 13, 18).


Example 4 (Further Embodiment of This Invention)


(1) Material



[0059] A metal laminate comprising bump forming copper foil (35 µm thickness) 5/etching stopper layer of nickel (plating thickness 1 µm) 6/wiring-forming copper foil (15 µm 1 was laminated to a semiconductor wafer formed at the surface thereof with circuit elements (identical with that used in Example 1 (Fig. 8).

(2) Pattern formation



[0060] After coating a resist on the metal laminate, exposure and development were conducted to form a bump-forming resist wiring pattern.

(3) Etching



[0061] Copper was selectively etched by using a commercially available copper etching solution such as an alkali type copper etching solution to form bumps 7 (Fig. 9).

(4) Removal of etching stopper layer



[0062] The etching stopper layer of nickel 6 was removed by using a commercially available nickel removing solution (N-950, manufactured by Mertex Co.) (Fig. 10)

(5) A wiring-forming resist wiring pattern was formed.


(6) Etching was conducted by using a copper etching solution such as an alkali type copper etching solution to form wirings 3 and then the resist was removed (Fig. 11).


(7) An insulative resin such as a polyimide is coated entirely on the semiconductor wafer to apply resin encapsulation. Subsequently, polishing is conducted so as to expose copper bumps to the surface (Fig. 14).


(8) Solder bumps are formed by using a printing method or the like (Fig. 15)


(9) It was divided into individual elements (Fig. 16, 17, 18).


Industrial Applicability



[0063] According to this invention, a chip-size package in which an electrode pitch is expanded by forming conductor wirings to a semiconductor on the electrode forming surface side can be fabricated efficiently and at a reduced cost. Particularly, wirings and bumps can be formed easily.

[0064] Accordingly, the wiring forming method according to this invention is useful in the field of semiconductors.


Claims

1. A semiconductor device as defined in claim 1 or 2, wherein the wiring-forming metal foil has a thickness of 1 to 100 µm. 4. A method of fabricating a semiconductor device including a step of laminating a wiring-forming multi-layered metal foil to a semiconductor wafer formed at the surface thereof with circuit elements on the electrode forming surface side, wherein the wiring-forming multi-layered metal fal comprises a bump-forming layer, an etching stopper layer and a wiring- forming layer, a step of forming a bump-forming resist wiring pattern on the bump-forming layer, a step of selectively etching the bump-forming layer down to the etching stopper layer to expose portions thereof, a step of removing the exposed portions of the etching stopper layer, a step of forming a wiring-forming resist wiring pattern, a step of forming wiring by etching of the wiring-forming layer a step of removing the wiring-forming resist , and a step of dividing into individual elements.
 
2. A method of fabricating a semiconductor device as defined in claim 1, wherein the wiring-forming multi-layered metal foil comprises the three layers of bump-forming copper or solder foil layer, an etching stopper layer of nickel, and a wiring-forming copper foil layer.
 
3. A method of fabricating a semiconductor device as defined in claim 2, wherein the thickness of the bump forming copper or solder foil is 10 to 100 µm.
 
4. A method of fabricating a semiconductor device as defined in claim 2 or 3, wherein the etching stopper layer of nickel is formed by nickel plating of 0.5 to 3 µm thickness or is a nickel foil clad of 1 to 10 µm thickness.
 
5. A method of fabricating a semiconductor device as defined in any one of claims 2 to 4 in which the thickness of the wiring-forming copper foil is 1 to 100 µm
 
6. A method of fabricating a semiconductor device as defined in any one of claims 1 to 5 in which the semiconductor wafer formed at the surface thereof with circuit elements is a semiconductor wafer formed at the surface thereof with a thin metal film.
 
7. A method of fabricating a semiconductor device as defined in any one of claims 1 to 6, further including the following steps between the step of removing the wiring-forming resist and the step of dividing into individual elements: a step of coating an insulative resin and polishing the surface thereof and a step of forming solder bumps.
 


Ansprüche

1. Verfahren zum Herstellen eines Halbleiterelements mit:

einem Schritt zum Laminieren einer verdrahtungsbildenden, mehrschichtigen Metallfolie auf einen Halbleiterwafer, auf dessen Oberfläche auf der elektrodenbildenden Oberflächenseite Schaltungselemente ausgebildet werden, wobei die verdrahtungsbildende, mehrschichtige Metallfolie eine anschlussbildende Schicht, eine Ätzstoppschicht und eine verdrahtungsbildende Schicht aufweist;

einem Schritt zum Ausbilden eines anschlussbildenden Resistverdrahtungsmusters auf der anschlussbildenden Schicht;

einem Schritt zum selektiven Ätzen der anschlussbildenden Schicht bis herab zur Ätzstoppschicht, um Abschnitte davon freizulegen;

einem Schritt zum Entfernen der freigelegten Abschnitte der Ätzstoppschicht;

einem Schritt zum Ausbilden eines verdrahtungsbildenden Resistverdrahtungsmusters;

einem Schritt zum Ausbilden einer Verdrahtung durch Ätzen der verdrahtungsbildenden Schicht;

einem Schritt zum Entfernen des verdrahtungsbildenden Resists; und

einem Schritt zum Teilen in einzelne Elemente.


 
2. Verfahren nach Anspruch 1, wobei die verdrahtungsbildende, mehrschichtige Metallfolie die drei folgenden Schichten aufweist:

eine anschlussbildende Kupfer- oder Lötmaterialfolienschicht, eine Ätzstoppschicht aus Nickel und eine verdrahtungsbildende Kupferfolienschicht.


 
3. Verfahren nach Anspruch 2, wobei die Dicke der anschlussbildenden Kupfer- oder Lötmaterialfolienschicht 10 bis 100 um beträgt.
 
4. Verfahren nach Anspruch 2 oder 3, wobei die Ätzstoppschicht aus Nickel durch Plattieren von Nickel in einer Dicke von 0,5 bis 3 µm hergestellt wird oder eine Nickelfolienauflage mit einer Dicke von 1 bis 10 µm ist.
 
5. Verfahren nach einem der Ansprüche 2 bis 4, wobei die Dicke der verdrahtungsbildenden Kupferfolie 1 bis 100 µm beträgt.
 
6. Verfahren nach einem der Ansprüche 1 bis 5, wobei der Halbleiterwafer, auf dessen Oberfläche Schaltungselemente ausgebildet werden, ein Halbleiterwafer ist, auf dessen Oberfläche eine dünne Metallschicht ausgebildet ist.
 
7. Verfahren nach einem der Ansprüche 1 bis 6, ferner mit den folgenden Schritten zwischen dem Schritt zum Entfernen des verdrahtungsbildenden Resists und dem Schritt zum Teilen in einzelne Elemente:

Beschichten mit einem Isolierharz und Polieren seiner Oberfläche; und

Ausbilden von Lötstellen.


 


Revendications

1. Procédé de fabrication d'un dispositif semi-conducteur comprenant une étape de laminage d'une feuille métallique multicouche formant un câblage en une tranche de semi-conducteur formée à la surface de celui-ci avec des éléments de circuit sur le côté de la surface formant l'électrode, dans lequel la feuille métallique multicouche formant un câblage comprend une couche formant une bosse, une couche d'agent d'arrêt de gravure et une couche de formation de câblage, une. étape de formation d'un motif de câblage de réserve formant une bosse sur la couche de formation de bosse, une étape de gravure sélective de la couche de formation de bosse jusqu'à la couche d'agent d'arrêt de gravure pour exposer des parties de celle-ci, une étape de retrait des parties exposées de la couche d'agent d'arrêt de gravure, une étape de formation d'un motif de câblage de réserve formant un câblage, une étape de formation d'un câblage par gravure de la couche de formation de câblage, une étape de retrait de la réserve de formation de câblage, et une étape de division en éléments individuels.
 
2. Procédé de fabrication d'un dispositif semi-conducteur selon la revendication 1, dans lequel la feuille métallique multicouche formant un câblage comprend les trois couches de cuivre ou la couche de feuille de soudure formant une bosse, une couche d'agent d'arrêt de gravure de nickel, et une couche de feuille de cuivre formant un câblage.
 
3. Procédé de fabrication d'un dispositif semi-conducteur selon la revendication 2, dans lequel l'épaisseur de la feuille de cuivre ou de soudure formant la bosse est de 10 à 100 µm.
 
4. Procédé de fabrication d'un dispositif semi-conducteur selon les revendications 2 ou 3, dans lequel la couche d'agent d'arrêt de gravure de nickel est formée par un placage de nickel d'une épaisseur de 0,5 à 3 µm ou d'un placage d'une feuille de nickel d'une épaisseur de 1 à 10 µm.
 
5. Procédé de fabrication d'un dispositif semi-conducteur selon l'une quelconque des revendications 2 à 4, dans lequel l'épaisseur de la feuille de cuivre formant le câblage est de 1 à 100 µm.
 
6. Procédé de fabrication d'un dispositif semi-conducteur selon l'une quelconque des revendications 1 à 5, dans lequel la tranche de semi-conducteur formée à la surface de celui-ci avec des éléments de circuit est une tranche de semi-conducteur formée à la surface de celui-ci avec un film métallique mince.
 
7. Procédé de fabrication d'un dispositif semi-conducteur selon l'une quelconque des revendications 1 à 6, comprenant également les étapes suivantes entre l'étape de retrait de la réserve de formation de câblage et l'étape de division en éléments individuels, une étape de couverture d'une résine isolante et de polissage de la surface de ceux-ci, et une étape de formations de bosses de soudure.
 




Drawing
























REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description