(19)
(11)EP 0 521 525 A2

(12)EUROPEAN PATENT APPLICATION

(43)Date of publication:
07.01.1993 Bulletin 1993/01

(21)Application number: 92111358.5

(22)Date of filing:  03.07.1992
(51)International Patent Classification (IPC)5H04L 27/22
(84)Designated Contracting States:
BE DE FR GB

(30)Priority: 04.07.1991 IL 98730

(71)Applicant: Technion Research & Development Foundation Ltd.
Haifa 32000 (IL)

(72)Inventor:
  • Bar-David, Israel
    34 982 Haifa (IL)

(74)Representative: Modiano, Guido, Dr.-Ing. et al
Baaderstrasse 3
D-80469 München
D-80469 München (DE)


(56)References cited: : 
  
      


    (54)Delay demodulation method, for DPSK, insensitive to carrier frequency offsets


    (57) A method for demodulating a modulated signal having a carrier component and a data component, in which the modulated signal is split into at least two parts one of which is delayed with respect to the other, and the two parts are multiply-coupled and linearly-combined to produce a combined output corresponding to a function of the data component independent of the carrier component frequency. The undelayed part is coupled with the delayed part in a multiport coupler, wherein the parts are relatively phase-shifted to produce a plurality of phase-shifted signals; and the phase-shifted signals are linearly combined such that the data component, in the function of the combined output, is not affected by variations in frequency or phase of the carrier component.




    Description


    [0001] The present invention relates to a method for demodulating an electrical signal. The method of the present invention is particularly useful for demodulating a differential phase-shift keying signal, and is therefore described below particularly with respect to this application.

    [0002] In traditional phase modulation, a data signal Φ(t) is impressed on a carrier signal of frequency fc to produce a modulated signal of amplitude A





    where the phase angle Φ(t) is either 0 or π and may change only at integral multiples of the symbol (or bit period) duration τ. In a conventional method of differential demodulation, a delayed version of the received signal is used for phase reference to the incoming signal, whereupon a multiplier is often used to generate the product:





    After lowpass filtering this includes only the phase-difference term:





    It would be convenient if the term product fcτ would be an integer because then





    and since the phase difference, which we denote by

    , is either 0 or π, depending on the modulating data, the cosine of it is respectively, 1 or -1, yielding exact demodulation. If, however, the term product fcτ is not an integer because of uncertainties of frequency, and if the quantity denoted by α is equal to 2πfcτ, modulo 2π, then the following phase shifted angle obtains:





    Since

    for both signal data alternatives, the result reduces to

    ; and if α is arbitrary, cos α can take on arbitrary values between -1 and +1, including zero, in which case the output is useless.

    [0003] The inevitable conclusion is that under frequency uncertainties, where the term product fcτ can shift from a pre-designed integer value by a fraction (δf)τ such that 2n(δf)τ becomes comparable to 1 radian, the conventional detection method is not satisfactory.

    [0004] Such frequency uncertainty is present in various radio frequency applications because of, for example, unknown Doppler shifts, as well as in optical communication systems that use semiconductor lasers of relatively unstable frequency. It should be noted that α is in effect a time-varying quantity but its variations, mostly because of the thermal effects in the oscillators and in varying Doppler shifts, are relatively slow, as compared to the data rate in Φ(t).

    [0005] According to the present invention, there is provided a method of demodulating a modulated signal having a carrier component and a data component, in which the modulated signal is split into at least two parts one of which is delayed with respect to the other, and the two parts are multiply-coupled and linearly-combined to produce a combined output corresponding to a function of the data component independent of the carrier component; characterized in that: the undelayed part is coupled with the delayed part in a multiport coupler, wherein the parts are relatively phase-shifted to produce a plurality of phase-shifted signals; and the phase-shifted signals are linearly combined such that the data component, in the function of the combined output, is not affected by variations in frequency or phase of the carrier component.

    [0006] It is thus seen that the invention uses a plurality of phases in a multiphase differential detection to overcome the frequency uncertainty problem.

    [0007] A demodulator operating in accordance with the foregoing method is insensitive to frequency and phase variations in the carrier signal because, when the frequency or phase changes, it alters the plurality of phase-shifted signals in a way such that their linearly combined outputs remain constant independently of frequency or phase. Prior art demodulators, using only a single phase output, are subject to variations which can even lead to complete destruction of the output variable.

    [0008] The invention is described below, for purposes of example, as included in a homodyne type demodulator and in a heterodyne type demodulator.

    [0009] In the homodyne type demodulator, the delayed and undelayed parts resulting from the splitting of the initial modulated signal are fed to a 2-port 90°-hybrid coupler, producing two relatively 90°-shifted output signals; or alternatively, to a 3-port symmetrical coupler producing an unshifted output signal, a 120°-shifted output signal, and a 240°-shifted output signal. The combined output of the demodulator, corresponding to a function of the data component independent of the carrier component frequency, is produced by linearly combining the three output signals from the multiport coupler in a base-band phase equalizer (BBPE) to be described below.

    [0010] In the heterodyne type demodulator described herein, the original modulated signal is fed with a local oscillator signal to a 90°-hybrid coupler producing two relatively 90°-shifted output signals; or alternatively, to a 3-port symmetrical coupler producing an unshifted output signal, a 120°-shifted output signal, and a 240°-shifted output signal. The input to the BBPE is produced by mixing and lowpass filtering the two output signals from the 90°-hybrid; or alternatively the three output signals from the 3-port coupler with the delayed replica of one of them. The combined output of the demodulator, corresponding to a function of the data component independent of the carrier component frequency, is the output of the BBPE.

    Fig. 1 illustrates a homodyne type demodulator constructed in accordance with the present invention;

    Fig. 2 illustrates a heterodyne type demodulator constructed in accordance with the present invention;

    Fig. 3 illustrates a two-phase heterodyne type demodulator constructed in accordance with the present invention;

    Fig. 4 illustrates a three-phase all-optical homodyne type demodulator constructed in accordance with the present invention;

    Fig. 5 illustrates a two-phase base-band phase-equalizer (BBPE) particularly useful in the method and apparatus of the present invention;

    Fig. 6 illustrates a three-phase BBPE also particularly useful in the method and apparatus of the present invention; and

    Figs. 7 and 8 illustrate another three-phase BBPE and two-phase BBPE, respectively, which may be used in the method and apparatus of the present invention.



    [0011] Fig. 1 illustrates a homodyne type demodulator constructed in accordance with the present invention. The modulated signal to be demodulated is a DPSK (differential phase-shifted keying) signal, in which the data component changes the phase of the carrier component (fc) only when the data component is a data symbol representing a logical "1".

    [0012] As shown in Fig. 1, the signal 10 to be demodulated, of amplitude A, is fed to a splitter 12 which outputs two parts on its two output lines 12a, 12b. The part outputted via line 12b is delayed in a delay circuit 14 by one symbol duration. It is then inputted, with the undelayed part on output line 12a, to a multiport coupler 16, which may be a 2-port 90°-hybrid coupler or a 3-port symmetrical coupler the latter circuit also including the appropriate detectors and filters. The filtered output signals x₁, x₂, x₃ are linearly combined in a base-band phase-equalizer (BBPE) 18 described below, to yield the desired DPSK output proportional to

    , where ΔΦ denotes the phase difference

    ; and ∝ denotes the phase 2πfcτ, modulo 2π; and k is a proportionality constant.

    [0013] It will be seen that if the multiphase coupler 16 is a 2-port 90°-hybrid, the output signals will be as follows:











    where L is a proportionality constant depending on the components.

    [0014] On the other hand, if coupler 16 is a 3-port symmetrical coupler, its output signals will be:











    In either case, the combined output of the BBPE 18 will be insensitive to frequency or phase variations in the carrier because any frequency or phase changes will alter the multiphase outputs of coupler 16 such that their linearly combined outputs will remain constant, and therefore independent of frequency or phase.

    [0015] Fig. 2 illustrates a heterodyne type demodulator constructed in accordance with the present invention.

    [0016] In the heterodyne type demodulator illustrated in Fig. 2, the original signal 20 to be demodulated, and of an amplitude of "A", is inputted with a signal 21 from a local oscillator, and of an amplitude "B", into the multiport coupler circuit 22 which, as described above with respect to Fig. 1, may be a 2-port 90°-hybrid or a 3-port symmetrical coupler. Coupler 22 produces three outputs v₁, v₂, v₃ on its output lines 22a, 22b and 22c, respectively, at an intermediate frequency ωIBA. Only one of the outputs, namely v₁ on output line 22a, is delayed by a delay circuit 24, and is used to multiply each of the undelayed outputs, as shown by multipliers 25a-25c, respectively. The outputs are then filtered, by filters 26a-26c, respectively, to produce the output signals x₁-x₃, respectively. These output signals are linearly combined in the BBPE circuit 28 to produce the desired DPSK combined output corresponding to a function of the data component independent of the carrier component frequency.

    [0017] Where the multiphase coupler 22 is a 2-port 90°-hybrid, it will be seen that the coupler output signals v₁ to v₃ will be:











    where L₁ is a proportionality constant, and the signals x₁-x₃ combined in the BBPE 28 will be:











    where L₂ is another proportionality constant. On the other hand, if the multiport coupler 22 is a 3-port symmetrical coupler, then the signals v₁-v₃ on its outputs lines 22a-22c will be:











    where L₃ is another proportionality constant, and the signals x₁,x₂,x₃ combined in the BBPE 28 will be:











    where L₄ is still another proportionality constant.

    [0018] In either case, as described above with respect to Fig. 1, variations in the frequency or phase of the carrier will not affect the combined output because such variations will alter the inputs to the BBPE 28 a manner such that their proper linear combination will be insensitive to carrier frequency.

    [0019] Fig. 3 illustrates a two-phase heterodyne embodiment particularly suitable for radio frequency applications.

    [0020] In Fig. 3 the signal 30,

    , is combined with the local oscillator output 31,

    , in a complex mixer 32 composed of a 90°-hybrid and appropriate detectors. The two quadrature outputs








    on output lines 32a, 32b are filtered at Intermediate Frequency ωIBA by filters 33a, 33b. The cosine term is delayed at 34, split, and multiplied at 35a, 35b into both undelayed quadrature signals yielding, after lowpass filtering, the two quadrature lowpass terms








    which are input to the two-phase BBPE 36.

    [0021] The operation of BBPE 36 is described in Fig. 5. It effectively multiplies iC and iS by either cos α and sin α, respectively, and sums them, yielding the desired output proportional to

    , or by

    and

    yielding

    , which is the inverse of the desired output. This ambiguity, in the sign of the entire sequence of the desired output data symbols, is readily resolved by differential encoding, which is a routine procedure in DPSK art. Here k₁ and k₃ in Fig. 3 are proportionality constants that depend on the parameters of the hardware components used in the receiver design but are independent of A and B.

    [0022] Fig. 4 illustrates a three-phase homodyne type demodulator appropriate for lightwave applications.

    [0023] In the demodulator illustrated in Fig. 4, the initial signal 40 is first fed to a splitter 42 which outputs the split signals on its output lines 42a, 42b.

    [0024] The split signal on output line 42a is passed through a length of fibre 44 to impose a delay τ, and appears on output line 44a of the delay. The split signal A

    on output line 42b is fed to a three-phase coupler 45 with its delayed version on output line 44a A

    , where

    modulo 2π. The lights from the three coupled outputs fall on the photosensitive detectors 46a-46c which yield currents, having the following signal components iR, iS and iT:











    where k is a proportionality factor that depends on the coupler losses and diode efficiencies but is independent of A and B.

    [0025] The outputs from the detectors 46a-46c are combined in a three-phase BBPE 48, e.g., as illustrated in Figs. 6 and 7. Briefly, the BBPE 48 effectively multiplies iR, iS and iT by

    and

    , respectively and adds the products, yielding the desired result proportional to

    ; or, by

    ,

    and

    , yielding a result proportional to

    , which is its inverse. The sign ambiguity is resolvable as indicated above in connection with Fig. 3.

    [0026] Fig. 5 illustrates a two-phase BBPE such as may be used in any of the above-described demodulators.

    [0027] The two-phase BBPE of Fig. 5 has two parts: (i) a large bandwith part 50A designed such that it can operate up to gigabits/sec rate, making it suitable for fiber-optic communications by employing microwave mixers and modulators; and (ii) a low rate part 50B which has only to track the slowly varying angle α. This can be implemented by digital means, by which the non-linear sinus and cosinus functions are easily achievable.

    [0028] The large bandwith part 50A comprises four large bandwidth modulators 51a-51d driven by slowly varying base-band cosinus and sinus signals at the BB ports, with the high rate signals x₁ (or ic) and x₂ (or is) being input at the modulators' L.O. ports. The adders (Σ) 52a, 52b are broadband amplifiers.

    [0029] The feedback stage produces the product

    in a broadband mixer 53 where k is a proportionality constant. This product, designated y(t), is a slow waveform, since

    , nominally for all "t"s. It is filtered at 54, sampled and converted to digital form by converter 55, and then filtered by a standard phase-lock-loop (PLL) filter H(s) 56, to produce the quantity x. This quantity x is input to the ROM table 57 that supplies the cos x and sin x factors to the high-rate modulators via D/A converter 58. Standard Phase Lock Loop techniques can be used to initiate and ensure proper tracking of the BBPE circuitry. The loop operation ensures conveyance of 2(α-x) to zero, or to 2π, such that cos(α-x) is +1, or -1, respectively. Thus, the output of the BBPE varies with "ΔΦ" or its inverse as indicated in Fig. 5.

    [0030] A three-phase BBPE has two possible embodiments. The preferred one is illustrated in Fig. 6, and an alternative is illustrated in Fig. 7. In Fig. 6 the three input currents 61, 62, 63 are combined by linear adder amplifiers 64, 65, into two outputs x₁, x₂, which are processed by the two-phase BBPE 66 described in Fig. 5. In Fig. 7 an augmented version of the two-phase BBPE described in Fig. 5 directly operates on the three inputs. Its operation is similar to that of the two-phase version described in Fig. 5, and corresponding elements carry the same reference numerals but in the "70" series.

    [0031] Rather than equalizing the phase α=ωcτ by first calculating the sine and cosine functions of the quantity x in the BBPE of Fig. 5 and then performing the complex manipulations by 51a-51d to generate the term sin 2(α-x), in which the argument (α-x) converges to zero, the phase equalization may be achieved by varying the delay τ itself using a voltage dependent (or current dependent) delay component that may replace 14 in Fig. 1, or 24 in Fig 2, or 34 in Fig. 3, or 44 in Fig. 4, with the voltage dependent delay component being controlled by the quantity x which is generated by a baseband delay equalizer (BBDE). Such an embodiment is described in Fig. 8, in the context of a 2-phase homodyne type apparatus, which resembles, in all its other aspects, Fig. 1, and is therefore correspondingly numbered. However, in the configuration of Fig. 8, the feedback loop will drive the quantity α=2πfcτ, modulo 2π, to zero due to the operation of the BBDE block 87. Block 84 indicates the voltage-dependent (or current-dependent) delay component controlled by the quantity "x" for achieving the required equalization by varying the delay τ.
    Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included just for the sole purpose of increasing intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.


    Claims

    1. A method of demodulating a modulated signal having a carrier component and a data component, in which the modulated signal is split into at least two parts one of which is delayed with respect to the other, and the two parts are multiply-coupled and linearly-combined to produce a combined output corresponding to a function of the data component independent of the carrier component frequency; characterized in that: the undelayed part is coupled with the delayed part in a multiport coupler, wherein the parts are relatively phase-shifted to produce a plurality of phase-shifted signals; and the phase-shifted signals are linearly combined such that the data component, in the function of said combined output, is not affected by variations in frequency or phase of the carrier component.
     
    2. The method according to Claim 1, wherein said parts are coupled in a 2-port 90°-hybrid to produce two relatively 90°-shifted signals, which signals are linearly combined to produce said combined output.
     
    3. The method according to Claim 1, wherein said parts are coupled in a symmetrical 3-port coupler to produce an unshifted signal, a 120°-shifted signal and a 240°-shifted signal, which signals are linearly combined to produce said combined output.
     
    4. The method according to Claim 1, wherein said modulated signal is fed with a local oscillator signal to a 2-port 90°-hybrid coupler producing two relatively 90°-shifted intermediate signals; one of said intermediate signals being delayed and then mixed with said intermediate signals to produce two relatively 90°-shifted output signals, said combined output being produced from said said relatively 90°-shifted combined output signals.
     
    5. The method according to Claim 1, wherein said modulated signal is fed with a local oscillator signal to a 3-port symmetrical coupler producing an unshifted intermediate signal, a 120°-shifted intermediate signal, and a 240°-shifted intermediate signal; said unshifted intermediate signal being delayed and then mixed with each of said other intermediate signals to produce three output signals, relatively ±120° phase shifted; said combined output being produced by linearly combining said output signals.
     
    6. The method according to any one of Claims 1-5, wherein said source signal is a differential phase-shift keying signal wherein the data component changes the phase of the carrier component only when the data component is a data symbol representing a logical "1".
     
    7. The method according to Claim 6, wherein said output signals are linearly combined in a base-band phase-equalizer to produce said combined output.
     
    8. The method according to Claim 7, wherein said base band phase equalizer linearly combines said signals by a feedback circuit which, upon receiving a 2- or 3-vector:

    or

    , respectively, estimates a quantity x close to α; generates a 2- or 3-vector (cos x, sin x) or (cos x, cos (x+120°), cos (x+240°)), respectively, and then performs their inner product, generating terms proportional to

    and to

    , the first term being proportional to the desired quantity, Ao, while the second term is close to the error term

    used in the feedback configuration to generate the quantity x.
     
    9. The method according to Claim 6, wherein a baseband delay equalizer operating on said output signals, generates the quantity x which varies the delay in a feedback loop driving the quantity α=2πfc , modulo 2π, to zero, and thereby driving one of the said output signals to the desired output value corresponding to a function of the data component independent of the carrier component frequency.
     




    Drawing