(19)
(11)EP 0 237 322 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
05.07.1989 Bulletin 1989/27

(43)Date of publication A2:
16.09.1987 Bulletin 1987/38

(21)Application number: 87302040.8

(22)Date of filing:  10.03.1987
(51)International Patent Classification (IPC)4H03K 19/20, H03K 3/03, H03K 3/288, H03K 3/037
(84)Designated Contracting States:
DE FR GB

(30)Priority: 11.03.1986 JP 51369/86

(60)Divisional application:
92114729.4 / 0523747

(71)Applicant: FUJITSU LIMITED
Kawasaki-shi, Kanagawa 211 (JP)

(72)Inventors:
  • Tsunoi, Hiroyuki
    Yokohama-shi Kanagawa 223 (JP)
  • Kanai, Yasunori
    Kuwana-shi Mie 511 (JP)
  • Sugiyama, Eiji
    Kawasaki-shi Kanagawa 213 (JP)
  • Seto, Motohiro
    Kawasaki-shi Kanagawa 211 (JP)
  • Ando, Naoyuki
    Yokohama-shi Kanagawa 232 (JP)

(74)Representative: Billington, Lawrence Emlyn et al
HASELTINE LAKE & CO Hazlitt House 28 Southampton Buildings Chancery Lane
London WC2A 1AT
London WC2A 1AT (GB)


(56)References cited: : 
  
      


    (54)Latch circuit


    (57) A latch circuit having two complementary hold loops for improved noise tolerance.
    The latch circuit includes a first gate (G11, G16) receiving data (D) and a first clock signal (CL), for outputting at least one signal gating the data and the first clock signal in response to a change in the clock signal; a second gate (G12, G15) receiving a second clock signal having an inverted polarity to that of the first clock signal; and a third gate (G13, G14); and operatively connected to output terminals of the first and second gates, for outputting at least one latch output (SQ). The latch circuit also includes a first hold line (HL1) supplying the latch output to the second gate and a second hold line (HL2) supplying another latch output of the latch circuit having an inverted polarity to that of the latch output to the second gate. The second gate may have an inverted input terminal receiving the other latch output.
    The second gate may include a differential operation gate circuit operating in response to a signal on the first hold line and a signal on the second hold line.
    The latch circuit may be an "in-phase" hold type latch circuit or an "inverted-phase" hold type latch circuit.







    Search report