(19)
(11)EP 1 495 569 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
28.11.2007 Bulletin 2007/48

(21)Application number: 03717442.2

(22)Date of filing:  08.04.2003
(51)International Patent Classification (IPC): 
H04L 1/00(2006.01)
(86)International application number:
PCT/GB2003/001577
(87)International publication number:
WO 2003/088550 (23.10.2003 Gazette  2003/43)

(54)

CHANNEL MAPPING IN A WIRELESS COMMUNICATION SYSTEM

KANALZUORDNUNG IN EINEM DRAHTLOSEN KOMMUNIKATIONSSYSTEM

MISE EN CORRESPONDANCE DE CANAUX DANS UN RESEAU DE COMMUNICATION SANS FIL


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IT LI LU MC NL PT RO SE SI SK TR

(30)Priority: 08.04.2002 GB 0208039

(43)Date of publication of application:
12.01.2005 Bulletin 2005/02

(73)Proprietor: IPWireless, Inc.
San Bruno, CA 94066 (US)

(72)Inventor:
  • BEALE, Martin
    Bristol BS2 8HE (GB)

(74)Representative: Jepsen, René Pihl 
Eltima Consulting Grove House, Lutyens Close' Chineham Court
Basingstoke, Hants RG24 8AG
Basingstoke, Hants RG24 8AG (GB)


(56)References cited: : 
WO-A-01/41314
US-A1- 2002 003 846
WO-A-99/45660
US-B1- 6 304 581
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Field of the Invention



    [0001] This invention relates to wireless communication systems and particularly to Packet-Based TDD-CDMA (Time Division Duplex - Code Division Multiple Access) systems such as UMTS (Universal Mobile Telecommunication System) systems complying with the evolving 3GPP (3rd Generation Partnership Project) standard.

    Background of the Invention



    [0002] In the field of this invention it is known that for TDD HSDPA (High Speed Downlink Packet Access) a HS-DSCH (High Speed - Downlink Shared CHannel) transport channel can use QPSK (Quadrature Phase Shift Key) or 16QAM (16-level Quadrature Amplitude Modulation) modulation. In the case of 16QAM modulation, 4 bits are mapped to a 16 level signal (composed of 4 in-phase levels and 4 quadrature levels). Two of the mapped bits have a higher reliability than the other two mapped bits (the bits to be modulated can thus be classified as being "high reliability bits" or "low reliability bits").

    [0003] HS-DSCH channel coding is known to use turbo codes. It is well known that performance of a turbo code can be improved if the systematic bits produced by the turbo coder are received with a greater reliability than the parity bits. It is thus natural to attempt to map the systematic bits from the output of the turbo coder to the "high reliability bits" within the 16QAM constellation and the parity bits to the "low reliability bits" within the 16QAM constellation. This scheme is known as "bit priority mapping".

    [0004] Bit priority mapping is known to be implemented for FDD (Frequency Division Duplex) HSDPA using a "HARQ (Hybrid Automatic-Repeat-Request) bit collection interleaver" followed by an "HS-DSCH interleaver". The "HARQ bit collection interleaver" arranges the bits at the output of the physical layer hybrid ARQ (Automatic-Repeat-Request) functionality to achieve a preferential order of systematic bits at its output: the "HARQ bit collection interleaver" attempts to ensure that odd indexed bits are preferably systematic bits and even indexed bits are preferably parity bits.

    [0005] The HS-DSCH interleaving stage interleaves the odd indexed and even indexed bits separately (in this way, the set of bits that are preferably systematic are kept separate from the set of bits that are preferably parity bits). In FDD HSDPA, the bits from the preferably systematic interleaver are mapped (in the physical channel mapping stage) to high reliability bits and the bits from the preferably parity interleaver are mapped to low reliability bits in the 16QAM symbol.

    [0006] In TDD, the physical channel mapping stage generally includes a function whereby odd indexed physical channels are filled with bits in a forward direction and even indexed physical channels are filled in the reverse direction. By tilling odd indexed channels in the forward direction and even indexed channels in the reverse direction, an extra degree of interleaving is achieved. In general, the forwards/reverse mapping can be considered as a physical channel mapper interleaving function.

    [0007] The TDD physical channel mapping scheme described above is suboptimal for HSDPA since it destroys the link between systematic bits and high reliability positions.

    [0008] An alternative approach tor physical channel mapping in TDD is to perform the identical operation to FDD: physical channels are all mapped in the forward direction consecutively (physical channel 1 is mapped in the forward direction; once this mapping is complete, left over bits are then mapped to physical channel 2 in the forward direction, etc.). This alternative approach will retain the benefit of mapping preferably systematic bits to high reliability bits and preferably parity bits to low reliability positions. However, this alternative approach does not give the interleaving benefit that is obtained from filling odd indexed physical channels in the forward direction and even indexed physical channels in the reverse direction.
    WO 01/41314 discloses a wireless communication system that includes forward and reverse mapping of bits after an interleaving stage.

    [0009] A need therefore exists for channel mapping wherein the abovementioned disadvantage(s) may be alleviated.

    Statement of Invention



    [0010] In accordance with a first aspect of the present invention there is provided an arrangement for channel mapping as claimed in claim 1.

    [0011] In accordance with a second aspect of the present invention there is provided an arrangement for channel demapping as claimed in claim 7.

    [0012] In accordance with a third aspect of the present invention there is provided a method for channel mapping as claimed in claim 13.

    [0013] In accordance with a fourth aspect of the present invention there is provided a method for channel demapping as claimed in claim 19.

    [0014] Briefly stated, in a preferred form the invention provides a new and inventive physical channel mapping/demapping scheme for TDD HSDPA which allows systematic bits to be mapped to high reliability positions in a 16QAM (or higher order) modulation while retaining an interleaving benefit by application of a forwards mapping rule for odd indexed physical channels and a backwards mapping rule for even indexed physical channels. The forwards/reverse mapping may be generally considered a physical channel mapper based interleaving function.

    [0015] The new scheme allows symbols, as opposed to bits, to be mapped into physical channels. Symbols may be assigned consecutively to odd indexed physical channels and even indexed physical channels. Physical channels may be mapped alternately in a forwards and a reverse direction.

    [0016] It is not strictly necessary to apply the mapping scheme at the symbol level. It is possible to perform the mapping such that systematic-parity bit pairs (a pair consisting of one systematic bit and one parity bit) are assigned consecutively to odd indexed physical channels and even indexed physical channels. Physical channels may be mapped alternately in a forwards and a reverse direction.

    [0017] The new mapping scheme may be applied at a transmitter and an inverse process applied at the receiver.

    [0018] In this text, unless the context otherwise requires, the term symbol is intended to cover any representation of a plurality of bits.

    Brief Description of the Drawings



    [0019] Three symbol mapping schemes incorporating the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which:

    FIG. 1 illustrates a block diagrammatic representation of a UTRA system in which the present invention is used;

    FIG. 2 illustrates a transport channel processing chain for TDD HSDPA in the system of FIG. 1;

    FIG. 3 illustrates a prior art TDD physical channel mapping of 1104 bits to 2 channels modulated with 16QAM;

    FIG. 4 illustrates an alternative prior art physical channel mapping scheme to that shown in FIG. 3;

    FIG. 5 illustrates portions of the transport channel processing chain relevant to a first embodiment of the present invention;

    FIG. 6 illustrates symbol based physical channel mapping according to the embodiment illustrated in FIG. 5;

    FIG. 7 illustrates portions of the transport channel processing chain relevant to a second embodiment of the present invention;

    FIG. 8 illustrates symbol based physical channel mapping according to the embodiment illustrated in FIG. 7;

    FIG. 9 illustrates Portions of transport channel processing chain relevant to a third embodiment of the present invention; and

    FIG. 10 illustrates symbol based physical channel mapping according to the embodiment illustrated in FIG. 9.


    Description of Preferred Embodiments



    [0020] Referring firstly to FIG. 1, a typical, standard UMTS network (100) is conveniently considered as comprising: a user equipment domain (110), made up of a user SIM (USIM) domain (120) and a mobile equipment domain (130); and an infrastructure domain (140), made up of an access network domain (150), and a core network domain (160), which is in turn made up of a serving network domain (170) and a transit network domain (180) and a home network domain (190).

    [0021] In the mobile equipment domain (130), user equipment UE (130A) receives data from a user SIM (120A) in the USIM domain 120 via the wired Cu interface. The UE (130A) communicates data with a Node B (150A) in the network access domain (150) via the wireless Uu interface. Within the network access domain (150), the Node B (150A) communicates with a radio network controller or RNC (150B) via the Iub interface. The RNC (150B) commmunicates with other RNC's (not shown) via the Iur interface. The RNC (150B) communicates with a SGSN (170A) in the serving network domain (170) via the Iu interface. Within the serving network domain (170), the SGSN (170A) communicates with a GGSN (170B) via the Gn interface, and the SGSN (170A) communicates with a VLR server (170C) via the Gs interface. The SGSN (170A) communicates with an HLR server (190A) in the home network domain (190) via the Zu interface. The GGSN (170B) communicates with public data network (180A) in the transit network domain (180) via the Yu interface.

    [0022] Thus, the elements RNC (150B), SGSN (170A) and GGSN (170B) are conventionally provided as discrete and separate units (on their own respective software/hardware platforms) divided across the access network domain (150) and the serving network domain (170), as shown the FIG. 1.

    [0023] The RNC (150B) is the UTRAN element responsible for the control and allocation of resources for numerous Node B's (150A); typically 50 to 100 Node B's may be controlled by one RNC. The RNC also provides reliable delivery of user traffic over the air interfaces. RNC's communicate with each other (via the interface Iur) to support handover and macrodiversity.

    [0024] The SGSN (170A) is the UMTS Core Network element responsible for Session Control and interface to the Location Registers (HLR and VLR). The SGSN is a large centralised controller for many RNCs.

    [0025] The GGSN (170B) is the UMTS Core Network element responsible for concentrating and tunnelling user data within the core packet network to the ultimate destination (e.g., internet service provider - ISP).

    [0026] The wireless Uu interface utilises a transport channel TrCH to transport information between UE's (130A) and Node B's (150A). The transport channel processing chain for TDD HSDPA is shown in FIG. 2. As shown, CRC (Cyclic Redundancy Check) attachment (210) is followed by code block segmentation (220), Channel Coding (230), Physical Layer Hybrid ARQ function (240), Bit Scrambling (250), Physical Channel Segmentation (260), HS-DSCH Interleaving (270), Physical Channel Mapping (280) and finally Bit Rearrangement for 16QAM (290) to produce codes for two physical channels PhCH#1 and PhCH#2. It will be understood that such a transport channel processing chain is in general well known and need not be described in further detail.

    [0027] The HS-DSCH transport channel can use QPSK or 16QAM modulation. In the case of 16QAM modulation as shown, 4 bits are mapped to a 16 level signal (composed of 4 in-phase levels and 4 quadrature levels). Two of the mapped bits have a higher reliability than the other two mapped bits (the bits to be modulated can thus be classified as being "high reliability bits" or "low reliability bits").

    [0028] The HS-DSCH channel coding uses turbo codes, as well understood. It is well known that performance of a turbo code can be improved if the systematic bits produced by the turbo coder are received with a greater reliability than the parity bits. It is thus natural to attempt to map the systematic bits from the output of the turbo coder to the "high reliability bits" within the 16QAM constellation and the parity bits to the "low reliability bits" within the 16QAM constellation. This scheme is known as "bit priority mapping".

    [0029] Bit priority mapping is implemented for FDD HSDPA using a "HARQ bit collection interleaver" followed by an "HS-DSCH interleaver". The "HARQ bit collection interleaver" arranges the bits at the output of the physical layer hybrid ARQ function (240) of FIG. 2 to achieve a preferential order of systematic bits at its output: the "HARQ bit collection interleaver" attempts to ensure that odd indexed bits are preferably systematic bits and even indexed bits are preferably parity bits.

    [0030] The HS-DSCH interleaving stage (270) of FIG. 2 interleaves the odd indexed and even indexed bits separately (in this way, the set of bits that are preferably systematic are kept separate from the set of bits that are preferably parity bits). In FDD HSDPA, the bits from the (preferably systematic) interleaver are mapped (in the physical channel mapping stage) to high reliability bits and the bits from the (preferably parity) interleaver are mapped to low reliability bits in the 16QAM symbol.

    [0031] In TDD, the physical channel mapping stage (280) generally includes a function whereby odd indexed physical channels are filled with bits in a forward direction and even indexed physical channels are filled in the reverse direction. This process is illustrated in FIG. 3 for the case where the bitstream v1,v2,v3,....v1103,v1104 is mapped to two physical channels supporting 16QAM. By filling odd indexed channels in the forward direction and even indexed channels in the reverse direction, an extra degree of interleaving is achieved. In general, the forwards/reverse mapping can be considered as a physical channel mapper interleaving function.

    [0032] However, the TDD physical channel mapping scheme described above is suboptimal for HSDPA since it destroys the link between systematic bits and high reliability positions. Considering the case illustrated in FIG. 3, the "HARQ bit collection interleaver" preferably assigns systematic bits to odd indexed positions (v2k-1, shown generally at 310) and parity bits to even indexed positions (v2k, shown generally at 320) : in this case, the preferably systematic bits are mapped to the first physical channel and the preferably parity bits are mapped to the second physical channel; this will lead to a suboptimal performance.

    [0033] As illustrated in FIG. 4, an alternative known approach for physical channel mapping in TDD is to perform the identical operation as for FDD, in which physical channels are all mapped in the forward direction consecutively: physical channel 1 is mapped in the forward direction (at indexed positions v1...v552, shown generally at 410), and once this mapping is complete, left over bits are then mapped to physical channel 2 (at indexed positions v553...v1104, shown generally at 420) in the forward direction, etc. In the alternative shown in FIG. 4, it is assumed that odd indexed bits in the physical channel are mapped to high reliability bit positions in the modulated symbol by the modulator. This alternative approach will retain the benefit of mapping preferably systematic bits to high reliability bits and preferably parity bits to low reliability positions. However, this alternative approach does not give the interleaving benefit that is obtained from filling odd indexed physical channels in the forward direction and even indexed physical channels in the reverse direction as described above in relation to FIG. 3.

    [0034] In order to alleviate the disadvantages of the alternative physical channel mapping schemes for TDD HSDPA described above in relation to FIG. 3 and FIG. 4, the present invention provides a new and inventive physical channel mapping scheme for TDD HSDPA. As will be described in greater detail below, this new scheme allows systematic bits to be mapped to high reliability positions in a 16QAM (or higher order) modulation while retaining an interleaving benefit by application of a forwards mapping rule for odd indexed physical channels and a backwards mapping rule for even indexed physical channels. The forwards/reverse mapping may be generally considered a physical channel mapper based interleaving function.

    [0035] The new scheme allows symbols, as opposed to bits, to be mapped into physical channels. Symbols may be assigned consecutively to odd indexed physical channels and even indexed physical channels. Physical channels may be mapped alternately in a forwards and a reverse direction. The forwards/reverse mapping may be generally considered a physical channel mapper based interleaving function.

    [0036] It is not strictly necessary to apply the mapping scheme at the symbol level. It is possible to perform the mapping such that systematic-parity bit pairs (a pair consisting of one systematic bit and one parity bit) are assigned consecutively to odd indexed physical channels and even indexed physical channels. Physical channels may be mapped alternately in a forwards and a reverse direction. The forwards/reverse mapping may be generally considered a physical channel mapper based interleaving function.

    [0037] The new mapping scheme may be applied at a transmitter (e.g., UE or Node B) and an inverse process applied at a receiver (e.g., Node B or UE).

    Embodiment 1



    [0038] The relevant sections of the TDD HSDPA transport channel processing chain in order to achieve embodiment 1 are illustrated in FIG. 5.

    [0039] As will be described in greater detail below, a HARQ bit collection block (510) collects bits from earlier HARQ rate matching function (not shown) and supplies bits to a HS-DSCH interleaver (520), which comprises a systematic interleaver (530) and a parity interleaver (540). It will be understood by those skilled in the art that the bits labelled "sys" are preferably systematic bits and the bits labelled "par" are preferably parity bits. In general, the HARQ rate matching function will not produce equal numbers of systematic and parity bits, for this reason the "sys" stream contains preferably systematic bits, but if there are insufficient systematic bits, this stream may also contain parity bits. It will further be understood that the blocks 510-540 are well-known per se and need not be described in further detail.

    [0040] As shown in FIG. 5, the TDD HSPDA transport channel processing chain includes a symbol grouping block (550) and a symbol based physical channel mapping block (560). It will be understood that these two blocks can, in a practical implementation, if desired, be merged into a single block.

    [0041] In embodiment 1 of the invention, the symbol grouping function (550) takes a group of bits from the "sys" stream and a group of bits from the "par" stream (in the case of 16QAM modulation, there will be 2 bits from the "sys" stream and 2 bits from the "par" stream). The symbol grouping function (550) maps the two groups of bits to a symbol such that the high reliability bits of the symbol created are taken from the "sys" group and the low reliability bits of the symbol created are taken from the "par" group.

    [0042] In embodiment 1 of the invention, the grouped symbols, marked "symbols" at the output of the symbol grouping function (550) in FIG. 5, are sent to the symbol based physical channel mapper (560). The symbol based physical channel mapper (560) maps symbols to physical channels such that:
    • symbols are mapped to physical channels in increasing order,
    • odd indexed physical channels are mapped with symbols in the forwards direction, and
    • even indexed physical channels are mapped in the reverse direction.


    [0043] The symbols produced by the symbol grouping function (560) are supplied to a modulator (not shown) for modulation for transmission on the transport channel in known manner, such that reliability based ordering applied in the physical channel mapper is maintained by the modulator. If the symbols produced by the symbol grouping function (560) are denoted s1,s2,s3,s4...sn-1,sn and these symbols are mapped to two physical channels (for the sake of illustration), then these symbols are mapped to physical channels #1 (610) and #2 (620) as shown in FIG. 6.

    [0044] Those skilled in the art will readily understand that the inverse process to that described above is applied at the receiver, UE (130A) or Node B (150A), for this embodiment, in such a manner that bit reliability in the modulator is maintained in the physical channel demapper.

    Embodiment 2



    [0045] Referring now to FIG. 7, in a second embodiment of the invention (similarly to embodiment 1 described above in relation to FIG. 5), a HARQ bit collection block (710) collects bits from earlier HARQ rate matching function (not shown) and supplies bits to a HS-DSCH interleaver (720), which comprises a systematic interleaver (730) and a parity interleaver (740).

    [0046] As shown in FIG. 7, the TDD HSPDA transport channel processing chain in embodiment 2 includes a symbol based physical channel mapping block (760) that supplies symbols to a modulator (not shown) for modulation for transmission on the transport channel in known manner, but in comparison with the FIG. 5 it can be seen that there is no symbol grouping function such as the symbol grouping block (550); instead embodiment 2 the order in which bits are mapped to physical channels is redefined in relation to the physical channel mapping for FDD HSDPA. For the sake of clarity, the following explanation of embodiment 2 focuses on the physical channel mapping operation for the case of 16QAM modulation. Those skilled in the art will be able to generalise this explanation to modulations other than 16QAM.

    [0047] In embodiment 2, as in embodiment 1 described above, the bits labelled "sys" are preferably systematic bits and the bits labelled "par" are preferably parity bits.

    [0048] In embodiment 2 of the invention, there is no explicit "symbol grouping" function. The "symbol based physical channel mapper" (760) in embodiment 2 of the invention maps bits to physical channels with full knowledge of the order that the bits will be read out of the mapped physical channels by the modulator (not shown). In this embodiment of the invention, groups of bits are mapped to physical channels on a group-by-group basis. In this embodiment of the invention, the group size is the number of bits that are carried by a modulated symbol (in the case of 16QAM, the group size is 4 bits).

    [0049] As an example, if the modulator breaks up a physical channel containing bits u1,u2,u3,u4...u549,u550,u551,u552 into symbols according to the rule that u1,u2, u5,u6 etc. (in general u4k+1,u4k+2 for the case of 16QAM) are mapped to high reliability bits in the modulated symbol (note the difference in definition used compared to that used for FIG. 3) and other bits are mapped to low reliability positions within the modulated symbol, then the "symbol based physical channel mapper" (760) of embodiment 2 maps an input bit sequence v1,v2,v3....v1103,v1104 (where bits v2k-1 are taken from the "sys" stream of FIG. 7 and bits v2k are taken from the "par" stream of FIG. 7) into mapped physical channel bits #1 (810) and #2 (820) as shown in FIG. 8.

    [0050] The mapping illustrated in FIG. 8 achieves the effect that the modulator will map bits from the "sys" stream to high reliability bit positions in the modulated symbol and bits from the "par" stream to low reliability positions in the modulated symbol. The mapping of FIG. 8 also achieves the interleaving effect of a "forwards/reverse" mapping of bits.

    Embodiment 3



    [0051] Referring now to FIG. 9, (similarly to embodiment 2 described above in relation to FIG. 7) a HARQ bit collection block (910) collects bits from earlier HARQ rate matching function (not shown) and supplies bits to a HS-DSCH interleaver (920), which comprises a systematic interleaver (930) and a parity interleaver (940).

    [0052] Similarly to embodiment 2, the TDD HSPDA transport channel processing chain in embodiment 3 includes a bit-pair based physical channel mapping block (960) that supplies bit-pairs to a modulator (not shown) for modulation for transmission on the transport channel in known manner, and unlike embodiment 1 described above in relation to FIG. 5 there is no symbol grouping function such as the symbol grouping block (550). In embodiment 3, as in embodiment 2, the order in which bits are mapped to physical channels is redefined in relation to the physical channel mapping for FDD HSDPA. For the sake of clarity, as above, the following explanation of embodiment 3 focuses on the physical channel mapping operation for the case of 16QAM modulation. Those skilled in the art will be able to generalise this explanation to modulations other than 16QAM.

    [0053] In embodiment 3, as in embodiments 1 and 2 described above, the bits labelled "sys" are preferably systematic bits and the bits labelled "par" are preferably parity bits.

    [0054] In the third embodiment of the invention, the group size is 2 bits (the group consists of a single systematic bit and a single parity bit). The group of bits in embodiment 3 consists of a single (preferably) systematic bit and a single (preferably) parity bit. In embodiment 3, bits are assigned to physical channels in systematic-parity bits pairs (a pair consisting of a single systematic bit and a single parity bit). In this section, for the sake of clarity, the explanation focuses on the physical channel mapping operation for the case of 16QAM modulation. Those skilled in the art will be able to generalise this explanation to modulations other than 16QAM.

    [0055] In embodiment 3 of the invention, bit pairs are mapped to physical channels rather than symbol-sized groups of bits. The "bit-pair based physical channel mapper" (960) in embodiment 3 of the invention maps bits to physical channels with full knowledge of the order that the bits will be read out of the mapped physical channels by the modulator.

    [0056] As an example, if the modulator breaks up a physical channel containing bits is u1,u2,u3,u4...u549,u550,u551,u552 into symbols according to the rule that u1,u2, u5,u6, etc. (in general u4k+1,u4k+2 for the case of 16QAM) are mapped to high reliability bits in the modulated symbol (note the difference in definition used compared to that used for FIG. 3) and other bits are mapped to low reliability positions within the modulated symbol, then the "bit-pair based physical channel mapper" of embodiment 3 maps an input bit sequence v1,v2,v3...v1103,v1104 (where bits v2k-1 are taken from the "sys" stream of FIG. 9 and bits v2k are taken from the "par" stream of FIG. 9) into mapped physical channel bits #1 (1010) and #2 (1020) as shown in FIG. 10.

    [0057] A salient point about the mapping illustrated in FIG. 10 is that bits from a bit-pair are mapped to the same physical channel (for instance, it may be noted that bits v1 and v2 which belong to the same bit-pair are both mapped to physical channel 1 whereas bits v3 and v4 which belong to the same bit-pair are both mapped to physical channel 2). This contrasts with embodiment 2 where v1,v2,v3 and v4 are all mapped to physical channel 1 because a 16QAM symbol consists of exactly 4 bits.

    [0058] The mapping illustrated in FIG. 10 achieves the effect that the modulator will map bits from the "sys" stream to high reliability bit positions in the modulated symbol and bits from the "par" stream to low reliability positions in the modulated symbol. The mapping of FIG. 10 also achieves the interleaving effect of a "forwards/reverse" mapping of bits.

    [0059] It will be appreciated that the method described above for modulation symbol/bit-pair mapping in a wireless communication system may be carried out in software running on a processor (not shown), and that the software may be provided as a computer program element carried on any suitable data carrier (also not shown) such as a magnetic or optical computer disc.

    [0060] It will be also be appreciated that the method described above for modulation symbol/bit-pair mapping in a wireless communication system may alternatively be carried out in hardware, for example in the form of an integrated circuit (not shown) such as an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

    [0061] It will be understood that the modulation symbol/bit-pair mapping scheme described above provides the following advantages that:
    • Systematic bits are preferably mapped to high reliability bit positions in TDD HSDPA. This achieves a performance gain of between 0.2dB and 0.5dB.
    • A forwards/reverse mapping is possible for successive physical channels. This achieves a degree of interleaving that improves system performance in fading channels or channels disturbed by short time period noise or interference.



    Claims

    1. An arrangement for channel mapping in a wireless communication system, the arrangement comprising:

    first interleaving means (730) for interleaving a bit sequence comprising systematic bits to produce an interleaved systematic bit sequence; and

    second interleaving means (740) for interleaving a bit sequence comprising parity bits to produce an interleaved parity bit sequence,

    logic (550) arranged to group bits from the interleaved parity bit sequence and bits from the interleaved systematic bit sequence to produce symbols; each symbol comprising parity bits and systematic bits, whereby bits from the interleaved systematic bit sequence are mapped to high reliability bits of the symbol and bits from the interleaved parity sequence are mapped to low reliability bits of the symbol; and

    mapping logic (760) arranged to map the symbols to an odd indexed physical channel and an even indexed physical channel, whereby the symbols are mapped in an increasing order in a forward direction or a reverse direction according to the channel index.


     
    2. The arrangement of claim 1 wherein the symbols are arranged to be modulated by 16QAM modulation.
     
    3. The arrangement of any preceding claim wherein the wireless communication system is a UTRA TDD system.
     
    4. The arrangement of claim 3 wherein the first and second channels are comprised in a transport channel.
     
    5. The arrangement of any preceding claim arranged to operate on a High Speed Downlink Shared Channel.
     
    6. The arrangement of claim 5 arranged to operate in High Speed Downlink Packet Access.
     
    7. An arrangement for channel demapping in a wireless communication system, the arrangement comprising:

    de-mapping logic arranged to de-map symbols in a forward or reverse direction according to a channel index where symbols have been mapped in an increasing order to an odd indexed physical channel or an even indexed physical channel;

    logic arranged to ungroup groups of bits from symbols to produce an interleaved parity bit sequence and an interleaved systematic bit sequence, each symbol comprising parity bits and systematic bits; and

    first deinterleaving means for deinterleaving the systematic bit sequence to produce a de-interleaved bit sequence comprising systematic bits; and

    second deinterleaving means for deinterleaving the parity bit sequence to produce a de-interleaved bit sequence comprising parity bits, whereby bits from the de-interleaved systematic bit sequence have been mapped to high reliability bits of the symbol and bits from the de-interleaved parity sequence have been mapped to low reliability bits of the symbol.


     
    8. The arrangement of claim 7 wherein the symbols are modulated by 16QAM modulation.
     
    9. The arrangement of any one of claims 7 to 8 wherein the wireless communication system is a UTRA TDD system.
     
    10. The arrangement of claim 9 wherein the first and second channels are comprised in a transport channel.
     
    11. The arrangement of any one of claims 7-10 arranged to operate on a High Speed Downlink Shared Channel.
     
    12. The arrangement of claim 11 arranged to operate in High Speed Downlink Packet Access.
     
    13. A method for channel mapping in a wireless communication system, the method comprising:

    interleaving (730) a bit sequence comprising systematic bits to produce an interleaved systematic bit sequence, and

    interleaving (740) a bit sequence comprising parity bits to produce an interleaved parity bit sequence,

    grouping (550) bits from the interleaved parity bit sequence and bits from the interleaved systematic bit sequence to produce symbols, each symbol comprising parity bits and systematic bits, whereby bits from the interleaved systematic bit sequence are mapped to high reliability bits of the symbol and bits from the interleaved parity sequence are mapped to low reliability bits of the symbol; and

    mapping (760) the symbols to an odd indexed physical channel and an even indexed physical channel in an increasing order in a forward direction or a reverse direction according to the channel index.


     
    14. The method of claim 13 wherein the symbols are modulated by 16QAM modulation.
     
    15. The method of any one of claims 13-14 wherein the wireless communication system is a UTRA TDD system.
     
    16. The method of claim 15 wherein the first and second channels are comprised in a transport channel.
     
    17. The method of any one of claims 13-16 operating on a High Speed Downlink Shared Channel.
     
    18. The method of claim 17 operating in High Speed Downlink Packet Access.
     
    19. A method for channel demapping in a wireless communication system, the method comprising:

    de-mapping symbols in a forward or reverse direction according to a channel index where symbols have been mapped in an increasing order to an odd indexed physical channel or an even indexed physical channel;

    ungrouping groups of bits from symbols to produce an interleaved parity bit sequence and an interleaved systematic bit sequence, each symbol comprising parity bits and systematic bits;

    deinterleaving the systematic bit sequence to produce a de-interleaved bit sequence comprising systematic bits; and

    deinterleaving the parity bit sequence to produce a de-interleaved bit sequence comprising parity bits, whereby bits from the de-interleaved systematic bit sequence have been mapped to high reliability bits of the symbol and bits from the de-interleaved parity sequence have been mapped to low reliability bits of the symbol.


     
    20. The method of claim 19 wherein the symbols are modulated by 16QAM modulation.
     
    21. The method of any one of claims 19-20 wherein the wireless communication system is a UTRA TDD system.
     
    22. The method of claim 21 wherein the first and second channels are comprised in a transport channel.
     
    23. The method of any one of claims 19-22 operating on a High Speed Downlink Shared Channel.
     
    24. The method of claim 23 operating in High Speed Downlink Packet Access.
     
    25. User equipment for use in a wireless communication system comprising an arrangement as claimed in any one of claims 1-12.
     
    26. A base station for use in a wireless communication system comprising an arrangement as claimed in any one of claims 1-12.
     
    27. An integrated circuit comprising the arrangement of any one of claims 1-12.
     
    28. A computer program element comprising computer program means for performing the method of any one of claims 13-24.
     


    Ansprüche

    1. Anordnung zur Kanalzuordnung in einem drahtlosen Kommunikationssystem, wobei die Anordnung umfasst:

    ein erstes Verschachtelungsmittel (730) zur Verschachtelung einer Bitsequenz, die systematische Bits umfasst, um eine verschachtelte systematische Bitsequenz zu erzeugen; und

    ein zweites Verschachtelungsmittel (740) zur Verschachtelung einer Bitsequenz, die Paritätsbits umfasst, um eine verschachtelte Paritätsbitsequenz zu erzeugen,

    eine Logik (550), die geeignet ist, um Bits von der verschachtelten Paritätsbitsequenz und Bits von der verschachtelten systematischen Bitsequenz zu gruppieren, um Symbole zu erzeugen, wobei jedes Symbol Paritätsbits und systematische Bits umfasst, wobei Bits von der verschachtelten systematischen Bitsequenz Bits des Symbols von hoher Verlässlichkeit zugeordnet werden und Bits von der verschachtelten Paritätssequenz Bits des Symbols von niedriger Verlässlichkeit zugeordnet werden; und

    eine Zuordnungslogik (760), die geeignet ist, um die Symbole einem ungerade indizierten physikalischen Kanal und einem gerade indizierten physikalischen Kanal zuzuordnen, wobei die Symbole in einer aufsteigenden Reihenfolge in einer Vorwärtsrichtung oder einer Rückwärtsrichtung, entsprechend dem Kanalindex, zugeordnet werden.


     
    2. Anordnung gemäß Anspruch 1, wobei die Symbole geeignet sind, um durch eine 16QAM-Modulation moduliert zu werden.
     
    3. Anordnung gemäß einem der vorangehenden Ansprüche, wobei das drahtlose Kommunikationssystem ein UTRA TDD-System ist.
     
    4. Anordnung gemäß Anspruch 3, wobei der erste und zweite Kanal in einem Transportkanal enthalten sind.
     
    5. Anordnung gemäß einem der vorangehenden Ansprüche, die geeignet ist, um in einem gemeinsam verwendeten Hochgeschwindigkeitsabwärtskanal ("High Speed Downlink Shared Channel") zu arbeiten.
     
    6. Anordnung gemäß Anspruch 5, die geeignet ist, um in einem Hochgeschwindigkeitsabwärtspaketzugriff ("High Speed Downlink Packet Access") zu arbeiten.
     
    7. Anordnung zur Auflösung einer Kanalzuordnung in einem drahtlosen Kommunikationssystem, wobei die Anordnung umfasst:

    eine Logik zur Auflösung einer Zuordnung, die geeignet ist, um Symbolzuordnungen in einer Vorwärts- oder Rückwärtsrichtung entsprechend einem Kanalindex aufzulösen, wobei Symbole in einer aufsteigenden Reihenfolge einem ungerade indizierten physikalischen Kanal oder einem gerade indizierten physikalischen Kanal zugeordnet worden sind;

    eine Logik, die geeignet ist, eine Gruppierung von Gruppen von Bits von Symbolen aufzulösen, um eine verschachtelte Paritätsbitsequenz und eine verschachtelte systematische Bitsequenz zu erzeugen, wobei jedes Symbol Paritätsbits und systematische Bits umfasst; und

    ein erstes Verschachtelungsauflösungsmittel zur Auflösung der Verschachtelung der systematischen Bitsequenz, um eine Bitsequenz mit aufgelöster Verschachtelung zu erzeugen, die systematische Bits umfasst; und

    ein zweites Verschachtelungsauflösungsmittel zur Auflösung der Verschachtelung der Paritätsbitsequenz, um eine Bitsequenz mit aufgelöster Verschachtelung zu erzeugen, die Paritätsbits umfasst, wodurch Bits von der systematischen Bitsequenz mit aufgelöster Verschachtelung Bits des Symbols von hoher Verlässlichkeit zugeordnet worden sind und Bits von der Paritätssequenz mit aufgelöster Verschachtelung Bits des Symbols von niedriger Verlässlichkeit zugeordnet worden sind.


     
    8. Anordnung gemäß Anspruch 7, wobei die Symbole durch eine 16QAM-Modulation moduliert werden.
     
    9. Anordnung gemäß einem der Ansprüche 7 bis 8, wobei das drahtlose Kommunikationssystem ein UTRA TDD-System ist.
     
    10. Anordnung gemäß Anspruch 9, wobei der erste und zweite Kanal in einem Transportkanal enthalten sind.
     
    11. Anordnung gemäß einem der Ansprüche 7-10, die geeignet ist, um in einem gemeinsam verwendeten Hochgeschwindigkeitsabwärtskanal zu arbeiten.
     
    12. Anordnung gemäß Anspruch 11, die geeignet ist, um in einem Hochgeschwindigkeitsabwärtspaketzugriff zu arbeiten.
     
    13. Verfahren zur Kanalzuordnung in einem drahtlosen Kommunikationssystem, wobei das Verfahren umfasst:

    Verschachteln (730) einer Bitsequenz, die systematische Bits umfasst, um eine verschachtelte systematische Bitsequenz zu erzeugen; und

    Verschachteln (740) einer Bitsequenz, die Paritätsbits umfasst, um eine verschachtelte Paritätsbitsequenz zu erzeugen,

    Gruppieren (550) von Bits von der verschachtelten Paritätsbitsequenz und Bits von der verschachtelten systematischen Bitsequenz, um Symbole zu erzeugen, wobei jedes Symbol Paritätsbits und systematische Bits umfasst, wobei Bits von der verschachtelten systematischen Bitsequenz Bits des Symbols von hoher Verlässlichkeit zugeordnet werden und Bits von der verschachtelten Paritätssequenz Bits des Symbols von niedriger Verlässlichkeit zugeordnet werden; und

    Zuordnen (760) der Symbole zu einem ungerade indizierten physikalischen Kanal und einem gerade indizierten physikalischen Kanal in einer aufsteigenden Reihenfolge in einer Vorwärtsrichtung oder einer Rückwärtsrichtung, entsprechend dem Kanalindex.


     
    14. Verfahren gemäß Anspruch 13, wobei die Symbole durch eine 16QAM-Modulation moduliert zu werden.
     
    15. Verfahren gemäß einem der Ansprüche 13-14, wobei das drahtlose Kommunikationssystem ein UTRA TDD-System ist.
     
    16. Verfahren gemäß Anspruch 15, wobei der erste und zweite Kanal in einem Transportkanal enthalten sind.
     
    17. Verfahren gemäß einem der Ansprüche 13-16, das auf einem gemeinsam verwendeten Hochgeschwindigkeitsabwärtskanal arbeitet.
     
    18. Verfahren gemäß Anspruch 17, das in einem Hochgeschwindigkeitsabwärtspaketzugriff arbeitet.
     
    19. Verfahren zur Auflösung einer Kanalzuordnung in einem drahtlosen Kommunikationssystem, wobei das Verfahren umfasst:

    Auflösen von Symbolzuordnungen in einer Vorwärts- oder Rückwärtsrichtung entsprechend einem Kanalindex, wobei Symbole in einer aufsteigenden Reihenfolge einem ungerade indizierten physikalischen Kanal, oder einem gerade indizierten physikalischen Kanal zugeordnet worden sind;

    Auflösen von Gruppen von Bits von Symbolen, um eine verschachtelte Paritätsbitsequenz und eine verschachtelte systematische Bitsequenz zu erzeugen, wobei jedes Symbol Paritätsbits und systematische Bits umfasst; und

    Auflösen der Verschachtelung der systematischen Bitsequenz, um eine Bitsequenz mit aufgelöster Verschachtelung zu erzeugen, die systematische Bits umfasst; und

    Auflösen der Verschachtelung der Paritätsbitsequenz, um eine Bitsequenz mit aufgelöster Verschachtelung zu erzeugen, die Paritätsbits umfasst, wodurch Bits von der systematischen Bitsequenz mit aufgelöster Verschachtelung Bits des Symbols von hoher Verlässlichkeit zugeordnet worden sind und Bits von der Paritätssequenz mit aufgelöster Verschachtelung Bits des Symbols von niedriger Verlässlichkeit zugeordnet worden sind.


     
    20. Verfahren gemäß Anspruch 19, wobei die Symbole durch eine 16QAM-Modulation moduliert werden.
     
    21. Verfahren gemäß einem der Ansprüche 19-20, wobei das drahtlose Kommunikationssystem ein UTRA TDD-System ist.
     
    22. Verfahren gemäß Anspruch 21, wobei der erste und zweite Kanal in einem Transportkanal enthalten sind.
     
    23. Verfahren gemäß einem der Ansprüche 19-22, das auf einem gemeinsam verwendeten Hochgeschwindigkeitsabwärtskanal arbeitet.
     
    24. Verfahren gemäß Anspruch 23, das in einem Hochgeschwindigkeitsabwärtspaketzugriff arbeitet.
     
    25. Teilnehmerausrüstung zur Verwendung in einem drahtlosen Kommunikationssystem, die eine Anordnung gemäß einem der Ansprüche 1-12 umfasst.
     
    26. Basisstation zur Verwendung in einem drahtlosen Kommunikationssystem, die eine Anordnung gemäß einem der Ansprüche 1-12 umfasst.
     
    27. Integrierte Schaltung, die die Anordnung gemäß einer der Ansprüche 1-12 umfasst.
     
    28. Computerprogrammelement, das Computerprogrammmittel zur Durchführung des Verfahrens gemäß einer der Ansprüche 13-24 umfasst.
     


    Revendications

    1. Agencement pour le mappage de canaux dans un système de communication sans fil, l'agencement comprenant :

    un premier moyen d'entrelacement (730) destiné à entrelacer une séquence de bits comprenant des bits systématiques pour produire une séquence de bits systématiques entrelacée ; et

    un second moyen d'entrelacement (740) destiné à entrelacer une séquence de bits comprenant des bits de parité pour produire une séquence de bits de parité entrelacée ;

    une logique (550) agencée pour grouper des bits provenant de la séquence de bits de parité entrelacée et des bits provenant de la séquence de bits systématiques entrelacée pour produire des symboles ; chaque symbole comprenant des bits de parité et des bits systématiques, moyennant quoi des bits provenant de la séquence de bits systématiques entrelacée sont mappés avec des bits à haute fiabilité du symbole et des bits provenant de la séquence de parité entrelacée sont mappés avec des bits à faible fiabilité du symbole ; et

    une logique de mappage (760) agencée pour mapper les symboles avec un canal physique à indexation impaire et un canal physique à indexation paire, moyennant quoi les symboles sont mappés dans un ordre croissant dans une direction avant ou une direction arrière selon l'index du canal.


     
    2. Agencement de la revendication 1 dans lequel les symboles sont agencés pour être modulés par une modulation 16QAM.
     
    3. Agencement de l'une quelconque des revendications précédentes dans lequel le système de communication sans fil est un système UTRA TDD.
     
    4. Agencement de la revendication 3 dans lequel le premier et le second canaux sont compris dans un canal de transport.
     
    5. Agencement de l'une quelconque des revendications précédentes agencé pour fonctionner sur un Canal Partagé de Liaison Descendante à Vitesse Elevée.
     
    6. Agencement de la revendication 5 agencé pour fonctionner dans un Accès par Paquets de Liaison Descendante à Vitesse Elevée.
     
    7. Agencement destiné au démappage de canaux dans un système de communication sans fil, l'agencement comprenant :

    une logique de démappage agencée pour démapper les symboles dans une direction avant ou arrière en fonction d'un index de canal où les symboles ont été mappés dans un ordre croissant avec un canal physique à indexation impaire ou un canal physique à indexation paire ;

    une logique agencée pour dégrouper les groupes de bits provenant des symboles pour produire une séquence de bits de parité entrelacée et une séquence de bits systématiques entrelacée, chaque symbole comprenant des bits de parité et des bits systématiques ; et

    un premier moyen de désentrelacement destiné à désentrelacer la séquence de bits systématiques pour produire une séquence de bits désentrelacée comprenant des bits systématiques ; et

    un second moyen de désentrelacement destiné à désentrelacer la séquence de bits de parité pour produire une séquence de bits désentrelacée comprenant des bits de parité, moyennant quoi les bits provenant de la séquence de bits systématiques désentrelacée ont été mappés avec des bits à haute fiabilité du symbole et les bits de la séquence de parité désentrelacée ont été mappés avec des bits à faible fiabilité du symbole.


     
    8. Agencement de la revendication 7 dans lequel les symboles sont modulés par une modulation 16QAM.
     
    9. Agencement de l'une quelconque des revendications 7 à 8 dans lequel le système de communication sans fil est un système UTRA TDD.
     
    10. Agencement de la revendication 9 dans lequel le premier et le second canaux sont compris dans un canal de transport.
     
    11. Agencement de l'une quelconque des revendications 7-10 agencé pour fonctionner sur un Canal Partagé de Liaison Descendante à Vitesse Elevée.
     
    12. Agencement de la revendication 11 agencé pour fonctionner dans un Accès par Paquets de Liaison Descendante à Vitesse Elevée.
     
    13. Procédé de mappage de canaux dans un système de communication sans fil, le procédé comprenant les étapes consistant à :

    entrelacer (730) une séquence de bits comprenant des bits systématiques pour produire une séquence de bits systématiques entrelacée ; et

    entrelacer (740) une séquence de bits comprenant des bits de parité pour produire une séquence de bits de parité entrelacée,

    grouper (550) des bits provenant de la séquence de bits de parité entrelacée et des bits provenant de la séquence de bits systématiques entrelacée pour produire des symboles, chaque symbole comprenant des bits de parité et des bits systématiques, moyennant quoi des bits provenant de la séquence de bits systématiques entrelacée sont mappés avec des bits à haute fiabilité du symbole et des bits provenant de la séquence de parité entrelacée sont mappés avec des bits à faible fiabilité du symbole ; et

    mapper (760) les symboles avec un canal physique à indexation Impaire et un canal physique à indexation paire dans un ordre croissant dans une direction avant ou une direction arrière selon l'index du canal.


     
    14. Procédé de la revendication 13 dans lequel les symboles sont modulés par une modulation 16QAM.
     
    15. Procédé de l'une quelconque des revendications 13-14 dans lequel le système de communication sans fil est un système UTRA TDD.
     
    16. Procédé de la revendication 15 dans lequel le premier et le second canaux sont compris dans un canal de transport.
     
    17. Procédé de l'une quelconque des revendications 13-16 fonctionnant sur un Canal Partagé de Liaison Descendante à Vitesse Elevée.
     
    18. Procédé de la revendication 17 fonctionnant dans un Accès par Paquets de Liaison Descendante à Vitesse Elevée.
     
    19. Procédé de démappage de canaux dans un système de communication sans fil, le procédé comprenant les étapes consistant à :

    démapper les symboles dans une direction avant ou arrière en fonction d'un index de canal où les symboles ont été mappés dans un ordre croissant avec un canal physique à indexation impaire ou un canal physique à indexation paire ;

    dégrouper les groupes de bits provenant des symboles pour produire une séquence de bits de parité entrelacée et une séquence de bits systématiques entrelacée, chaque symbole comprenant des bits de parité et des bits systématiques ;

    désentrelacer la séquence de bits systématiques pour produire une séquence de bits désentrelacée comprenant des bits systématiques ; et

    désentrelacer la séquence de bits de parité pour produire une séquence de bits désentrelacée comprenant des bits de parité, moyennant quoi les bits provenant de la séquence de bits systématiques désentrelacée ont été mappés avec des bits à haute fiabilité du symbole et les bits de la séquence de parité désentrelacée ont été mappés avec des bits à faible fiabilité du symbole.


     
    20. Procédé de la revendication 19 dans lequel les symboles sont modulés par une modulation 16QAM.
     
    21. Procédé de l'une quelconque des revendications 19-20 dans lequel le système de communication sans fil est un système UTRA TDD.
     
    22. Procédé de la revendication 21 dans lequel le premier et le second canaux sont compris dans un canal de transport.
     
    23. Procédé de l'une quelconque des revendications 19-22 fonctionnant sur un Canal Partagé de Liaison Descendante à Vitesse Elevée.
     
    24. Procédé de la revendication 23 fonctionnant dans un Accès par Paquets de Liaison Descendante à Vitesse Elevée.
     
    25. Equipement utilisateur destiné à être utilisé dans un système de communication sans fil comprenant un agencement tel que revendiqué dans l'une quelconque des revendications 1-12.
     
    26. Station de base destinée à être utilisé dans un système de communication sans fil comprenant un agencement tel que revendiqué dans l'une quelconque des revendications 1-12.
     
    27. Circuit intégré comprenant l'agencement de l'une quelconque des revendications 1-12.
     
    28. Elément de programme informatique comprenant un moyen de programme informatique destiné à exécuter le procédé de l'une quelconque des revendications 13-24.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description