(19)
(11)EP 1 531 492 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
11.07.2018 Bulletin 2018/28

(43)Date of publication A2:
18.05.2005 Bulletin 2005/20

(21)Application number: 04026606.6

(22)Date of filing:  09.11.2004
(51)International Patent Classification (IPC): 
H01L 23/492(2006.01)
H01L 23/485(2006.01)
H01L 23/31(2006.01)
H01L 21/56(2006.01)
(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LU MC NL PL PT RO SE SI SK TR
Designated Extension States:
AL HR LT LV MK YU

(30)Priority: 14.11.2003 JP 2003385645

(71)Applicant: Stanley Electric Co., Ltd.
Meguro-ku Tokyo 153-8636 (JP)

(72)Inventors:
  • Tsuchiya, Masahiko
    Meguro-ku Tokyo (JP)
  • Horio, Naochika
    Meguro-ku Tokyo (JP)

(74)Representative: Emde, Eric 
Wagner & Geyer Gewürzmühlstrasse 5
80538 München
80538 München (DE)

  


(54)Semiconductor device and its manufacturing method capable of preventing short circuit of electrodes when semiconductor device is mounted on sub-mount substrate


(57) A confronting surface of a substrate (1) faces a first surface of a semiconductor element (30). Extension layers (4,5) are formed on the substrate at positions facing electrodes (36,37) on the semiconductor element (30). A levee film (14) is disposed on one of the confronting surface and the first surface. Openings (15,16) are formed through the levee film (14). Connection members (38,39) which is filled but is not completely filled in the openings (15,16) connect the electrodes (36,37) and the extension layers (4,5).







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Search report