(19)
(11)EP 0 220 895 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
22.07.1992 Bulletin 1992/30

(21)Application number: 86308074.3

(22)Date of filing:  17.10.1986
(51)International Patent Classification (IPC)5H03L 7/20

(54)

Improvements in and relating to signal generators

Signalgeneratoren

Générateurs de signaux


(84)Designated Contracting States:
DE FR

(30)Priority: 21.10.1985 GB 8525878

(43)Date of publication of application:
06.05.1987 Bulletin 1987/19

(73)Proprietor: Wiltron Measurements Limited
Stevenage, Herts SG1 2BY (GB)

(72)Inventors:
  • Turl, Christopher Brian D.
    Letchworth Hertfordshire (GB)
  • Hurst, Geoffrey John
    Royston Hertfordshire (GB)

(74)Representative: Nash, Keith Wilfrid 
KEITH W. NASH & Co. Pearl Assurance House 90-92 Regent Street
Cambridge CB2 1DP
Cambridge CB2 1DP (GB)


(56)References cited: : 
US-A- 3 427 561
US-A- 4 038 612
US-A- 3 641 434
US-A- 4 349 789
  
  • HEWLETT PACKARD J., vol. 30, no. 8, August 1979, pages 13-19,Palo Alto, US; L.R. MARTIN et al.: "A synthesized microwave local oscillator with continuous-sweep capability"
  • 1982 IEEE MTT-S INTERNATIONAL MICROWAVE SYMPOSIUM DIGEST, Dallas, Texas, 15th-17th June 1982, pages 494-496, IEEE; M.P. FORTUNATO et al.: "A broadband, solid state millimeter-wave synthesizer"
  • TOUTE L'ELECTRONIQUE, no. 500, January 1985, pages 47-48, Paris, FR: "Vobulateur synthétisé 10 MHz - 26,5 GHz"
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Field of invention.



[0001] This invention concerns signal generators particularly stablised signal generators capable of operating in the GHz range either in continuous wave (CW) mode or Swept frequency mode and typically used in transmission/reflection analysers.

Background to the invention.



[0002] Various source oscillators are available for generating very high frequency electrical signals but all suffer to a greater or lesser extent from drift introduced by environmental changes such as temperature, power supply fluctuations and variation in electrical components associated with the oscillatory source. Typical sources for very high frequency applications utilise a YIG oscillator or a Varactor tuned oscillator.

[0003] Techniques for improving frequency stability fall under two headings;

a) techniques for unlocked sources, and

b) techniques for locked (usually phase-locked) sources.



[0004] In the case of unlocked systems, an open loop form of correction is normally incorporated with some form of linearisation circuit. This type of approach can vary from simple diode shaping networks which are common with Varactor tuned circuits to more complex PROM data correction incorporated into microprocessor controlled signal generators. Because the circuits are open loop, no correction is possible for frequency shifts with time or mismatch errors.

[0005] By using a temperature sensing thermistor, a correction signal can be generated to assist in correcting the source frequency for temperature drift. However, in all other respects the arrangement is essentially open loop.

[0006] With locked systems, a signal is derived from the high frequency source using a Down-Conversion principle so as to obtain a signal having a lower frequency than the source, and this Down-Converted signal is compared with a Reference Signal normally derived from a crystal controlled oscillator. The comparison occurs in a phase detector the output of which is a voltage proportional to the phase error of the two signals. The correction voltage is applied to the tuning port of the high frequency source oscillator to correct for frequency shifts and by the nature of the system remarkably high levels of accuracy can be achieved.

[0007] Thus whilst open loop systems typically have an accuracy which will allow the generated signal to lie within a range of +/- 5 MHz in a signal approaching 2000 MHz, closed loop phase locked systems can achieve accuracies of better than 1 KHz in 2000 MHz.

[0008] As would be expected, closed loop phase locked systems are complex and more expensive than the relatively more simple open loop unlocked systems.

[0009] Both types of source can be configured to produce either a CW output or a Swept output.

[0010] In the case of an open loop source, frequency sweeping is achieved by adjusting the frequency determining component to a start frequency and then applying an increasing (or decreasing) tuning signal (usually a varying voltage) to the tuning port of the oscillatory device. This may be achieved by generating a ramp voltage which may be derived using analogue circuits or may be derived from a digital signal using a digital to analogue converter (DAC). Where the latter approach is used a microprocessor is conventionally employed to control the generation of the ramp voltage. Whatever type of ramp signal is used (either analogue or digitally derived) the oscillator has a varying level of frequency inaccuracy due largely to the non-linearity of the tuning port of the oscillator and temperature changes.

[0011] In the case of a phase-locked system, two approaches are possible.

[0012] In one arrangemnt the start frequency at the beginning of each sweep is phase-locked, using a phase detector, to relate the required output frequency to a reference frequency. The source is ramped in an open loop manner, the swept range being achieved in the same way as in a normal open loop case. However the accuracy is greater in that the frequency at the start of each sweep is phase-locked.

[0013] Alternatively not only the start frequency is phase-locked but a fully synthesized sweep is produced by digitally moving up (or down) in frequency by a series of steps and phase locking to each frequency step and only moving onto the next frequency step after phase locking has been achieved.

[0014] Of these two arrangements, the first offers a fast sweep update time but relatively poor frequency accuracy across the swept band whilst the second offers a much higher level of frequency accuracy during each sweep, but a slower sweep update time.

[0015] With either of the phase locked versions, any frequency drift due to time, temperature or output mis-match will be corrected-for, either instantly, or at least before each sweep. No such correction is possible within an open loop swept frequency generator.

[0016] Because of the very considerable cost of phase locked systems, various attempts have been made to improve the accuracy of open loop systems. One approach has been to generate so-called "BIRDI markers" and provide a visual display associated with the signal generator, on which the electrically generated marker signals can be displayed.

[0017] Such systems operate by producing from a crystal controlled signal, a so-called "comb" (or harmonic series) of frequencies each of which is a multiple of the frequency of the original crystal controlled signal. The generator output signal is sampled, and the sample signal is mixed with the "comb" signal. A beat or "BIRDI" is produced between components of the "comb" signal which are closest in frequency to the frequency of the output signal. Using low pass filters, the beat (or "BIRDI") signal can be separated from the higher frequency signals and can be amplified and displayed on a CRT or similar display device. Frequency correction is achieved by the user manually adjusting the master oscillator to correct for any frequency drift which will be seen as a shift of the "BIRDI" display on the screen.

[0018] Whilst a system utilising such a display has the configuration of a closed loop (when the user is considered) the accuracy achievable is far less than that of a phase-locked loop system and apart from the time delay inherent in such systems, they possess other disadvantages relative to conventional open loop systems namely:-

a) If the amplitude of the output signal is reduced, the beat signal is also reduced in amplitude and eventually can become lost within the electrical noise within the system. At this stage visual correction becomes very difficult.

b) If a very frequency selective component is tested having a very steep response curve, the beat signal can be lost in the steep component characteristic making frequency correction again very difficult.



[0019] On the other hand the generation of a beat signal from a crystal controlled source represents a simple method of generating a feedback signal and it is an object of the present invention to provide a closed loop system which is simpler and cheaper than a conventional phase-locked loop system and which derives the feedback information for frequency control from a beat signal.

[0020] US A-3 427 561 (Hamer) shows a frequency synthesiser in which the output frequency of a voltage controlled amplifier is locked onto a selected one of a comb of harmonics in a reference signal.

Summary of the invention.



[0021] According to one aspect of the present invention there is proposed a method of setting up a signal generating device according to Claim 1.

[0022] Typically the calibration procedure and the frequency shifting, null point detection, signal storage and addition is under the control of a microprocessor.

[0023] According to another aspect of the present invention there is proposed a signal generating device according to Claim 3.

[0024] The beat signal of interest may be selected from the large number of sum and difference signals by separation on a frequency selective basis using a low pass filter.

[0025] Typically the crystal controlled oscillator is set to operate at a frequency of the order of 25MHz if the master oscillator is to operate at frequencies in the range 1MHz upwards.

[0026] According to another aspect of the invention Claim 4 proposes a a method of controlling the frequency of oscillation of a master oscillator in a signal generating device.

[0027] It will be seen that after the calibration procedure has been effected, the frequency of the master oscillator will be correct and thereafter remain so depending on the quality of any open loop correction incorporated into the signal generator such as to compensate for thermal drift and the like.

[0028] When the master oscillator is called upon to sweep through a range of frequencies, the method according to the invention preferably includes the steps of:

(1) varying the computed control signal using the corrected control signal as a starting point, the variation being in accordance with an algorithm linking the frequency of oscillation with value of the control signal,

(2) when the final target frequency of the sweep has been reached, thereafter inhibiting the output of the signal generator, and

(3) thereafter repeating the correction process involving the aforementioned method until a beat signal is detected once again whereafter the sweep process can again be initiated.



[0029] The reference signal may be a so-called harmonic spectrum signal typically derived from a crystal controlled source. by means of a step recovery diode or the like.

[0030] It will be seen that with this form of correction, the linearity of the sweep frequency will be dictated inter alia by the accuracy of the algorithm linking the oscillator frequency to the control signals therefor.

[0031] If the algorithm is an imperfect description of the frequency versus control signal relationship or if the particular master oscillator is relatively non-linear and the algorithm is a theoretical description of the performance of a more linear version of such a device, then the resulting sweep will not be particularly linear.

[0032] Unless sweep time does not permit, a preferred method according to the invention involves the steps of:

(1) identifying a series of key frequencies throughout the range which is to be swept and starting with either the lowest or the highest, making corrections to the control signal supplied to the master oscillator until a beat signal is produced by the interaction of the master oscillator output signal and a component of the reference signal,

(2) modifying the corrected control signal in accordance with the known algorithm to produce a control signal for obtaining frequencies in between the first frequency and the next target frequency,

(3) when the next target frequency is approached, repeating the calibration process for the oscillator control signal before continuing to alter the frequency of the oscillator through the next range of frequencies to the next target frequency.



[0033] In this way the frequency of the master oscillator is corrected at each of a series of steps throughout the range and if high accuracy is required, a correspondingly large number of steps may be employed.

[0034] Typically digital signals are generated by the microprocessor and digital to analogue converters (DAC's) serve to convert the digital signals to voltages or currents which can be used to control the frequency of the master oscillator.

[0035] Selection of the appropriate beat signal is most conviently achieved using a low pass filter set to transmit signals in the range d.c. to f (where f may for example lie in the range of 500KHz to 5MHz).

[0036] In view of the attenuation effect of a low pass filter, signal amplifying and pulse conditioning circuit means is preferably provided after the low pass filter and before the microprocessor.

[0037] Typically the high accuracy fixed frequency oscillatory source is a crystal controlled oscillator.

[0038] High levels of accuracy are achievable by determining from the width of the beat signal pulse the precise mid-position of the selected beat signal pulse, which corresponds to the null frequency or DC content within the beat signal. Thus the microprocessor is preferably programed to seek out the mid-position of any beat signal pulse detected thereby and to use the determined mid-position of the pulse as the target.

[0039] Where the stored information is in digital form and alteration to this information is in the form of a digital error signal which is produced by the microprocessor, both the stored information and the error signal can be converted to analogue signals to enable them to be summed more easily than would otherwise be the case.

[0040] In a Sweep mode, i.e. where tie generator produces a signal whose frequency varies with time from a first frequency (f1) to a second frequency (f2) defining a Swept Band, conveniently two items of information are entered into a memory associated with the miroprocessor namely;

1. the Sweep Width (i.e. F2 - F1), and

2. the Centre of the Swept Range (i.e. ½(F2 + F1)).



[0041] The process of finding the start of the Swept Range involves the steps of:-

1. from the Sweep Width and the Centre information a microprocessor is programmed to compute a control signal so that digital to analogue converter means initialised by the microprocessor produces one or more analogue signals which should theoretically cause the master oscillator to generate the start frequency

2. simultaneously an error DAC (whose output is combined with the first mentioned DAC means) is set to mid-range;

3. a correction in the error signal is then produced by the microprocessor so as to alter the output from the error DAC until a beat or difference signal is detected.

4. the total correction to the value of the error signal required to produce a beat signal pulse is stored in a buffer memory for subsequent reference.

5. an adjustment in the control signals supplied to the master oscillator is effected according to the frequency/control signal characteristic of the master oscillator, using the stored values in the buffer as a starting point, to obtain a new frequency of operation of the master oscillator corresponding to the Start frequency (f1) of the Sweep.

6. a Sweep is effected by the microprocessor producing a varying output signal which is applied to the frequency controlling element of the master oscillator so as to produce the desired sweep in the output frequency thereof from f1 to f2.



[0042] At the end of each Sweep, the microprocessor reverts to a search routine to locate the beat signal to recalibrate the oscillator, so that the latter is corrected at the beginning of each Sweep.

[0043] Preferably the master oscillator includes two frequency controlling elements, a first one for effecting large changes in frequency and a second for effecting smaller changes in frequency, each having an input, and the control device such as a microprocessor driven controller is adapted to produce a first control signal for the first input and a second control signal for the second input. Where an error signal is generated by the control device, this may be added to or subtracted from the value of the said second control signal.

[0044] For high frequency applications the master oscillator is preferably a YIG oscillator having a main tuning coil for wide range tuning and a smaller FM coil for fine range tuning.

[0045] Alternatively a Varactor tuned oscillator may be employed.

Description of drawings.



[0046] The invention will now be described by way of example with reference to the accompanying drawings in which:-

Figure 1 illustrates diagrammatically an open loop oscillator with temperature correction,

Figure 2 illustrates a closed loop oscillator or synthesizer.

Figure 3 is a block circuit diagram of a crystal controlled beat signal (marker) generating circuit for frequency calibration of a master oscillator embodying the present invention,

Figure 4a and Figure 4b illustrate a typical marker pulse structure,

Figure 5 is a block circuit diagram of an RF source with drive circuitry and beat signal (marker) locking loop, embodying the invention,

Figure 6 is a schematic diagram of an alternative system embodying the invention but without a programmed microprocessor as required in Figure 5, and

Figure 7 shows a double down conversion system based on the circuit of Figure 3, by which the RF range can reach as high as 30GHz.



[0047] Figure 1 does not illustrate an embodiment of the present invention but indicates how temperature correction can be applied to an oscillator. It is anticipated that correction of this nature could be included in embodiments of the present invention.

[0048] Thus in Figure 1 a YIG oscillator 10 has a coarse tuning port 12 associated with the main tuning coil and a fine tuning port 14 associated with the FM coil. Signal amplifiers 16 and 18 serve to supply control signals to ports 12 and 14 respectively. Coarse frequency adjustment typically in the form of a potentiometer is not shown but the fine frequency drive input is shown as having been derived from an amplifier 20 the input of which includes a temperature correction resistor or thermistor 22. By positioning the latter to sense changes in temperature of oscillator 10, so a compensating error signal can be fed back via amplifiers 20 and 18 to the input 14 to correct for temperature drift.

[0049] The output frequency on line 24 will thus be better stabilised than without the temperature correction.

[0050] Figure 2 illustrates a more complex, closed loop phase locked oscillator. Similar reference numerals have been used to denote parts in common with Figure 1.

[0051] The primary difference between the two circuits is that a closed loop is formed between the output 24 and the fine frequency drive amplifier 18 input at 26. The loop is closed by means of a programmable divider 28 feeding a low frequency signal to a phase detector 30 to which a reference signal is supplied at 32 typically from a crystal controlled oscillator.

[0052] Any minute change in frequency between the sub-multiple of the output frequency on line 24 and the crystal controlled frequency on input 32 will be seen as a phase difference, and an error signal generated by the phase detector is supplied to the fine tuning port 14 via amplifier 18. Very high levels of accuracy can be attained using this type of circuit.

[0053] The complexities and cost however of such circuits particularly at very high frequencies means that there is a place for an alternative approach in accordance with the present invention.

[0054] Figure 3 is a block circuit diagram of an embodiment of the present invention. As before common parts have been identified by reference numerals already used in Figures 1 and 2.

[0055] The invention is primarily directed to very high frequency signal generators (although it is not limited to such applications) and in particular to signal generators for generating signals in the range 1 MHz to 2000 MHz.

[0056] In accordance with the invention digital signals from a microprocessor (not shown) are supplied via DAC 34 to amplfier 16 and via DAC 36 to the input of amplifiers 18. DAC 38 supplies an error signal combination with the output DAC 36.

[0057] The sampled signal from line 24 is applied as one input to a mixer or sampler 40 the other input of which comprises a signal derived from a crystal controlled oscillator 42, operating typically at 25 MHz, the output of which is amplified in a power amplifier 44 and is then applied via a step recovery diode 46 to produce a so-called "comb" signal or harmonic spectrum signal, in which the lowest frequency is 25 MHz and the highest is dictated inter alia by the bandwidth of the circuitry.

[0058] The conversion of the 25 MHz fixed frequency signal into the harmonic spectrum signal ensures a large number of so-called "BIRDI" markers are generated, with which the sample signal can be compared.

[0059] The comparison is effected by a mixing technique which results in sum and difference signals in the output of the mixer device 40. A low pass filter 48 eleminates all but the most useful beat signal pulses and to this end is a low pass filter having a 1 MHz cut-off. The attenuated output is amplified by amplifier 50 and supplied via pulse conditioning circuit 52 to a microprocessor.

[0060] Reference to Figures 4a and 4b will better indicate the nature of the pulses in the output of conditioner 52.

[0061] At Figure 4a can be seen the output pulses from the low pass filter, to a small scale, which is generated whenever the oscillator frequency passes through a harmonic component of the 25 MHz reference signal each such pulse is itself made up of a number of pulses (see Figure 4b) the repetition frequency of which varies from a relatively high level near the edges of the pulse to a d.c. level (in theory) in the middle of the pulse. Edge regions are denoted by reference numerals 54 and 56 in Figures 4a and 4b and the central d.c. zone is denoted by reference numeral 58.

[0062] Since the pulses such as 60 as shown in Figure 4a, are relatively narrow, to a first approximation the leading edge (or the trailing edge) of each said pulse can be detected and used to denote the arrival of a beat signal.

[0063] According to a preferred aspect of the invention, apparatus is provided for determining the mid-point of each such pulse 60 so that the true DC or null frequency zone is used to determine the actual presence of the pulse.

[0064] Figure 5 illustrates a development of the system shown in Figure 3 and includes in a general sense a microprocessor control system not previously shown.

[0065] Where components are commmon to the preceding Figures, the same reference numerals have been employed. Thus a YIG oscillator 10 provides an RF output along line 24 and the content of the elements 40, 42, 44, 46, 48, 50 and 52 are for convenience shown as a single element in Figure 5 identified by reference numeral 62. One output from this element comprises the RF output socket 64 and the other output comprises the so-called marker output at which electrical pulses comprising the beat signal pulses or markers are produced by the interaction of the output from the YIG oscillator and the harmonics derived from the output from the local crystal controlled oscillator 42 of Figure 3.

[0066] The individual pulses are referred to as markers and in the insert within Figure 5 is shown a plurality of such marker pulses 66 and an enlarged view of the first one. It will be seen fromm the enlargement that this is made up of a plurality of individual pulses of varying amplitude and frequency including a central region having essentially zero frequency, ie DC, denoted by reference numeral 68.

[0067] By virtue of the manner in which the pulses such as 66 are generated, the presence of the DC level within the pulse 66 indicates a particular relationship between the output of the YIG oscillator and the output of the crystal controlled oscillator 42 and is also indicative of the values of the control signals which are for the time being supplied to the YIG oscillator.

[0068] The determination of the existence of a null frequency zone or DC level within the pulses such as 66 is most simply achieved using a microprocessor controlled pulse analysing circuit generally designated 70 and a marker pulse interface unit 72 (part of which is incorporated in the pulse conditioning circuit 52 of Figure 3), is required between the output from the mixer and low pulse filter of the circuitry contained within item 62 and the input to the microprocessor control system 70.

[0069] The latter determines the width of the first marker pulse 66 and the half-way point which corresponds to the point at which there is a one to one relationship between the YIG oscillator frequency and the frequency of the crystal controlled oscillator 42 of Figure 3. The microprocessor control system includes a keyboard or other data input device such as 74 and the latter may be dedicated to the instrument so as to include dedicated controls such as Start/Stop and Centre/Width keys.

[0070] The signal generator of Figure 5 is normally used in a Sweep mode of operation and in relation to much of the further description of the operation of the circuit, it will be assumed that this is the mode of operation which has been selected.

[0071] Initial presetting of the Sweep Width (scaling) and Centre is determined by the required Start and Stop frequencies that the source is to sweep over. The YIG oscillator 10 has thus to be driven between a Start and Stop frequency by controlling the electric signals supplied to two different frequency controlling elements within the oscillator as described in relation to Figure 3. However, in order to give a greater control over the setting up of the sweep, three Digital to Analogue converters are provided in place of the two described with reference to Figure 3. Thus a first DAC 76 determines the Centre of the sweep, a second DAC produces a ramp voltage which must be supplied to one or other of the drive amplifiers 16 and 18 via a scaling DAC 80 and a third DAC 82 provides error signal conversion as an input to the second driver amplifier 18 for correcting for drift and controlling the tuning of the source.

[0072] A selector switch 84 enables the output from the scaling DAC 80 to be supplied as an input to either amplifier 16 or amplifier 18.

[0073] A common source 86 provides the reference signals for the three DACs 76, 78 and 82 and the Data BUS from the microprocessor driven control system 70 is supplied as a main data input to each of the DACs.

[0074] The data highway 88 supplies information relating to the tuning of the YIG oscillator 10 and also the Sweep parameters such as Start and Stop frequencies, and the Sweep Width information for DAC 80, Sweep DAC 78 and Centre DAC 76.

[0075] During each sweep, the sweep DAC is the only converter that needs to be altered dynamically. Information supplied via data highway 88 and 92 causes 78 to produce a fixed ramp signal the actual shape and amplitude of which is determined by parameters within the microprocessor. The actual amplitude of the ramp signal is then scaled by the converter 80 again using information from the microprocessor 70 to cover the appropriate sweep width dictated by information supplied via the data input keyboard 74.

[0076] The function of the Error DAC is to "nudge" the frequency produced by the YIG oscillator 10 by up to +/- 25 MHz under the control of the microprocessor. This is used to shift the frequency of the signal produced by the YIG oscillator 10 until it becomes a whole number multiple of one of the harmonic components of the comb signal from circuit element 46.

[0077] The response of the Error DAC must be calibrated, stable and fast so that the frequency of the YIG oscillator can be rapidly altered with precision anywhere within the range of the 50 MHz governed by the nudge facility. In this way, as long as a beat signal can be located at some point within the 50 MHz band, the YIG oscillator can be calibrated to a frequency within +/- 25 MHz of the desired final frequency thereby enabling the YIG oscillator to be shifted subsequently to the desired frequency by the application of an additional "error" signal, via DAC 82, to the frequency controlling signals already supplied to the oscillator during calibration.

[0078] The nudging action of the microprocessor and Error DAC 82 thus serves two purposes:-
  • During calibration of the YIG oscillator at the beginning of each sweep, the nudge facility enables the YIG oscillator frequency to be shifted quickly and accurately throughout a 50 MHz band in order to find at least one (and preferably two) beat signals (normally referred to as markers), and
  • after calibration, the same two components (ie microprocessor 70 and Error DAC 82) serve to generate the DC shift signal required to shift the frequency of the YIG oscillator to the desired frequency called for by the input information fed to the microprocessor.


[0079] The process of locating a beat signal or marker pulse such as 66 involves the following:

1. From the selection of a frequency span, the Centre, Sweep Width and Sweep DACs are all initialised and the Error DAC 82 is adjusted to mid-range under the control of the microprocessor 70.

2. As the sweep is about to commence, a search routine is instigated by the microprocessor in which the Error DAC 82 is adjusted first in one direction (typically down) until a marker pulse 66 is detected by the marker interface 72.
Typically this is set to look for a change in amplitude with a transition from high frequency content through to DC and back to high frequency content in the amplitude excursion concerned. The position of the null point or DC level within the detected pulse 66 is noted and the value of the error signal or nudge required to produce that particular beat signal is stored in the microprocessor memory.

3. Having established the signal required on the FM coil of the YIG oscillator to produce the marker pulse, the oscillator has effectively been calibrated. It is now a simple matter for the microprocessor to compute the additional signal to be added to (or subtracted from) the signal known to produce the same frequency as the identified comb signal component, in order to achieve the desired frequency.



[0080] Where it happens that the desired frequency is that of the marker (comb signal component), no addition orsubtraction is required.

[0081] In the more general case where the desired Start frequency is not equal to one of the comb components, an algorithm or a look-up table is employed to determine the signal correction required to acheive the desired frequency from the calibration frequency.

[0082] The algorithm or look-up table may be stored in the microprocessor memory (or in a ROM or entered into the machine memory via a keyboard), and describes the frequency response of the YIG oscillator 10 for different signals supplied to the main and subsidiary frequency determining coils.

[0083] Where very high accuracy is required, the microprocessor search routine includes steps necessary to identify the high frequency edge regions of the identified marker pulse 66 identified in Figure 5 by 94 and 96, and the microprocessor is further programmed to interpolate between these two edges of the marker pulse so as to find the mid position between the two edges 94 and 96. Since the pulse 66 is produced as the YIG oscillator frequency moves from above to below one of the comb frequencies (or in the reverse direction) the mid point 68 corresponds to when the frequency of the YIG oscillator 10 is precisely equal to the comb frequency with which it is being mixed. By incorporating this additional computation process in the microprocessor search programme, so a unique and precise signal paramter can be dictated by the processor 70 for the output from the Error DAC 82 so as to produce from the YIG oscillator 10 a signal having exactly the same frequency as that of the comb component derived from the crystal controlled oscillator 42.

[0084] Currently open loop signal generators attain frequency accuracies of the order of +/- 5MHz. Apparatus embodying the invention has achieved accuracies of +/- 100 KHz in 2000 MHz. If the YIG oscillator 10 has good linearity and predictable frequency response for changes in control signals from 16 and 18, a very precise sweep can be obtained using such a system as shown in Figure 5.

[0085] If CW operation is required, the Sweep Width is set to zero and the frequency of operation of the YIG oscillator 10 is determined by the Centre DAC 76. By setting the Error DAC 82 to mid range and then instigating the microprocessor search routine, the YIG oscillator 10 is calibrated by finding the nearest marker pulse such as 66 (and the mid position of that if that level of accuracy is required) and then computing the necessary error signal or nudge signal, required to shift the actual frequency of the YIG oscillator 10 to the desired frequency which the source 10 is to produce.

[0086] Drift particularly due to thermal considerations during CW operation may be controlled by a thermal compensation circuit such as described in relation to Figure 1.

[0087] If the CW operation can be interrupted at regular intervals, the microprocessor 70 is conveniently programmed to do this and perform a further search and calibration routine during each dead interval before switching the RF back on again.

[0088] To reduce transients and switching problems, the YIG oscillator 10 is preferably not turned on and off but the RF circuitry 62 includes a suitable attenuator for attenuating the output signal during the initial calibrating and subsequent calibrating intervals.

[0089] Such an attenuator is also preferably incorporated into a Sweep Mode of operation so as to attenuate the RF signal during the calibration at the beginning of each sweep.

[0090] Figure 6 shows a hardware implementation not incorporating a microprocessor but which is limited to the accuracy associated with merely detecting the presence of a marker pulse such as 66.

[0091] Here the marker interface comprises a pulse presence detector 114 which by any convenient means detects either the leading or trailing edge of a pulse such as shown at 66.

[0092] Frequencies corresponding to the required sweep are entered via front panel 98 and a FREQUENCY INSTRUCTION circuit 100 calculates the appropriate drive signals to set up the sweep - digital data for the driving DAC's 76 etc, or analog voltages for the drive amplifiers 16, 18. It also generates a voltage corresponding to the distance the required START frequency is away from a calibration point. This is referred to as the NUDGE SIGNAL and can be switched in or out with the switch 81. Thus if the required START is 57 MHz and a calibration point is available at 50 MHz then a signal corresponding to +7 MHz is generated. If 42 MHz is the required START point, then a signal corresponding to -8 MHz must be generated. A NULL signal (0 volts) is generated for a start frequency equalling a calibration point. This will apply where the start frequency is a multiple of 25 MHz.

[0093] The FREQUENCY INSTRUCTION circuit 100 thus sets up the drive circuits such that the START frequency is a multiple of the calibration points, and after calibration, the required START frequency is achieved by switching in the NUDGE SIGNAL and adding it to the signals set up by 100.

[0094] A SWEEP RAMP GENERATOR 102 provides a fixed ramp which drives the oscillator 10 via the drive electronics 78, 80 over the requested range. This generator starts the ramp in response to a signal on the TRIGGER input. When the ramp has finished 102 indicates this by providing a signal at the SWEEP END output 104.

[0095] A further section of hardware, LOCK CONTROL 108, provides a secondary ramp covering a small frequency range sufficient to cover the maximum errors expected. When requested by a signal at the START LOCK RAMP input 110, a ramp is started from its minimum point, and stopped when demanded by the STOP LOCK RAMP input 112.

[0096] The RF output is supplied to the MARKER PRESENCE DETECTOR 114 (already referred to) whose output is latched by a latch circuit 116. LOCK CONTROL 108 operates so that in the presence of a marker pulse 66 (corresponding to a calibration point) a STOP LOCK RAMP signal is generated for input 112 and the ramp value from 108 is held in a SAMPLE & HOLD circuit 118.

[0097] The sequence of events during a typical sweep under the control of the signals from the timing circuit 120 is as follows:

(a) The frequency parameters are entered via controls on the front panel 98. The frequency instruction circuit 100 frequency to the desired stop frequency.



[0098] It will be appreciated that the nudge signal must be removed whilst the YIG oscillator 10 is being calibrated at the begining and ending of each sweep. It is for this reason that switch S1 is provided.

[0099] If higher accuracy is required, the detector 114 can be a more complex device to interpolate from the width of the pulse 66 and generate information corresponding to the null point 68 of the detected marker pulse as described with reference to Figure 5.

[0100] Figure 7 represents a double down conversion system based on Figure 3 but which will allow the software locking to reach 30 GHz and beyond by suitable choice of the two drive frequencies.

[0101] The design and operation of the system follows similar lines to Figure 3, and similar reference numerals are employed where appropriate.

[0102] A sample of the RF output frequency is routed to a first down conversion stage comprising a sampler or mixer 126. To this sampler is applied a drive comb derived from a high frequency reference source 128 (eg a 500 MHz SAW oscillator), power amplifier 130 and a step recovery diode 132. The low frequency down conversion signal is then amplified and filtered by 134, 136 to provide a wideband drive signal to a second down conversion stage comprising a sampler or mixer 138 (corresponding to the sampler or mixer 40 of Figure 3). This mixer 138 is driven with a drive signal having much lower frequency than that for the sampler or mixer 126. Conveniently the drive reference signal for 138 is obtained from a divided down signal from the first reference signal (ie the 500 MHz SAW source), by use of a divider 140.

[0103] The remainder of the circuit functions in general as described with reference to Figure 3.

[0104] To allow for the greater non linearity and pointing inaccuracy that will occur at such high frequencies in the initial tuning of the output frequency, both the low frequency and the high frequency pulses are processed. To this end a second processing line 48', 50' & 52' is provided for the output of 136.

[0105] In use the YIG oscillator 10 is tuned approximately and the nearest relevent 500 MHz marker is searched for. Once found this can be referenced to the related 25 MHz marker on the low frequency marker output. From then on, for that output frequency range, only reference to the 25 MHz markers is needed. Only if the output frequency is to be shifted by a large amount (eg greater than say 3 GHz) would reference back to the 500 MHz marker output be needed.

[0106] There now follows a listing and general description of a programme which may be used in conjunction with a suitable microprocessor to perform the various frequency establishing steps and calibration steps of the apparatus herein described.

Marker Locking Source Code



[0107] The one entry point is the procedure LOCK_START. This assumes that the sweeper has been set up to approximately the correct frequency and that only calibration to a 25.MHz marker is now required. It is assumed that the nearest marker will be the correct one for locking to. This implies that the maximum error in placing the frequency is less than 12.5 MHz.

[0108] Call lock start when the calling procedure is ready to start a sweep, the values for the NUDGE after lock must already have been calculated (in another module) from the required start frequency. In essence this is a simple algorithm to find the remainder after multiple subtraction of 25 MHz :-
REMAINDER =
START- ([START / 25 MHz ] * 25 MHz)
IF REMAINDER > 12.5 MHz then REMAINDER =
REMAINDER - 25 MHz


[0109] Where START is the required start frequency, "/" denotes integer division. REMAINDER is then scaled according to hardware to provide the value ERROR_ DAC_NUJ which is the value to be summed in to achieve the required start frequency after locking.

[0110] The structure of the module is as follows:-

LOCK START Procedure



[0111] This is the main procedure, returning when calibration has been achieved, and the nudge has been added to achieve the required start frequency. This calls two main routines SEARCH_UP and SEARCH_DOWN.

SEARCH UP, SEARCH DOWN Procedures



[0112] These perform complete searches up and down (in frequency) looking for markers and locating their center points. The values corresponding to these points are stored in stores E1 and E2. These routines use primitive routines NUD,NDD.

NUD,NDD Procedure



[0113] These routines are Nudge Up and Detect and Nudge Down and Detect. These set up the error_dac as requested and wait to search for a marker at the frequency generated. They include some intelligence to ensure that the reported status of marker present/not present takes into account the possible hole in the center of the marker. These routines use WAIT_FOR_MARKER.

WAIT FOR MARKER Procedure



[0114] This is a primitive routine which simply takes into account hardware delays after setting up the error_dac, and then tests for the presence of a marker at that one frequency point.

TEST TO 12M5



[0115] This routine simply returns a flag indicating if the found lock point is valid due to distance away from the uncalibrated point
























Claims

1. A method of setting up a signal generating device to enable it to deliver an output frequency which may lie anywhere in a range extending up to hundreds and thousands of MHz, and which includes coarse and fine frequency controlling elements (12,14) fed with coarse and fine frequency controlling signals, wherein the fine frequency control is capable of producing linear changes in output frequency for corresponding changes in the value of an electrical signal supplied thereto, but only over a small range of N + MHz; characterised in that:

- the output of the device is combined with a multicomponent reference signal containing at least a known component having a frequency of L MHz, which is within N MHz of any desired frequency F MHz,

- the values of the coarse and fine frequency controlling signals supplied to the device are adjusted to yield an output signal having a frequency also within N MHz of the desired frequency F MHz,

- the parameter of the electrical signal controlling the fine frequency controlling element (36) is then adjusted until a beat signal is detected, at which point the device can be calibrated since the beat signal indicates a one to one relationship of the output signal and the known reference signal component L MHz and

- the values of the fine frequency controlling signals at which beat signals are detected are stored for calibration purposes,

- whereby using an algorithm or look-up table the value of a correction signal required by the fine frequency controlling element to shift the frequency of the device by (F-L) MHz can be determined and an output signal of F MHz can be obtained by using the stored calibration values of the control signals for L MHz and by adding the correction signal to the stored fine frequency signal and using the combined signal as the fine frequency controlling signal for the device.


 
2. A method according to claim 1, wherein the calibration procedure and the frequency shifting, beat signal detection, signal storage and addition is under the control of a microprocessor.
 
3. A signal generating device whose output frequency is to be set at a frequency F, including a master oscillator (10) having an output at which a radio frequency signal appears when the oscillator is operating and having associated therewith a large bandwidth frequency controlling element and a small bandwidth frequency controlling element by which linear changes in the output frequency over the small band of frequencies can be obtained by making corresponding changes in a parameter of an electrical signal supplied thereto, characterised by:-

(1) a control system adapted to generate, from information entered therein, electrical signals for controlling the frequency of the master oscillator,

(2) means for deriving a sample signal from the output of the master oscillator,

(3) a stable fixed frequency oscillatory signal source (42) for producing a reference signal F(ref),

(4) circuit means (44,46) for producing from the reference signal F(ref) a harmonic spectrum or "comb" of signals F(ref); 2F(ref); 3F(ref) ...n.F(ref), + referred to as a harmonic spectrum signal, at least one component of which is within the said small band of frequencies from F,

(5) mixing or sampling circuit means (40) for combining the sampled signal with the harmonic spectrum signal to produce beat signals, i.e. signals having frequencies which are inter alia the arithmetic difference between the frequency of the sample signal and the component in the said harmonic spectrum signal, and

(6) beat signal detector circuit means (48, 50, 52) responsive to the output of the mixing circuit means and adapted to identify when a beat signal pulse is occurring;

and by the provision of the following elements for the purpose of frequency calibration: a programmed control system to alter the frequency controlling signals supplied to the master oscillator tuning controls until a beat signal is produced caused by the interaction of the master oscillator output signal and a component N.F(ref) of the harmonic spectrum signal; means for detecting a beat signal at which point the values of the frequency controlling signals supplied to the master oscillator are known to be producing a frequency of N.F(ref); and means storing an algorithm or look-up table which describes the frequency response of the master oscillator to control signals supplied to the frequency controlling elements thereof,

wherein said programmed control means includes means for computing new values for the control signals supplied to the small band width frequency controlling element using the algorithm or look-up table and the values of the frequency controlling signals which produce the detected beat frequency with the N.F(ref) signal, the said new values causing the master oscillator to shift in frequency from N.F(ref) to the desired frequency F.


 
4. A method of controlling the frequency of oscillation of a master oscillator in a signal generating device in which a linear frequency controlling element (36) responsive to a control signal has a restricted frequency sweep capability, characterised by the steps of:-

(1) generating frequency control signals which will produce a signal in the output of the master oscillator which if not equal to F is close thereto, and applying same to the oscillator,

(2) combining a sample of the master oscillator output signal with a reference signal having a component which is sufficiently close to the desired frequency F as to be within the said restricted frequency sweep from the frequency of oscillation F, of the master oscillator;

(3) adjusting the value of the signal supplied to the linear frequency control until a beat signal is detected between the master oscillator output signal and the reference signal component, and

(4) adjusting the value of the control signal for the linear frequency controlling element from the value corresponding to the value at which the beat signal is detected to a new value computed using an algorithm or look-up table relating the frequency response of the master oscillator to the values of the frequency control signals therefor, so as to shift the master oscillator ouput to the desired frequency F.


 
5. A method according to claim 4, wherein, when the master oscillator is called upon to sweep through a range of frequencies, the method is charactersied by the steps of:

(1) varying the computed control signal using the corrected control signal as a starting point, the variation being in accordance with an algorithm linking the frequency of oscillation with value of the control signal,

(2) when the final target frequency of the sweep has been reached, thereafter inhibiting the output of the signal generator, and

(3) thereafter repeating the correction process involving the aforementioned method until a beat signal is detected once again whereafter the seep process can again be initiated.


 
6. A method according to claim 5, characterised in that the reference signal is an harmonic spectrum signal, and characterised by

(1) identifying a series of key frequencies throughout the range which is to be swept and starting with either the lowest or the highest, making corrections to the control signal supplied to the master oscillator until a beat signal is produced by the interaction of the master oscillator output signal and a component of the reference signal,

(2) modifying the corrected control signal in accordance with the known algorthim to produce a control signal for obtaining frequencies in between the first frequency and the next target frequency,

(3) when the next target frequency is approached, repeating the calibration process for the oscillator control signal before continuing to alter the frequency of the oscillator through the next range of frequencies to the next target frequency.


 
7. A signal generating device or method of operation thereof according to any preceding claim characterised by a microprocessor adapted to control the signal generating device or to perform the method, and wherein digital signals are generated by the microprocessor and digital to analogue converters (DAC's) (34, 36, 38) serve to convert the digital signals to voltages or currents which can be used to control the frequency of the master oscillator.
 
8. A signal generating device or method according to any preceding claim, characterised in that selection of the beat signal is achieved by means of a low pass filter (48) set to transmit signals in the range d.c. to f, where f typically lies in the range 500 kHz to 5 MHz, and in that signal amplifying means (50) and pulse conditioning circuit means (52) is provided after the low pass filter and before the microprocessor.
 
9. A signal generating device or method according to any preceding claim, characterised by a microprocessor adapted to control the signal generating device or to perform the method and also to determine from the width of the beat signal pulse the precise mid-position of the selected beat signal pulse, which corresponds to the null frequency or DC content of the beat signal, the microprocessor being programmed to seek out the mid-position of any beat signal pulse detected thereby and to use the determined mid-position of the pulse to target the frequency controlling signal value corresponding thereto.
 
10. A signal generating device or method having microprocessor control according to any preceding claim, characterised in that, for operation in the sweep mode, i.e. where the generating device produces a signal whose frequency varies with time from a first frequency (f1) to a second frequency (f2) defining a swept band, two items of information are entered into a memory associated with the microprocessor namely:

(a) the sweep width (i.e. F2 - F1), and

(b) the centre of the swept range, i.e. 1/2(F2 + F1), and in that the start of the swept range is found by the following steps:-

(1) from the sweep width and the centre range information a microprocessor is programmed to compute a control signal so that digital to analogue converter means, DAC, initialised by the microprocessor produces one or more analogue signals which should theoretically cause the master oscillator to generate the start frequency,

(2) simultaneously an error DAC, whose output is combined with the first mentioned DAC means, is set to mid-range,

(3) a correction in the error signal is then produced by the microprocessor so as to alter the output from the error DAC until a beat or difference signal is detected,

(4) the total correction to the value of the error signal required to produce a beat signal pulse is stored in a buffer memory for subsequent reference,

(5) an adjustment in the control signals supplied to the master oscillator is effected according to the frequency/control signal characteristic of the master oscillator, using the stored values in the buffer as a starting point, to obtain a new frequency of operation of the master oscillator corresponding to the start frequency (f1) of the sweep,

(6) a sweep is effected by the microprocessor producing a varying output signal which is applied to the frequency controlling element of the master oscillator so as to produce the desired sweep in the output frequency thereof from f1 to f2.


 


Revendications

1. Un procédé d'ajustement d'un dispositif générateur de signaux,pour lui permettre de fournir une fréquence de sortie qui peut être située à un emplacement quelconque dans une plage s'étendant jusqu'à des centaines et des milliers de MHz, et qui comprend des éléments (12, 14) de réglage grossier et fin de fréquence, alimentés par des signaux de réglage grossier et fin de cette fréquence, pour lequel le réglage fin de fréquence est susceptible de produire des modifications linéaires de fréquence de sortie pour des variations correspondantes de la valeur d'un signal électrique qui lui est fourni, mais seulement sur une petite plage de N ± MHz; caractérisé en ce que :

- la sortie du dispositif est combinée avec un signal de référence à composants multiples, contenant au moins un composant connu d'une fréquence de L MHz, qui s'écarte de moins de N MHz d'une fréquence souhaitée quelconque F MHz,

- les valeurs des signaux de réglage grossier et fin de fréquence fournis au dispositif sont ajustées pour fournir un signal de sortie dont la fréquence s'écarte aussi de moins de N MHz de la fréquence souhaitée F MHz,

- le paramètre du signal électrique réglant l'élément (36) de réglage fin de fréquence est ensuite ajusté jusqu'à ce qu'un signal de battement soit détecté, et le dispositif peut dès lors être calibré puisque le signal de battement indique un rapport 1/1 du signal de sortie et du composant connu de signal de référence L MHz et

- les valeurs des signaux de réglage fin de fréquence auxquelles des signaux de battement sont détectés, sont mémorisées dans un but de calibrage,

- grâce à quoi, en utilisant un algorithme ou une table, la valeur d'un signal de correction nécessaire à l'élément de réglage fin de fréquence pour décaler la fréquence du dispositif de (F - L) MHz, peut être déterminée et un signal de sortie de F MHz peut être obtenu en utilisant les valeurs mémorisées de calibrage des signaux de réglage pour L MHz et en ajoutant le signal de correction au signal fin mémorisé de fréquence, et en utilisant le signal combiné comme signal de réglage fin de fréquence du dispositif.


 
2. Un procédé selon la revendication 1, dans lequel la procédure de calibrage et le décalage en fréquence, la détection de signaux de battement, la mémorisation de signaux et l'addition sont effectués sous la commande d'un microprocesseur.
 
3. Un dispositif générateur de signaux dont la fréquence de sortie doit être ajustée à une fréquence F, incluant un oscillateur maître (10) qui comprend une sortie à laquelle apparaît un signal de fréquence radio lorsque l'oscillateur est en fonctionnement et qui comprend un élément de réglage de fréquence à grande largeur de bande et un élément de réglage de fréquence à faible largeur de bande qui lui sont associés, au moyen desquels des variations linéaires de la fréquence de sortie, dans la faible bande de fréquence, peuvent être obtenues en effectuant des modifications correspondantes sur un paramètre d'un signal électrique qui lui est fourni,caractérisé par :

(1) un système de réglage apte à engendrer, à partir d'une information qui y est entrée, des signaux électriques destinés à régler la fréquence de l'oscillateur maître,

(2) un moyen destiné à dériver un signal d'échantillon à partir de la sortie de l'oscillateur maître,

(3) une source stable (42) de signaux oscillatoires à fréquence fixe pour produire un signal de référence F (ref),

(4) un moyen de circuit (44, 46) pour produire à partir du signal de référence F (ref) un spectre harmonique ou "peigne" de signaux F (ref); 2F (ref); 3F (ref) ... n.F (ref), appelé signal harmonique de spectre, dont au moins un composant est situé à l'intérieur de la petite bande de fréquence par rapport à F,

(5) un moyen de circuit (40) de mélange ou d'échantillonnage pour combiner le signal échantillonné avec le signal de spectre harmonique pour produire des signaux de battement, c'est-à-dire des signaux dont les fréquences sont, entre autres, la différence arithmétique entre la fréquence du signal d'échantillon et la composante dudit signal de spectre harmonique, et

(6) un moyen de circuit (48, 50, 52) détecteur de signaux de battement sensible à la sortie du moyen de circuit de mélange et apte à identifier le moment où apparaît une impulsion de signal de battement
   et par la mise en place des éléments suivants dans un but de calibrage de fréquence :
   un système de réglage programmé pour modifier les signaux de réglage de fréquence amenés aux réglages d'accord de l'oscillateur maître jusqu'à ce que soit produit un signal de battement provoqué par l'interaction du signal de sortie de l'oscillateur maître et d'un composant N.F (ref) du signal de spectre harmonique; un moyen de détection d'un signal de battement à partir duquel les valeurs des signaux de réglage de fréquence fournis à l'oscillateur maître sont aptes à produire une fréquence de N.F (ref); et un moyen de mémorisation d'un algorithme ou d'une table
   que décrit la réponse de fréquence de l'oscillateur maître à des signaux de réglage fournis à ses éléments de réglage de fréquence,
   dans lequel ledit moyen programmé de réglage comprend un moyen pour calculer de nouvelles valeurs des signaux de réglage fournisà l'élément de réglage de fréquence à faible largeur de bande en utilisant l'algorithme ou la table et les valeurs des signaux de réglage de fréquence qui produisent la fréquence détectée de battement avec le signal N.F(ref), lesdites nouvelles valeurs amenant l'oscillateur maître à se décaler en fréquence, depuis N.F (ref) jusqu'à la fréquence souhaitée F.


 
4. Un procédé de réglage de la fréquence d'oscillation d'un oscillateur maître dans un dispositif générateur de signaux dans lequel un élément linéaire (36), de fréquence sensible à un signal de réglage, possède une capacité restreinte de balayage en fréquence, caractérisé par les étapes consistant à :

(1) engendrer des signaux de réglage de fréquence qui produiront dans la sortie de l'oscillateur maître un signal qui, s'il n'est pas égal à F, en est voisin et appliquer celui-ci à l'oscillateur,

(2) combiner un échantillon du signal de sortie de l'oscillateur maître avec un signal de référence qui possède un composant qui est suffisamment voisin de la fréquence souhaitée F pour se trouver à l'intérieur dudit balayage restreint en fréquence, par rapport à la fréquence d'oscillation F de l'oscillateur maître;

(3) ajuster la valeur du signal amené au réglage linéaire de fréquence jusqu'à ce que soit détecté un signal de battement entre le signal de sortie de l'oscillateur maître et le composant du signal de référence, et

(4) ajuster, à partir de la valeur correspondant à la valeur à laquelle le signal de battement est détecté, la valeur du signal de réglage pour l'élément de réglage linéaire de fréquence à une nouvelle valeur calculée, en utilisant un algorithme ou table donnant la fréquence de réponse de l'oscillateur maître aux valeurs des signaux de réglage de fréquence qui y correspondent, de façon à décaler à la fréquence souhaitée F la sortie de l'oscillateur maître.


 
5. Un procédé selon la revendication 4, dans lequel le procédé est caractérisé, lorsque l'oscillateur maître est appelé à balayer une plage de fréquence, par les étapes consistant à:

(1) faire varier le signal calculé de réglage en utilisant comme point d'origine le signal corrigé de réglage, la variation étant conforme à un algorithme reliant la fréquence d'oscillation à la valeur du signal de réglage,

(2) lorsque la fréquence finale cible de balayage a été atteinte, bloquer ensuite la sortie du générateur de signaux, et

(3) répéter ensuite le processus de correction, impliquant le procédé ci-dessus, jusqu'à ce que soit détecté à nouveau un signal de battement, à la suite de quoi le processus de balayage peut être recommencé.


 
6. Un procédé selon la revendication 5, caractérisé en ce que le signal de référence est un signal de spectre harmonique, et caractérisé par les étapes consistant à:

(1) identifier une série de fréquences clés dans toute la plage qui doit être balayée et commencer soit par la plus basse soit par la plus élevée, effectuer des corrections du signal de réglage fourni à l'oscillateur maître jusqu'à ce qu'un signal de battement soit produit par l'interaction du signal de sortie de l'oscillateur maître et d'un composant du signal de référence,

(2) modifier le signal corrigé de réglage conformément à l'algorithme connu pour produire un signal de réglage destiné à obtenir des fréquences entre la première fréquence et la fréquence cible suivante,

(3) répéter, lorsque l'on s'approche de la fréquence cible suivante, le processus de calibrage du signal de réglage de l'oscillateur avant de continuer à modifier la fréquence de l'oscillateur dans la plage suivante de fréquence vers la fréquence cible suivante.


 
7. Un dispositif générateur de signaux ou un procédé de mise en oeuvre de celui-ci conforme à une quelconque des revendications précédentes, caractérisé par un microprocesseur apte à régler le dispositif générateur de signaux pour mettre en oeuvre le procédé et dans lequel des signaux numériques sont engendrés par ce microprocesseur et par des convertisseurs numériques analogiques (DAC) (34, 36, 38), servant à convertir les signaux numériques en tensions ou en courants qui peuvent être utilisés pour régler la fréquence de l'oscillateur maître.
 
8. Un dispositif ou un procédé de génération de signaux selon une quelconque des revendications précédentes, caractérisé en ce que le choix du signal de battement est atteint au moyen d'un filtre passe-bas (48), disposé de façon à transmettre des signaux dans la plage comprise entre un courant contenu et f, où f est typiquement située dans la plage de 500 kHz à 5 MHz, et en ce qu'un moyen (50) d'amplification de signaux et un moyen (52) de circuit de conditionnement d'impulsions sont prévus après le filtre passe-bas et avant le microprocesseur.
 
9. Un dispositif ou un procédé de génération de signaux conforme à une quelconque des revendications précédentes, caractérisé par un microprocesseur apte à régler le dispositif de générateur de signaux ou à mettre en oeuvre le procédé et à déterminer aussi à partir de la largeur de l'impulsion de signal de battement, la position médiane précise de l'impulsion de signaux de battement choisie qui correspond à la fréquence nulle ou au contenu en courant continu du signal de battement, le microprocesseur étant programmé pour rechercher la position médiane d'une impulsion quelconque de signal de battement détectée de cette manière et pour utiliser la position médiane déterminée de l'impulsion pour cibler la valeur du signal de réglage de fréquence qui lui correspond.
 
10. Un dispositif ou un procédé de génération de signaux comportant un réglage par microprocesseur selon une quelconque des revendications précédentes, caractérisé en ce que, pour le fonctionnement dans le mode de balayage, c'est-à-dire celui où le dispositif générateur produit un signal dont la fréquence varie avec le temps à partir d'une première fréquence f1 jusqu'à une deuxième fréquence f2, en définissant une bande balayée, deux éléments d'information sont entrés dans une mémoire associée au microprocesseur, à savoir:

(a) la largeur de balayage (c'est-à-dire F2 - F1), et

(b) le centre de la plage balayée, c'est-à-dire 1/2 (F2 + F1), et en ce que le début de la plage balayée est trouvé par les étapes suivantes:

(1) à partir de la largeur de balayage et de l'information de plage centrale, le microprocesseur est programmé pour calculer un signal de réglage de façon qu'un moyen convertisseur de numérique analogique (DAC) initialisé, par le microprocesseur produise un ou plusieurs signaux analogiques qui doivent théoriquement amener l'oscillateur maître à engendrer la fréquence d'origine.

(2) un DAC d'erreur, dont la sortie est combinée au premier moyen DAC mentionné, est simultanément réglé au milieu de la plage,

(3) une correction du signal d'erreur est ensuite produite par le microprocesseur de façon à modifier la sorte du DAC d'erreur jusqu'à ce que soit détecté un signal de battement ou de différence,

(4) la correction totale à la valeur du signal d'erreur nécessaire pour produire une impulsion de signal de battement est mémorisée dans une mémoire tampon en vue d'une référence ultérieure,

(5) un ajustement des signaux de réglage amenés à l'oscillateur maître est effectué selon la caractéristique fréquence/signal de réglage de l'oscillateur maître, en utilisant comme point d'origine les valeurs mémorisées dans la mémoire tampon, pour obtenir une nouvelle fréquence de fonctionnement de l'oscillateur maître, correspondant à la fréquence d'origine (f1) du balayage,

(6) un balayage est effectué par le microprocesseur en produisant un signal de sortie variable qui est appliqué à l'élément de réglage de fréquence de l'oscillateur maître de façon à produire le balayage souhaité, de f1 à f2, dans la fréquence de sortie de celui-ci.


 


Ansprüche

1. Ein Verfahren zum Vorbereiten einer Signalgeneratorvorrichtung, damit diese eine Ausgangsfrequenz irgendwo in einem Bereich bis zu hunderten und tausenden MHz liefern kann und die mit Frequenzgrob- und -feinsteuersignalen beaufschlagte Frequenzgrob- und -feinsteuerelemente (12, 14) enthält, wobei die Frequenzfeinsteuerung bei entsprechenden Änderungen im Wert eines ihr zugeführten elektrischen Signales, aber nur über einem schmalen Bereich von N ± MHz lineare Änderungen in der Ausgangsfrequenz erzeugen kann, dadurch gekennzeichnet, daß:

- das Ausgangssignal der Vorrichtung mit einem viele Komponenten enthaltenden Bezugssignal mit mindestens einer bekannten Komponente mit einer Frequenz von L MHz, die innerhalb von N MHz jeder gewünschten Frequenz F MHz liegt, zusammengesetzt wird,

- die Werte der der Vorrichtung zugeführten Frequenzgrob- und -feinsteuersignale zur Bildung eines Ausgangssignals mit einer Frequenz auch innerhalb von N MHz der gewünschten Frequenz F MHz eingestellt werden,

- der Parameter des das Frequenzfeinsteuerelement (36) steuernden elektrischen Signales dann bis zum Detektieren eines Schwebungssignales eingestellt wird, an welchem Punkt die Vorrichtung kalibriert werden kann, da das Schwebungssignal eine Eins-zu-Eins-Beziehung des Ausgangssignales und der bekannten Bezugssignalkomponente L MHz anzeigt, und

- die Werte der Frequenzfeinsteuersignale, bei denen Schwebungssignale detektiert werden, zu Kalibrierungszwecken gespeichert werden,

- wobei unter Verwendung eines Algorithmus oder einer Nachschlagtabelle der Wert des von dem Frequenzfeinsteuerelement zum Verschieben der Frequenz der Vorrichtung um (F-L) MHz benötigten Korrektursignales bestimmt werden kann und ein Ausgangssignal von F MHz unter Verwendung der gespeicherten Kalibrierungswerte der Steuersignale für L MHz und durch Zugabe des Korrektursignales zu dem gespeicherten Feinfrequenzsignal und Verwendung des kombinierten Signales als das Frequenzfeinsteuersignal für die Vorrichtung erzielt werden kann.


 
2. Ein Verfahren nach Anspruch 1, wobei der Kalibrierungsvorgang und das Verschieben der Frequenz, die Schwebungssignaldetektierung, die Signalspeicherung und -zugabe unter der Steuerung eines Mikroprozessors erfolgt.
 
3. Eine Signalgeneratorvorrichtung, deren Ausgangsfrequenz auf eine Frequenz F einzustellen ist, mit einem Hauptoszillator (10) mit einem Ausgang, an dem ein Rundfunkfrequenzsignal bei Betrieb des Oszillators erscheint und mit dem ein eine große Bandbreite aufweisendes und ein eine kleine Bandbreite aufweisendes Frequenzsteuerelement zusammenwirken, wodurch lineare Änderungen in der Ausgangsfrequenz über dem schmalen Frequenzband durch Bewirken von entsprechenden Änderungen in einem Parameter eines ihm zugeführten elektrischen Signales erreicht werden können, gekennzeichnet durch:

(1) ein Regelsystem zum Erzeugen von elektrischen Signalen aus in das System eingegebener Information zum Regeln der Frequenz des Hauptoszillators,

(2) Mittel zum Ableiten eines Abfragesignales vom Ausgang des Hauptoszillators,

(3) eine oszillatorische Signalquelle (42) mit stabiler fester Frequenz zum Erzeugen eines Bezugssignales F(ref),

(4) Schaltmittel (44, 46) zum Erzeugen eines harmonischen Spektrums oder "Kammes" von Signalen F(ref); 2F(ref); 3F(ref) ... n.F(ref) (genannt Signal mit harmonischem Spektrum), wobei sich mindestens eine Komponente des Spektrums in dem kleinen Frequenzband von F befindet, aus dem Bezugssignal F(ref),

(5) ein Misch- oder Abfrageschaltmittel (40) zum Kombinieren des abgefragten Signales mit dem Signal mit harmonischem Spektrum zum Erzeugen von Schwebungssignalen, das heißt Signalen mit Frequenzen, die unter anderem gleich der arithmetischen Differenz zwischen der Frequenz des Abfragesignales und der Komponente in dem Signal mit harmonischem Spektrum sind, und

(6) ein Schwebungssignaldetektorschaltmittel (48, 50, 52), das auf das Ausgangssignal des Mischschaltmittels anspricht und das Auftreten eines Schwebungssignalimpulses identifiziert, und
   die Anordnung der folgenden, der Frequenzkalibrierung dienenden Elemente:
   ein programmiertes Regelsystem zum Ändern der den Abstimmsteuerungen des Hauptoszillators zugeführten Frequenzsteuersignalen bis zum Erzeugen eines durch das Zusammenwirken des Ausgangssignales des Hauptoszillators und einer Komponente N.F(ref) des Signals mit harmonischem Spektrum bewirkten Schwebungssignales, Mittel zum Detektieren eines Schwebungssignales, an welchem Punkt die Werte der dem Hauptoszillator zugeführten Frequenzsteuersignale zum Erzeugen einer Frequenz von N.F(ref) bekannt sind, und Mittel zum Speichern eines Algorithmus oder einer Nachschlagetabelle, die die Frequenzabhängigkeit des Hauptoszillators zum Steuern der dessen Frequenzsteuerelementen zugeführten Signale beschreibt,
   wobei das programmierte Steuermittel ein Mittel zum Errechnen neuer Werte für die dem das schmale Band aufweisenden Frequenzsteuerelement zugeführten Steuersignale enthält unter Verwendung des Algorithmus oder der Nachschlagetabelle und der Werte der Frequenzsteuersignale, die die detektierte Schwebungsfrequenz mit dem N.F.(ref)-Signal erzeugen, wobei die neuen Werte bewirken, daß sich der Hauptoszillator in der Frequenz von N.F(ref) zur Sollfrequenz F verschiebt.


 
4. Ein Verfahren zum Steuern der Schwingungsfrequenz eines Hauptoszillators in einer Signalerzeugungsvorrichtung, in der ein auf ein Steuersignal ansprechendes lineares Frequenzsteuerelement (36) eine begrenzte Frequenzdurchlauffähigkeit aufweist, gekennzeichnet durch die folgenden Stufen:

(1) Erzeugen von Frequenzsteuersignalen, die am Ausgang des Hauptoszillators ein Signal erzeugen, das, falls es F nicht gleich ist, dicht bei diesem liegt, und Anlegen dieses Signales an den Oszillator,

(2) Kombinieren einer Probe des Ausgangssignales des Hauptoszillators mit einem Bezugssignal mit einer Komponente, die ausreichend eng an der Sollfrequenz F liegt, um innerhalb des begrenzten Durchlaufbereiches der Frequenz F der Schwingung des Hauptoszillators zu sein,

(3) Einstellen des Wertes des der linearen Frequenzsteuerung zugeführten Signales, bis ein Schwebungssignal zwischen dem Ausgangssignal des Hauptoszillators und der Bezugssignalkomponente festgestellt wurde, und

(4) Einstellen des Wertes des Steuersignales für das lineare Frequenzsteuerelement aus dem Wert, der dem Wert entspricht, an dem das Schwebungssignal auf einen neuen errechneten Wert detektiert ist unter Verwendung eines Algorithmus oder einer Nachschlagetabelle bezüglich der Frequenzabhängigkeit des Hauptoszillators gegenüber den Werten der für diesen vorgesehenen Frequenzsteuersignale, um das Ausgangssignal des Hauptoszillators auf die Sollfrequenz F zu verschieben.


 
5. Ein Verfahren nach Anspruch 4, wobei bei Anrufen des Hauptoszillators zu einem Durchlaufen durch einen Frequenzbereich das Verfahren durch die folgenden Schritte gekennzeichnet ist:

(1) Verändern des errechneten Steuersignales unter Verwendung des korrigierten Steuersignales als Ausgangspunkt, wobei die Veränderung in Übereinstimmung mit einem die Schwingungsfrequenz mit dem Wert des Steuersignales verbindenden Algorithmus erfolgt,

(2) bei Erreichen der endgültigen Zielfrequenz des Durchlaufes anschließend der Ausgang des Signalgenerators gesperrt wird und

(3) anschließend der Korrekturvorgang unter Einschluß des vorstehend erwähnten Verfahrens wiederholt wird, bis wieder ein Schwebungssignal detektiert wird, worauf der Durchlaufvorgang wieder ausgelöst werden kann.


 
6. Ein Verfahren nach Anspruch 5, dadurch gekennzeichnet, daß das Bezugssignal ein Signal mit einem harmonischen Spektrum ist, und gekennzeichnet durch

(1) Identifizieren einer Folge von Schlüsselfrequenzen in dem zu durchlaufenden Bereich und Beginnen mit entweder niedrigsten oder höchsten, Durchführen von Korrekturen an dem dem Hauptoszillator zugeführten Steuersignal bis zum Erzeugen eines Schwebungssignales durch das Zusammenwirken des Ausgangssignales des Hauptoszillators und einer Komponente des Bezugssignales,

(2) Modifizieren des korrigierten Steuersignales nach Maßgabe des bekannten Algorithmus unter Erzeugen eines Steuersignales zum Erzielen von Frequenzen zwischen der ersten Frequenz und der nächsten Zielfrequenz,

(3) bei Annäherung an die nächste Zielfrequenz Wiederholen des Kalibrierungsvorganges für das Steuersignal des Oszillators vor einer Wiederholung der Änderung der Frequenz des Oszillators über dem nächsten Frequenzbereich bis zur nächsten Zielfrequenz.


 
7. Eine Signalerzeugungsvorrichtung oder Verfahren zum Betreiben dieser Vorrichtung gemäß irgendeinem der vorhergehenden Ansprüche, gekennzeichnet durch einen zum Steuern der Signalgeneratorvorrichtung oder zum Ausführen des Verfahrens geeigneten Mikroprozessor, und wobei digitale Signale durch den Mikroprozessor erzeugt und Digital/Analogwandler (DAC's) (34, 36, 38) zum Wandeln der digitalen Signale in Spannungen oder Ströme, die zum Steuern der Frequenz des Hauptoszillators verwandt werden können, dienen.
 
8. Eine Signalgeneratorvorrichtung oder Verfahren gemäß irgendeinem vorhergehenden Anspruch, dadurch gekennzeichnet, daß die Auswahl des Schwebungssignales mittels eines auf den Durchgang von Signalen im Bereich von Gleichspannung bis f eingestellten Tiefpaßfilters (48) erreicht wird, wobei f in einem typischen Fall in dem Bereich von 500 kHz bis 5 MHz liegt, und das ein Signalverstärkermittel (50) und ein Impulsformerschaltungsmittel (52) nach dem Tiefpaßfilter und vor dem Mikroprozessor vorgesehen ist.
 
9. Eine Signalgeneratorvorrichtung oder Verfahren nach irgendeinem vorhergehenden Anspruch, gekennzeichnet durch einen zum Steuern der Signalgeneratorvorrichtung oder zum Durchführen des Verfahrens und auch zum Bestimmen der genauen Mittelstellung des ausgewählten Schwebungssignalimpulses aus der Breite des Schwebungssignalimpulses geeigneten Mikroprozessor, wobei der ausgewählte Schwebungssignalimpuls der Nullfrequenz oder dem Gleichspannungsgehalt des Schwebungssignals entspricht, und der Mikroprozessor auf das Heraussuchen der Mittelstellung jedes von ihm erkannten Schwebungssignalimpulses programmiert ist und zum Verwenden der ermittelten Mittelstellung des Impulses zum Ausrichten des diesem entsprechenden Wertes des die Frequenz steuernden Signales.
 
10. Eine Signalgeneratorvorrichtung oder ein Verfahren mit einer Mikroprozessorsteuerung gemäß irgendeinem vorhergehenden Anspruch, dadurch gekennzeichnet, daß zum Betrieb im Durchlaufmodus, das heißt wo die Generatorvorrichtung ein Signal erzeugt, dessen Frequenz sich über der Zeit von einer ein durchlaufenes Band bestimmenden ersten Frequenz (f1) bis zu einer zweiten Frequenz (f2) verändert, wobei zwei Informationsteile in einen mit dem Mikroprozessor zusammenwirkenden Speicher eingegeben werden, nämlich:

(a) die Durchlaufbreite (das heißt F2 - F1) und

(b) der Mittelpunkt des durchlaufenen Bereiches, das heißt 1/2(F2 + F1), und wobei der Anfangspunkt des durchlaufenen Bereiches mit den folgenden Stufen ermittelt wird:

(1) ein Mikroprozessor wird von der Information bezüglich der Durchlaufbreite und des Mittenbereiches so programmiert, daß er ein Steuersignal errechnet, so daß das von dem Mikroprozessor angestoßene Digital/Analogwandlermittel, DAC, ein oder mehrere Analogsignale erzeugt, die theoretisch bewirken sollten, daß der Hauptoszillator die Startfrequenz erzeugt,

(2) gleichzeitig ein Fehler DAC, dessen Ausgang mit dem zuerst erwähnten DAC-Mittel zusammengeschaltet wird, auf den Mittenbereich gesetzt wird,

(3) in dem Fehlersignal dann durch den Mikroprozessor eine Korrektur erzeugt wird, um das Ausgangssignal vom Fehler DAC bis zum Erkennen eines Schwebungs- oder Differenzsignales zu ändern,

(4) die zum Erzeugen des Schwebungssignalimpulses erforderliche Gesamtkorrektur für den Wert des Fehlersignales in einem Pufferspeicher für eine sich anschließende Bezugnahme gespeichert wird,

(5) eine Einstellung in den dem Hauptoszillator zugeführten Steuersignalen nach Maßgabe der Frequenz/Steuersignalcharakteristik des Hauptoszillators unter Verwendung der in dem Puffer als Ausgangspunkt gespeicherten Werte zum Erzielen einer neuen Betriebsfrequenz des Hauptoszillators entsprechend der Startfrequenz (F1) des Durchlaufs bewirkt wird,

(6) durch den Mikroprozessor ein Durchlauf unter Erzeugung eines sich verändernden Ausgangssignales bewirkt wird, das an das Frequenzsteuerelement des Hauptoszillators angelegt wird, so daß der gewünschte Durchlauf in der Ausgangsfrequenz von f1 bis f2 erzeugt wird.


 




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