(19)
(11)EP 1 626 506 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
31.05.2017 Bulletin 2017/22

(21)Application number: 05107487.0

(22)Date of filing:  15.08.2005
(51)International Patent Classification (IPC): 
H03M 13/11(2006.01)

(54)

Simplified LPDC encoding for digital communications

Vereinfachte LDPC Kodierung für digitale Kommunikation

Codage de LDPC simplifié pour la communication digitale


(84)Designated Contracting States:
DE FR GB

(30)Priority: 13.08.2004 US 601602 P
29.07.2005 US 703920 P
10.08.2005 US 201391

(43)Date of publication of application:
15.02.2006 Bulletin 2006/07

(73)Proprietor: TEXAS INSTRUMENTS INC.
Dallas, Texas 75265 (US)

(72)Inventor:
  • Hocevar, Dale E.
    Plano, TX 75074 (US)

(74)Representative: Zeller, Andreas et al
Texas Instruments Deutschland GmbH Haggertystraße 1
85356 Freising
85356 Freising (DE)


(56)References cited: : 
EP-A- 1 443 656
US-A1- 2004 148 560
EP-A- 1 511 177
  
  • HOCEVAR D E ED - INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS: "Efficient encoding for a family of quasi-cyclic LDPC codes" GLOBECOM'03. 2003 - IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE. CONFERENCE PROCEEDINGS. SAN FRANCISCO, DEC. 1 - 5, 2003, IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE, NEW YORK, NY : IEEE, US, vol. VOL. 7 OF 7, 1 December 2003 (2003-12-01), pages 3996-4000, XP010677362 ISBN: 0-7803-7974-8
  • TONG ZHANG ET AL: "VLSI implementation-oriented (3, k)-regular low-density parity-check codes" SIGNAL PROCESSING SYSTEMS, 2001 IEEE WORKSHOP ON 26-28 SEPT. 2001, PISCATAWAY, NJ, USA,IEEE, 26 September 2001 (2001-09-26), pages 25-36, XP010562749 ISBN: 0-7803-7145-3
  • RICHARDSON T J ET AL: "Efficient encoding of low-density parity-check codes" IEEE TRANSACTIONS ON INFORMATION THEORY, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 47, no. 2, February 2001 (2001-02), pages 638-656, XP002965294 ISSN: 0018-9448
  • LI PING ET AL: "Low density parity check codes with semi-random parity check matrix" ELECTRONICS LETTERS, IEE STEVENAGE, GB, vol. 35, no. 1, 7 January 1999 (1999-01-07), pages 38-39, XP006011650 ISSN: 0013-5194
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

FIELD OF THE INVENTION



[0001] This invention is in the field of data communications, and is more specifically directed to redundant coding for error detection and correction in such communications.

BACKGROUND OF THE INVENTION



[0002] High-speed data communications, for example in providing high-speed Internet access, is now a widespread utility for many businesses, schools, and homes. In its current stage of development, this access is provided according to an array of technologies. Data communications are carried out over existing telephone lines, with relatively slow data rates provided by voice band modems (e.g., according to the current v.92 communications standards), and higher data rates provided by Digital Subscriber Line (DSL) technology. Another current technology involves the use of cable modems communicating over coaxial cable, often in combination with cable television services. The Integrated Services Digital Network (ISDN) is a system of digital phone connections over which data is transmitted simultaneously across the world using end-to-end digital connectivity. Localized wireless network connectivity according to the IEEE 802.11 standard has become popular for connecting computer workstations and portable computers to a local area network (LAN), and typically through the LAN to the Internet. Broadband wireless data communication technologies, for example those technologies preferred to as "WiMAX" and "WiBro", and those technologies according to the IEEE 802.16d/e standards, are now being developed to provide wireless DSL-like connectivity in the Metro Area Network (MAN) and Wide Area Network (WAN) context.

[0003] A problem that is common to all data communications technologies is the corruption of data by noise. As is fundamental in the art, the signal-to-noise ratio for a communications channel is a degree of goodness of the communications carried out over that channel, as it conveys the relative strength of the signal that carries the data (as attenuated over distance and time), to the noise present on that channel. These factors relate directly to the likelihood that a data bit or symbol as received is in error relative to the data bit or symbol as transmitted. This likelihood is reflected by the error probability for the communications over the channel, commonly expressed as the Bit Error Rate (BER) ratio of errored bits to total bits transmitted. In short, the likelihood of error in data communications must be considered in developing a communications technology. Techniques for detecting and correcting errors in the communicated data must be incorporated for the communications technology to be useful.

[0004] Error detection and correction techniques are typically implemented by the technique of redundant coding. In general, redundant coding inserts data bits into the transmitted data stream that do not add any additional information, but that indicate, on decoding, whether an error is present in the received data stream. More complex codes provide the ability to deduce the true transmitted data from a received data stream even if errors are present.

[0005] Many types of redundant codes that provide error correction have been developed. One type of code simply repeats the transmission, for example repeating the payload twice, so that the receiver deduces the transmitted data by applying a decoder that determines the majority vote of the three transmissions for each bit. Of course, this simple redundant approach does not necessarily correct every error, but greatly reduces the payload data rate. In this example, a predictable likelihood remains that two of three bits are in error, resulting in an erroneous majority vote despite the useful data rate having been reduced to one-third. More efficient approaches, such as Hamming codes, have been developed toward the goal of reducing the error rate while maximizing the data rate.

[0006] The well-known Shannon limit provides a theoretical bound on the optimization of decoder error as a function of data rate. The Shannon limit provides a metric against which codes can be compared, both in the absolute and relative to one another. Since the time of the Shannon proof, modem data correction codes have been developed to more closely approach the theoretical limit. An important class of these conventional codes includes the "turbo" codes, which encode the data stream by applying two convolutional encoders. One of these convolutional encoders encodes the datastream as given, while the other encodes a pseudo-randomly interleaved version of the data stream. The results from the two encoders are interwoven to produce the encoded data stream.

[0007] Another class of known redundant codes are the Low Density Parity Check (LDPC) codes. The fundamental paper describing these codes is Gallager, "Low-Density Parity-Check Codes", (MIT Press, 1963), monograph available at http://www.inference.phy.cam.ac.uk/mackay/gallager/papers/. In these codes, a sparse matrix H defines the code, with the encodings c of the payload data satisfying:

over Galois field GF(2). Each encoding c consists of the source message ci combined with the corresponding parity check bits cp for that source message ci. The encodings c are transmitted, with the receiving network element receiving a signal vector r = c+ n, n being the noise added by the channel. Because the decoder at the receiver also knows matrix H, it can compute a vector z = Hr. However, because r = c+ n, and because Hc = 0:



[0008] The decoding process thus involves finding the most sparse vector x that satisfies:

over GF(2). This vector x becomes the best guess for noise vector n, which can be subtracted from the received signal vector r to recover encodings c, from which the original source message ci is recoverable.

[0009] There are many known implementations of LDPC codes. Some of these LDPC codes have been described as providing code performance that approaches the Shannon limit, as described in MacKay et al., "Comparison of Constructions of Irregular Gallager Codes", Trans. Comm., Vol. 47, No. 10 (IEEE, Oct. 1999), pp. 1449-54, and in Tanner et al., "A Class of Group-Structured LDPC Codes", ISTCA-2001 Proc. (Ambleside, England, 2001).

[0010] In theory, the encoding of data words according to an LDPC code is straightforward. Given enough memory or small enough data words, one can store all possible code words in a lookup table, and look up the code word in the table according to the data word to be transmitted. But modern data words to be encoded are on the order of 1 kbits and larger, rendering lookup tables prohibitively large and cumbersome. Accordingly, algorithms have been developed that derive codewords, in real time, from the data words to be transmitted. A straightforward approach for generating a codeword is to consider the n-bit codeword vector c in its systematic form, having a data or information portion ci and an m-bit parity portion cp such that c = (ci | cp). Similarly, parity matrix H is placed into a systematic form Hsys, preferably in a lower triangular form for the m parity bits. In this conventional encoder, the information portion ci is filled with n-m information bits, and the m parity bits are derived by back-substitution with the systematic parity matrix Hsys. This approach is described in Richardson and Urbanke, "Efficient Encoding of Low-Density Parity-Check Codes", IEEE Trans. on Information Theory, Vol. 47, No. 2 (Feb. 2001), pp. 638-656. This article indicates that, through matrix manipulation, the encoding of LDPC. codewords can be accomplished in a number of operations that approaches a linear relationship with the size n of the codewords. However, the computational efficiency in this and other conventional LDPC encoding techniques does not necessarily translate into an efficient encoder hardware architecture. Specifically, these and other conventional encoder architectures are inefficient because the typically involve the storing of inverse matrices, by way of which the parity check of equation (1), or a corollary, is solved in the encoding operation.

[0011] By way of further background, my copending patent application U.S. Serial No. 10/329,597, filed December 26, 2002, now published as U.S. Patent Publication No. US 2004/0034828 A1, and my copending patent application U.S. Serial No. 10/806,879, filed March 23, 2004, and now published as U.S. Patent Publication No. US 2004/0194007 A1, both commonly assigned herewith, describe a family of structured irregular LDPC codes, and decoding architectures for those codes. The quasi-cyclic structure of this family of LDPC codes can also provide efficiencies in the hardware implementation of the encoder, as described in my copending patent application U.S. Serial No. 10/724,280, filed November 28, 2003, now published as U.S. Patent Publication No. US 2004/0148560 A1, commonly assigned herewith. The encoder and encoding method that are described in U.S. Patent Publication No. US 2004/0148560 A1 follow a generalized approach, and are capable of handling such complications as row rank deficiency.

SUMMARY OF THE INVENTION



[0012] It is an object of this invention to provide a simplified approach to the encoding of information words using structured Low Density Parity Check (LDPC) codes.

[0013] It is a further object of this invention to provide efficient encoder circuitry for following this simplified encoding approach.

[0014] It is a further object of this invention to provide such encoder circuitry that may be in the form of a programmed microprocessor or digital signal processor.

[0015] It is a further object of this invention to provide such an encoding approach that is well-suited for high data rate applications such as wireless broadband communication.

[0016] Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.

[0017] The present invention resides in a method of encoding code words and an encoder as set out in the appended claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS



[0018] 

FIG. 1 is a functional block diagram of communications between two OFDM transceivers, where at least the transmitting transceiver is constructed according to a first preferred embodiment of the invention.

FIG. 2 is an electrical diagram, in block form, of a transceiver constructed according to the preferred embodiments of the invention.

FIG. 3 is an illustration of an example of a macro parity check matrix representation of an LDPC code suitable for use in connection with the preferred embodiment of the invention.

FIG. 4 is a flow diagram illustrating the operation of the encoding method according to the preferred embodiment of the invention.

FIG. 5 is an illustration of the solution of the parity portion of a coding, using the code illustrated in FIG. 3 and following a recursion path within the parity portion of the macro parity check matrix.

FIG. 6 is an electrical diagram, in block form, of encoder circuitry in the transceiver of FIG. 2, constructed according to the preferred embodiment of the invention.

FIG. 7 is an electrical diagram, in block form, of a cyclic multiply unit in the encoder of FIG. 6, constructed according to the preferred embodiment of the invention.


DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION



[0019] The present invention will be described in connection with an example of its implementation in an exemplary transceiver, for example a wireless broadband network adapter such as according to the IEEE 802.16 wireless broadband standards. It will be apparent to those skilled in the art having reference to this specification that this invention is particularlywell-suited for use in such an application. However, it is also contemplated that this invention will be of similar benefit in many other applications that involve error correction coding, including other types of communications and different media, including other wireless communications such as wireless telephony, and wireless Local Area Network (LAN) communications, such as contemplated according to the IEEE 802.11 a/b/g standards; this invention is also contemplated to be beneficial for error correction coding in wired data communications such as involved in conventional Digital Subscriber Line (DSL) broadband communications, cable modem broadband access, wired LAN communications, and even data communications within a single computer system (e.g., error correction as applied to disk drive access). In the communications context, this invention can be used in communications carried out using a wide range of modulation techniques, including single-carrier modulation, and multicarrier modulation approaches such as orthogonal frequency division multiplexing (OFDM) and discrete multitone modulation (DMT). It is therefore to be understood that these and other alternatives to and variations on the embodiment described below are contemplated to be within the scope of this invention as claimed.

[0020] FIG. 1 functionally illustrates an example of a somewhat generalized communication system into which the preferred embodiment of the invention is implemented in connection with a wireless broadband communications environment, such as contemplated by the IEEE 802.16 wireless broadband standard. As mentioned above, it is of course contemplated that this generalized arrangement is provided by way of context only. In the system of FIG. 1, only one direction of transmission (from transmitting transceiver 10 over transmission channel C to receiving transceiver 20) is illustrated. It will of course be understood by those skilled in the art that data will also be communicated in the opposite direction, with transceiver 20 as the transmitting transceiver and transceiver 10 as the receiving transceiver. Typically, this reverse communication will be carried out in a similar manner as the "forward" direction communication, but multiplexed in either frequency or time to avoid interference.

[0021] As shown in FIG. 1, transmitting transceiver 10 receives an input bitstream that is to be transmitted to receiving transceiver 20. The input bitstream may be generated by a computer at the same location (e.g., the central office) as transmitting transceiver 10, or alternatively and more likely is generated by a computer network, in the Internet sense, that is coupled to transmitting transceiver 10. Typically, this input bitstream is a serial stream of binary digits, in the appropriate format as produced by the data source.

[0022] According to this embodiment of the invention, LDPC encoder function 11 digitally encodes the input bitstream for error detection and correction purposes. According to this embodiment of the invention, a redundant LDPC code is applied by encoder function 11, with the particular code selected to facilitate implementation and performance of LDPC encoder function 11, as will be apparent from the following description. The specifics of the code will become apparent from the description of this encoder function, presented below relative to the description of the construction and operation of transmitting transceiver 10 according to the preferred embodiment of the invention. In general, the coded bits include both the payload data bits and also code bits that are selected, based on the payload bits, so that the application of the codeword (payload plus code bits) to the sparse LDPC parity check matrix equals zero for each parity check row. After application of the LDPC code, bit to symbol encoder function 12 groups the incoming bits into symbols that modulate one or more carrier frequencies in the eventual broadband transmission.

[0023] FIG. 2 illustrates an exemplary construction of transmitting transceiver 10, in the form of a wireless broadband network adapter. Transceiver 10 is coupled to host system 30 by way of a corresponding bus B. Host system 30 corresponds to a personal computer, a laptop computer, or any sort of computing device capable of wireless broadband communications, in the context of a wireless wide area network (WAN) or "metro" area network ("MAN"); of course, the particulars of host system 30 will very with the particular application. In the example of FIG. 2, transceiver 10 may correspond to a built-in broadband, wireless adapter that is physically realized within its corresponding host system 30, to an adapter card installable within host system 30, or to an external card or adapter coupled to host computer 30. The particular protocol and physical arrangement of bus B will, of course, depend upon the form factor and specific realization of transceiver 20. Examples of suitable buses for bus B include PCI, MiniPCI, USB, CardBus, and the like.

[0024] Transceiver 10 in this example includes spread spectrum processor 31, which is bidirectionally coupled to bus B on one side, and to radio frequency (RF) circuitry 33 on its other side. RF circuitry 33, which may be realized by conventional RF circuitry known in the art, performs the analog demodulation, amplification, and filtering of RF signals received over the wireless channel and the analog modulation, amplification, arid filtering of RF signals to be transmitted by transceiver 10 over the wireless channel, both via antenna A. The architecture of spread spectrum processor 31 into which this embodiment of the invention can be implemented follows that of the TNETW1130 single-chip media access controller (MAC) and baseband processor available from Texas Instruments Incorporated, by way of example, and that corresponds to a wireless LAN realization at customer premises equipment. It is contemplated that the architecture of other transceiver installations, including for wireless broadband communications, whether on the network or client side, can follow a similar generic approach, as modified for the particular application location, as known in the art. This exemplary architecture includes embedded central processing unit (CPU) 36, for example realized as a reduced instruction set (RISC) processor, for managing high level control functions within spread-spectrum processor 31. For example, embedded CPU 36 manages host interface 34 to directly support the appropriate physical interface to bus B and host system 30. Local RAM 32 is available to embedded CPU 36 and other functions in spread spectrum processor 31 for code execution and data buffering. Medium access controller (MAC) 37 and baseband processor 39 are also implemented within spread-spectrum processor 31 according to the preferred embodiments of the invention, for generating the appropriate packets for wireless communication, and providing encryption, decryption, and wired equivalent privacy (WEP) functionality. Program memory 35 is provided within transceiver 10, for example in the form of electrically erasable/programmable read-only memory (EEPROM), to store the sequences of operating instructions executable by spread-spectrum processor 31, including the coding and decoding sequences according to the preferred embodiments of the invention, which will be described in further detail below. Also included within transceiver 10, in the form of a wireless adapter, are other typical support circuitry and functions that are not shown, but that are useful in connection with the particular operation of transceiver 20.

[0025] According to the preferred embodiments of the invention, LDPC encoding is embodied in specific custom architecture hardware associated with baseband processor 39, and shown as LDPC encoder circuitry 38 in FIG. 2. LDPC encoding circuitry 38 is custom circuitry for performing the coding of transmitted and data packets according to the preferred embodiments of the invention. A preferred embodiment of the particular construction of LDPC encoder circuitry 38 according to the preferred embodiment of this invention will be described in further detail below.

[0026] Alternatively, it is contemplated that baseband processor 39 itself, or other computational devices within transceiver 20, may have sufficient computational capacity and performance to implement the encoding functions described below in software, specifically by executing a sequence of program instructions. It is contemplated that those skilled in the art having reference to this specification will be readily able to construct such a software approach, for those implementations in which the processing resources are capable of timely performing such encoding.

[0027] In either case, referring back to FIG. 1, the encoded symbols are then applied to modulator 14, which generates a datastream according to the particular modulation technique for the communications protocol. The particular modulation applied by modulator 14 may be a single carrier modulation, as used according to some of the options under the IEEE 802.16 wireless broadband standards. Alternatively, modulator 14 may be a multiple-carrier modulator, as used in OFDM modulation contemplated for certain IEEE 802.16 wireless broadband modes, or as used in Discrete Multitone modulation (DMT) for conventional DSL communications. In the case of multiple-carrier modulation, modulator 14 will apply an inverse Discrete Fourier Transform (IDFT) function to the output of encoder 12, to associate each input symbol with one subchannel in the transmission frequency band, and to generate a corresponding number of time domain symbol samples according to the Fourier transform. In any case, to the extent that modulator 14 generates multiple time domain symbol samples, this datastream is converted into a serial stream of samples by parallel-to-serial converter 16. In the single carrier example, functions 11 through 16 convert the input bitstream into a sequence of complex amplitudes (e.g., according to a QAM constellation) corresponding to the symbol values. In the multiple carrier implementation, functions 11 through 16 will convert the input bitstream into a serial sequence of symbol values representative of the sum of a number of modulated subchannel carrier frequencies, the modulation indicative of the various data values, and including the appropriate redundant code bits for error correction. Those skilled in the art having reference to this specification will readily recognize that each of functions 11 through 16 may be carried out, and preferably actually are carried out, as digital operations executed by a digital signal processor (DSP).

[0028] Filtering and conversion function 18 then processes the datastream for transmission. Function 18 applies the appropriate-digital filtering operations, such as interpolation to increase sample rate and digital low pass filter for removing image components, for the transmission. The digitally-filtered datastream signal is then converted into the analog domain and the appropriate analog filtering is then applied to the output analog signal, prior to its transmission.

[0029] The output of filter and conversion function 18 is then applied to transmission channel C, for forwarding to receiving transceiver 20. The transmission channel C will of course depend upon the type of communications being carried out. In the wireless communications context, the channel will be the particular environment through which the wireless broadband or LAN transmission takes place. Alternatively, in the DSL context, the transmission channel is physically realized by conventional twisted-pair wire. In any case, transmission channel C adds significant distortion and noise to the transmitted analog signal, which can be characterized in the form of a channel impulse response.

[0030] This transmitted signal is received by receiving transceiver 20, which, in general, reverses the processes of transmitting transceiver 10 to recover the information of the input bitstream. Filtering and conversion function 21 in receiving transceiver 20 processes the signal that is received over transmission channel C. Function 21 applies the appropriate analog filtering, analog-to-digital conversion, and digital filtering to the received signals, again depending upon the technology of the communications. In the DSL context, this filtering can also include the application of a time domain equalizer (TEQ) to effectively shorten the length of the impulse response of the transmission channel C. Serial-to-parallel converter 23 converts the filtered datastream into a number of samples that are applied to demodulator function 24. In the single channel example, demodulator function 24 will convert the received amplitude (typically complex) into a digital symbol value, while in the multiple channel example, demodulator function 24 applies a Discrete Fourier Transform (DFT) to recover the modulating symbols at each of the subchannel frequencies, reversing the IDFT performed by modulator 14 in transmitting transceiver 10. In either case, demodulator 24 outputs a frequency domain representation of a block of transmitted symbols, multiplied by the frequency-domain response of the effective transmission channel. Recovery function 25 then effectively divides out the frequency-domain response of the effective channel, for example by the application of a frequency domain equalizer (FEQ), to recover an estimate of the modulating symbols. Symbol-to-bit decoder function 26 then demaps the recovered symbols, and applies the resulting bits to LDPC decoder function 28.

[0031] LDPC decoder function 28 reverses the encoding that was applied in the transmission of the signal, to recover an output bitstream that corresponds to the input bitstream upon which the transmission was based. This output bitstream is then forwarded to the host workstation or other recipient. According to this preferred embodiment of the invention, a preferred architecture for LDPC decoder function 28 is described in above-mentioned copending patent application U.S. Serial No. 10/,329,597, filed December 26, 2002, now published as U.S. Patent Publication No. US 2004/0034828 A1, and my copending patent application U.S. Serial No. 10806,879, filed March 23, 2004, and now published as U.S. Patent Publication No. US 2004/0194007 A1, both commonly assigned herewith.

LDPC Encoding



[0032] The theory of operation of the preferred embodiment of the invention will now be described, following which its implementation into LDPC encoding function 11 in transceiver 10, in the form of LDPC encoder circuitry 38 operating in cooperation with baseband processor 39, will then be described.

[0033] By way of nomenclature, the LDPC code is fundamentally contained within an mxj parity check matrix H that satisfies the following equation, when multiplied by the true transmitted code word vector c:

over Galois Field (2). For a single one of the m rows in parity check matrix H, this parity check amounts to:

over GF(2). The example of the parity-check equation (5a) thus logically.. becomes, for an exemplary row of parity check matrix H having a "1" in its columns 1, 3, 4, and 7:



[0034] For systematic codes, such as the LDPC codes applied by LDPC encoder circuitry 38 according to this invention, code word vector c expressly contains an information portion ci, which presents the information bits or payload of the code word, and parity portion cp, which presents the parity check bits. For the example of an LDPC code of code rate 1:2, information portion ci and parity portion cp each constitute one-half of code word vector c.

[0035] Therefore, once the parity check matrix H is defined, and because the information bits ci of code word vector c are known, the process of encoding amounts to solving the parity check equation:

for the parity bits cp, where the matrices Hp and Hi correspond to the portions of parity check matrix H that are applied to the parity and information bits of code word vector c, respectively. Rewriting equation (6a), the encoding problem can be expressed as:

and solving for parity bits cp. In the general case, this solution requires the generation of an inverse matrix, namely the inverse of the parity matrix portion Hp. As known in the art, the calculations and memory requirements for such an operation, particularly for relatively large codewords as contemplated in modern communications, requires sufficient resources that this brute force approach to solving for parity portion cp for a given information portion ci is not efficient, especially in the hardware sense.

[0036] This encoding of a message frame can be executed in a straightforward if not brute force manner, using conventional programmable integrated circuits such as digital signal processors and the like. Examples of recent encoding techniques are described in Richardson and Urbanke, "Efficient Encoding of Low-Density Parity-Check Codes", IEEE Trans. on Information Theory, Vol. 47, No. 2 (Feb. 2001), pp. 638-656. However, as mentioned above, these conventional techniques do not lend themselves to efficient hardware realization. The encoders described in my copending patent application U.S. Serial No. 10/724,280, filed November 28, 2003, now published as U.S. Patent Publication No. US 2004/0148560 A1, commonly assigned herewith, take advantage of the quasi-cyclic structure of the family of LDPC codes described in U.S. Patent Publications No. US 2004/0034828 A1 and No. US 2004/0194007 A1 to arrive at substantial efficiencies in the encoding process and hardware.

[0037] FIG. 3 illustrates an example of a macro parity check matrix HM, which represents an LDPC parity check matrix H. Macro parity check matrix HM illustrates that parity check matrix H has a column and row block structure in which each matrix entry represents a submatrix block that, according to this invention, is a pxp submatrix. In this example, therefore, because macro parity check matrix HM has twenty-four block columns and twelve block rows, the full parity check matrix H has 24p columns and 12p rows. In this representation of FIG. 3, each "1" entry in macro parity check matrix HM indicates that the corresponding pxp submatrix, or block, is a cyclically shifted identity matrix. Those entries of macro parity check matrix HM that are zero-valued (shown blank in FIG. 3, for clarity), correspond to a zero-valued block at that location. As evident from the representation of macro parity check matrix HM of FIG. 3, parity check matrix H is indeed a low density, or sparse, matrix. And in this example, the first twelve block columns (1 through 12) of macro parity check matrix HM correspond to parity matrix portion Hp of equations 6a and 6b, while the last twelve block columns (13 through 24) of macro parity check matrix HM correspond to the information matrix portion Hi of equations 6a and 6b. As such, the code represented by macro parity check matrix HM, in this example, has a code rate of 1:2.

[0038] In a general sense, encoding according to the preferred embodiment of the invention is based on the initial factoring of macro parity check matrix HM into a form, similar to that of FIG. 3, in which one block section of parity matrix portion Hp can be resolved from the product of information matrix portion Hi with the known information portion ci. Once this block section is solved, and its corresponding parity bits known, the encoding approach according to the preferred embodiment of the invention reverts to the original macro parity check matrix HM to recursively solve for the other parity bits.

[0039] In the example of FIG. 3, the solvable block portion of macro parity check matrix Hm is (or is arranged to be, by rearrangement of the columns) the twelfth block column. The first eleven block columns of macro parity check matrix HM each have a column weight of two and, over those first eleven block columns, each of the block rows have a row weight of two or less. The twelfth block column (i.e., the solvable block portion) need not fit these constraints, and in this example does not so fit (e.g., because it has a block column weight of three). It has been observed, according to this invention, that this structure of a macro parity check matrix HM is relatively common within the family of LDPC codes described in U.S. Patent Publication No. US 2004/0148560 A1, especially considering that the columns within the parity check matrix H can be freely rearranged, as known in the art. As will be evident from the following description, the positions and numbers of non-zero entries provide a recursion path by way of which the parity bits cp can be solved once the solvable block portion (e.g., the twelfth block column in FIG. 3) is solved, according to the preferred embodiment of the invention. It is contemplated that other arrangements of the non-zero entries and other matrix structures may also provide such a recursion path, permitting solution of the parity bits cp according to this invention.

[0040] Encoding of data in this manner, and according to the preferred embodiment of this invention, will now be described with reference to the generalized flow chart of FIG. 4.

[0041] According to the preferred embodiment of this invention, preparation for encoding (i.e., processing that is performed before receiving information bits ci that are to be encoded) includes cyclic factorization of parity check matrix H into a factored form Hf:

where submatrix B is a pxp submatrix (i.e., one column block by one row block), occupying the Jth block row and Jth block column position of factored parity check matrix Hf, J being the position of one of the block columns within parity matrix portion Hp and establishing the solvable column block portion described above. In this example, equation (7) illustrates that the block row containing Submatrix B is the bottom block row, but of course it will be understood that this block row, containing submatrix B and zero-valued entries for the remainder of the parity portion, can be at any selected block row position; the bottom block row position, of this example, tends to facilitate visualization of the solution process. This factoring corresponds to process 40 of FIG. 4. A description of the method of factoring a parity check matrix into a form such as that of equation (7) is provided in U.S. Patent Publication No. US 2004/0148560 A1. In this factored form, submatrix a is a submatrix of p columns (one column block) by (n-1)p rows (n being the number of row blocks in the corresponding macro parity check matrix HM). Submatrices HfiU and 4fiL correspond to factored upper and lower portions of information portion matrix Hi. Submatrix Hfp is the remaining factored portion of parity matrix portion Hp. All of the submatrices in factored parity check matrix Hf are block matrices, within which each entry (block) is a pxp cyclic matrix, with a weight that is not constrained to one as a result of the factoring operation. According to the preferred embodiment of this invention, submatrix B is an invertible cyclic matrix, and submatrix Hfp has a block upper triangular structure. These properties of factored parity check matrix Hf and its submatrices are attained by conventional row and column reordering, row factorization, and other operations as described in U.S. Patent Publication No. US 2004/0148560 A1, in combination with selection of the LDPC code from the family of codes that is also described in U.S. Patent Publication No. US 2004/0148560 A1. It is contemplated that those skilled in the art, having reference to this specification, will be readily able to select such a code, and apply the appropriate reordering and factoring, to derive such a factored parity check matrix Hf. The factoring of parity check matrix H in process 40 is, in practice, preferably accomplished prior to encoding (and, indeed, may be hardwired or pre-stored into the encoding hardware or software of the encoding transceiver), as these calculations are not dependent on the data being encoded.

[0042] Once factored parity check matrix Hf is established in this manner, encoding of data can commence. In process 42, an information word ci that is to be encoded is received by the encoder, which, in combination with the parity check matrix H (as factored in process 40) leaves only the parity bits cp as unknown. As discussed above, the encoding operation amounts to solving equation 6b:

or, using the conventional matrix mathematics nomenclature of a "right-hand side". RHS:



[0043] In a recursive solution approach, as used according to this embodiment of the invention, the right-hand side RHS will be updated as each parity section is solved, permitting solution for a next parity section from the "left-hand side". In process 44 of FIG. 4, the right-hand side RHS is computed, according to the preferred embodiment of the invention, preferably by a summation of a series of vector products, each product involving summed cyclic shifts, as described in U.S. Patent Publication No. US 2004/0148560 A1. In this calculation of the right-hand side values RHS based on the information bits ci only, it is the original (non-factored) parity check matrix Hi that is utilized.

[0044] The parity bits cp associated with the block column containing submatrix B of equation 7 are now solved. In general, this operation involves evaluation of:

to derive the matrix-vector product rJ, which is a vector of size p for the Jth (bottom) block row of the factored parity matrix Hf, which is performed in process 46 in this example For some cases in which the factorization is simple, vector rj can be computed by applying, to the right-hand side values RHS, the same factorization steps as used to produce factored parity check matrix portion HfiL from original information parity matrix portion Hi. This matrix vector product rJ is, of course, the product of submatrix B with the yet-unknown parity bits cp,J for the Jth block column. But, as mentioned above, submatrix B is an invertible cyclic matrix, and as such:



[0045] And because the inverse of a cyclic matrix is itself a cyclic matrix, submatrix B-1 is a cyclic matrix. The solution of equation 8b, performed in process 48 in this example, is therefore a sample calculation for digital circuitry. In process 50, these newly-solved parity bits cp,J are used to update the right-hand side values:

by adding, to the previous right-hand side value, the vector product of these newly-solved parity bits cp,J with the corresponding block Jth column (considering the non-zero entries in the entire block column, over all rows). Once the parity bits cp,J for the Jth block column are solved and the right-hand side values RHS updated, the recursive solution of the remaining parity bits begins, with process 52.

[0046] According to the preferred embodiment of this invention, the recursive solution for the remaining parity bits uses the original parity check matrix H rather than the factored parity check matrix Hf. The use of the original parity check matrix H takes advantage of the constrained block row and block column weights that establish the recursion path, as will be evident from this description, which will refer to FIG. 3 by way of example. Macro parity check matrix HM is a useful abstraction of original parity check matrix H, for purposes of this description.

[0047] In the first pass of process 52, parity bits cp,J for the Jth block are known from process 48. In the example of FIG. 3, parity bits Cp,J correspond to the parity bits cp,12 because J=12 in that example. Knowledge of parity bits cp,12 permits solution of the parity bits for block column 1, because both block column 12 and block column 1 have non-zero entries in block row 1, and because the row weight of block row 1 is one over the remaining eleven block columns in the parity portion Hp. Accordingly, this first pass of process 52 solves for parity bits cp,1 by solving:

where r1 is the contents, in block row 1, of the updated right-hand side value from process 50, including the results from the solution of parity bits cp,12 in process 48, and where P1,1-1 is the inverse of the block, or submatrix, represented by row 1 and column 1 of macro parity matrix HM. As described above, the LDPC code is selected, and parity matrix H is arranged, so that each submatrix such as P1,1 is a cyclically shifted identity matrix, the inverse of which (i.e., submatrix P1,1-1) is also a cyclically shifted identity matrix. The product on the right-hand side of equation 10a is thus a simple circular shift of the vector r1 from the updated right-hand side value. As a result of process 52, additional parity bits, namely parity bits cp,1 associated with block column 1 in this example, are determined for the eventual code word,c.

[0048] Decision 53 determines whether additional block columns remain, in macro parity matrix HM, for which the parity bits cp are still to be determined. If so (decision 53 is YES), process 50 is repeated to update the right-hand side value PHS:

for this example, in which the most recently solved parity bits were solved for block column 1, and for all non-zero entries in parity matrix block column Hp,1 (not just submatrix P1,1 for block column 1 and block row 1, as used in process 52).

[0049] The next instance of process 52 is then executed, for the remaining block column in parity matrix portion Hp having a remaining block row weight of one after removing the previously solved block column to the right-hand side. In the example of FIG. 3, the parity bits cp,1 associated with block column 1 are now solved and moved to the right-hand side values, and these values are linked into parity matrix portion Hp via block row 7. This knowledge of parity bits cp,1 thus leaves block column 11 as a remaining block column in parity matrix portion Hp with a block row of weight one, and as such, the next pass of process 52 computes:

r7 being the contents, in block row 7, of the updated right-hand side value and P7,11-1 being the inverse of the submatrix in block row 7 and column row 11 of macro parity matrix HM. Decision 53 again returns a YES result, and the right-hand side is updated in process 50:

using the most recently solved parity bits c11 for block column 11 and for the non-zero entries in parity matrix block column Hp,11. The remaining parity bits cp are solved in a similar manner, following the recursion path through parity matrix portion Hp established by its non-zero entries. For the example of FIG. 3, these subsequent iterations can be expressed by the following equations (each of which combine solution process 52 with the right-hand side update of the subsequent process 50):

where vector r12 is the updated right-hand side value, in block row 12, and showing the matrix product of submatrix P12,11 with the most recently solved parity bits c11 for block column 11. In fact, because the vector r for this block row is used only for this next iteration, the full set of right-hand side values RHS need not be updated. The remaining equations thus follow similarly:

















[0050] The recursion path corresponding to these equations, through exemplary macro parity matrix HM of FIG. 3, is illustrated in FIG. 5. The dashed boxes around particular ones of the entries highlight the inverse submatrix Pj,k-1 position at which the corresponding parity bits cp,k are solved in process 52.

[0051] The example of FIG. 3 also illustrates the existence of an alternative recursion path that may be followed in processes 50, 52 and decision 53 instead of, or in addition to, that shown in FIG. 5. As evident from FIG. 3, block row 2 in parity matrix portion Hp has a block row weight of one. Accordingly, the parity bits cp,2 can be solved directly from the right-hand side values (independent of the solving of parity bits cp,12 in this example) by:

following which a recursion path solving for parity bits cp,2, then parity bits cp,7, cp,3, cp,8, cp,4, cp,9, cp,5, cp,10, cp,6, cp,11, and cp,1 could be followed. This path is the reverse of the path shown in FIG. 5. If this alternative path is pursued solely, the solution of parity bits cp,J (J=12, in this example) by inversion of submatrix B is still required prior to solution for any block column that has a non-zero entry in the same block row in which block column J also has a non-zero entry (e.g., block column 3 in the example of FIG. 3). Further in the alternative, depending upon the computational capacity and hardware capability for the encoder, both paths may be followed simultaneously and in parallel, reducing the solution time by half.

[0052] Referring back to FIG. 4, upon the parity bits cp,j for the last unsolved block column being solved, decision 53 returns a NO result. Control then passes back to process 42, in which the information word to be encoded is received, following which the encoding process repeats from process 44.

[0053] Encoding of digital data for communication according to this preferred embodiment provides numerous important advantages, relative to conventional encoding techniques. In addition, by constraining the LDPC codes in the family of codes described in U.S. Patent Publication No. US 2004/0148560 A1, as described above in connection with this invention, the storage requirements for the description of the LDPC code can be much reduced (i.e., only the original parity check matrix need be stored for the parity portion, rather than both the original parity check matrix and its factored version), as can the amount of computation involved in the encoding process. Additionally, the encoding hardware or functionality requirements can also be substantially reduced, as will now be described relative to FIG. 6, which illustrates the construction of LDPC encoder circuitry 38 (FIG. 2) according to the preferred embodiment of the invention.

[0054] LDPC encoder circuitry 38 includes certain memory resources and computational units, all operating under the control of controller 100. Controller 100 is constructed in the conventional manner, for example as a control state machine, control ROM, or in another known arrangement, to control the operation of the various constituents of LDPC encoder circuitry 38 to effect the operations described herein. Specifically, it is contemplated that controller 100 can control the sequence of operations performed by LDPC encoder circuitry 38, including accessing of the various memory and register resources, and causing the operative logic circuitry to perform its particular functions upon the appropriate operands. It is contemplated that those skilled in the art having reference to this specification will be able to readily realize the construction of controller 100 to perform these functions, using conventional techniques.

[0055] On the input side, the memory resources in LDPC encoder circuitry 38 include matrix shift value memory 82, which stores the definition of the various shift values of the original parity check matrix H. As described above, because each non-zero block entry of the parity check matrix portion Hp (other than the Jth block column including submatrix B, or more properly its inverse B-1, which will typically have a weight greater than one) corresponds to a cyclically shifted identity matrix, each block will have a weight of one, and as such each entry in matrix shift value memory 82 need only store the shift position of the identity diagonal for its corresponding block. Information parity check matrix portion Hi can also be stored in matrix shift value memory 82, in this manner. In general, matrix shift value memory 82 will store both the shift values, and a weight value, associated with inverse submatrix B-1 and for the factored information check matrix portion Hf,iL. Certain codes may require even less information to be stored, for example if each non-zero submatrix has the same shift value, or if the shift values follow a pattern. In such cases, there may not even be express "storage" of the shift values, but rather the values and patterns may be expressed in controller logic. For the general case, the contents of memory 82 completely specifies parity check matrix H. Another input memory resource in LDPC encoder circuitry 38 is information bit vector memory 84, which receives and stores the information bits ci to be encoded.

[0056] Output and working memory resources in LDPC encoder circuitry 38 include right-hand side value memory 89, which stores the results of matrix multiplications between the information bit vector stored in memory 84 and the entries in parity check matrix H (generated in processes 44, 46 and updated in each iteration of process 50), and as will be described below. Parity bit memory 90 stores the resulting parity portion cp from the encoding process carried out by LDPC encoder circuitry 38.

[0057] The computational resources in LDPC encoder circuitry 38 include cyclic multiply unit 88, which effects many of the calculations involved in the encoding process, as will be described below.

[0058] The interconnection of these memory and computational resources within LDPC encoder circuitry 38 is illustrated in FIG. 6. As shown, matrix shift value memory 82 is connected to cyclic multiply unit 88. Cyclic multiply unit 88 also receives operands from information bit vector memory 84, right-hand side value memory 89, and parity bit memory 90, via multiplexer 86, which is controlled by controller 100 according to the operations being performed. Optionally, a direct connection from the output of cyclic multiply unit 88 may also be applied to another input of multiplexer 86 to directly feed subsequent calculations, as will be described below. The output of cyclic memory unit is coupled to right-hand side value memory 89, and also to parity bit memory 90. Of course, two or more memories 82, 84, 89, 90 may be combined with one another into a combined physical memory, or indeed all such memory resources may be realized within in a single physical memory. It is contemplated that the specific memory architecture may be selected according to the particular application of encoder 38, by the skilled artisan having reference to this specification.

[0059] Referring now to FIG. 7, the construction of cyclic multiply unit 88 will now be described in detail. This construction will also illustrate the operation of cyclic multiply unit 88 in the encoding process of FIG. 4 described above, and will illustrate the efficiency with which the encoding of LDPC codes is attained according to this preferred embodiment of the invention.

[0060] Cyclic multiply unit 88 includes circular shift unit 104, which is a circular shifter, or barrel shifter, that can receive p bits of a selected segment of information portion ci from information bit vector memory 84, or of a segment of information from another input source via multiplexer 86. The particular segment received by circular shift unit 104 is selected under the control of controller 100, and constitutes that portion to be operated upon by cyclic multiply unit 88, depending on the operation. Circular shift unit 104 can shift these received bits by a number of bit places from 0 to p-1 responsive to a shift value received from matrix shift value memory 82.

[0061] For purposes of evaluating matrix operations involving a cyclic submatrix having a weight greater than one (e.g., inverse submatrix B-1 as used in process 48, and the information portion of factored parity check matrix Hf as applied in process 46), the output of circular unit 104 is applied to one input of bitwise exclusive-OR function 106; the output of bitwise exclusive-OR function 106 is applied to the input of accumulator 108, and the output of accumulator 108 is applied as a second input to bitwise exclusive-OR function 106. Bitwise exclusive-OR function 106 is combinational logic for performing an exclusive-OR logic operation, bit-by-bit, on the data words received at its inputs. The output of accumulator 108 is applied to bitwise exclusive-OR function 110, which receives another input from right-hand side value memory 89, and presents its output as the output of cyclic multiply unit 88 to right-hand side value memory 89, or to parity bit memory 90. Bitwise exclusive-OR function 110 thus serves as a modulo-2 accumulator, in which the output of accumulator 108 are subtracted (which, in modulo-2 arithmetic, is effectively an accumulation) from a current right-hand side value from memory 89.

[0062] For purposes of evaluating matrix operations involving a cyclic submatrix having a weight of one, the output of circular shift unit 104 is directly applied to bitwise exclusive-OR function 110, as the multiple exclusive-OR and accumulation operations are unnecessary. This "direct" connection may, of course, be effected simply by way of bitwise-exclusive-OR function 106 combining a zero value with the output of circular shift unit 104, for a single pass through functions 106, 108. It is also contemplated that, by further constraining the LDPC code so that submatrix B is necessarily a weight one cyclic matrix (i.e., a cyclically shifted identity matrix), while of course maintaining the other constraints regarding the recursion path in parity check matrix HM, exclusive-OR function 106 and accumulator 108 can be eliminated from cyclic multiply unit 88. In such a case, parity check matrix HM may be factored simply by adding all block rows together.

[0063] In operation, cyclic multiply unit 88 performs matrix operations useful in the encoding of the LDPC code, according to the processes described above relative to FIGS. 3 through 5. One such operation is performed by cyclic multiply unit 88 performing process 44 to derive the initial right-hand side values RHS according to equation (8), and loading these values into right-hand side value memory 89. These initial right-hand side values are determined using each non-zero block of the information portion of parity check matrix Hi, one block at a time. According to the preferred embodiment of the invention, the appropriate segment of information portion ci, is forwarded to circular shift unit 104. Circular shift unit 104 shifts the received segment by a shift value received from matrix shift value memory 82, corresponding to the cyclically shifted diagonal within a current block of information parity check matrix portion Hi. The result of this shift is accumulated into right-hand side value memory 89. For these operations, bitwise exclusive-OR function 106 and accumulator 108 are effectively bypassed, with bitwise exclusive-OR function 110 applying previous right-hand side results from memory 88. Alternatively, accumulation of right-hand side results along a block row can be performed by using exclusive-OR function 106 and accumulator 108. This operation continues for all blocks of information parity check matrix portion Hi.

[0064] Process 46 involves deriving the vector rJ for the bottom block row, as described above relative to equation (8a). This evaluation is carried out beginning with circular shift unit 104 shifting a received segment of information portion ci by a shift value received from matrix shift value memory 82, for a first one of the cyclically shifted diagonals within a current block of factored parity check matrix Hf,iL. The shifted result is stored in accumulator 108. Circular shift unit 104 then shifts the information segment by a next value, if the weight of the block exceeds one, and this shifted segment is exclusive-ORed with the previous contents of accumulator 108 by bitwise exclusive-OR function 106. This process continues, until all diagonals within the current block have been calculated, at which point the contents of accumulator 108 are accumulated into right-hand side value memory 89 by bitwise exclusive-OR function 110, which receives the existing contents of right-hand side value memory 89 at its second input. This operation continues for all blocks of the information portion Hf,iL of factored parity check matrix Hf, which is, of course, restricted to the bottom block row.

[0065] In process 48, cyclic multiply unit 88 is then operated to solve for the parity values associated with the Jth block column, using the inverse submatrix B-1, and the values for the bottom block row right-hand side vector rJ from process 46, following equation (8b). As mentioned above, in this case, inverse submatrix B-1 is itself a cyclic matrix, because submatrix B is a cyclic matrix. Accordingly, matrix shift value memory 82 preferably stores the shift values for inverse submatrix B-1. To then solve the parity bits cp,J from equation (8b), cyclic multiply unit 88 loads the bottom block row right-hand side vector rJ from right-hand side value memory 84, via multiplexer 86, into circular shift unit 104. Vector rJ is then shifted by circular shift unit 104, by a first shift value for inverse submatrix B-1 received from matrix shift value memory 82, and the shifted result is stored in accumulator 108. For additional diagonals within submatrix B, vector rJ is shifted again by circular shift unit 104, and accumulated with the prior contents of accumulator 108. Upon completion of the block matrix operations for inverse submatrix B-1, the result in accumulator 108 is forwarded to parity bit memory 90, as the corresponding parity bits cp,J.

[0066] Once these parity bits are determined, then cyclic multiply unit 88 executes update process 50, by applying the parity bits cp,J to the other blocks within the Jth block column. In this process, multiplexer 86 forwards parity bits cp,J to circular shift unit 104, which shifts these input bits by the matrix shift value from memory 82 for the corresponding blocks in the Jth block column, and the result is accumulated with the corresponding block row portion from right-hand side value memory 89, using bitwise exclusive-OR function 110. Upon completion of process 50, the right-hand side value memory 89 is updated so that the Jth block column is now part of the "right-hand side", as in equation (9).

[0067] Process 52 is then performed to solve for the parity bits in a selected block column in the parity portion of the original, non-factored, parity check matrix H. Controller 100 determines the particular block row and block column that is to be evaluated in this instance, and causes right-hand side value memory 89 to present the appropriate contents rk for that selected kth block row to multiplexer 86, and causes matrix shift value memory 82 to apply the corresponding shift value for the particular submatrix (inverse submatrix) Pk,m-1 in the selected kth block row and mth block column to cyclic multiply unit 88. The kth block row and mth block column are selected according to the design of the particular LDPC code and the specific recursion path that is to be followed, which is of course known in advance, thus, for example, following equation (10c). Cyclic multiply unit 88 thus effects process 52 by shifting the received right-hand side contents rk by the value indicated by the shift value for the inverse matrix Pk,m-1, by the operation of circular shift unit 104 and exclusive-OR function 110, thus generating the parity bits cp,m, which are forwarded to parity bit memory 90. These parity bits cp,m are then forwarded back to cyclic multiply unit 88 for updating of the right-hand side values in process 50 (assuming that additional block columns are to be processed, i.e., assuming that decision 53 is YES). The forwarding of parity bits cp,m may follow the optional path shown in FIG. 6 (which may be realized by parity bit memory 90 having a path or mode by way of which it can immediately forward its input values), or may be accomplished by retrieval of these bits from parity bit memory 90 after being stored. Process 50 is then effected by cyclic multiply unit 88 applying the shift value for submatrix Pn.m, which is also determined by the code and the selected recursion path, for example as shown in equation (10d), and accumulating this shifted value with the current right-hand side values to update the values RHS. As mentioned above, these values need not be stored in right-hand side value memory 88, because they are only used in the next solution pass.

[0068] In this manner, the remainder of the parity bits cp are determined by following at least one recursion path, for example as described above relative to equations (10c) through (10m). Also as described above, controller 100 can effect the recursive operations by following two recursion paths, in which case another instance of cyclic multiply unit 88 would be useful for parallel processing.

[0069] Upon completion of the recursion path or paths, parity bit memory 90 will contain the encoded parity bits for the information bits then stored in information bit vector memory 84. These values can then be readily combined (i.e., appended to one another), to form the systematic encoded code word c, which is forwarded by encoding function 11 (FIG. 1) to the next function in the data flow. The next information word to be encoded can then be received, and stored in information bit vector memory 84, and the operation of encoder 38 repeated.

[0070] While FIG. 6 illustrates a hardware implementation of encoder 38, it will of course be understood by those skilled in the art having reference to this specification that the encoding process according to the preferred embodiment of this invention may also readily be realized by way of a software program executed by a programmable processor such as a microprocessor or a digital signal processor. It is contemplated that such a software implementation may be readily be realized by those skilled in the art having reference to this specification, without undue experimentation.

[0071] As mentioned above, the encoding of digital data for communication according to this preferred embodiment provides numerous important advantages, including reduction of memory requirements for the LDPC code and the computations required for encoding. In addition, as evident from the above description regarding encoder 38 relative to FIG. 6, hardware and software realization of this encoding approach is greatly streamlined, resulting in an encoder that can be realized at relatively low cost, and that can provide excellent real-time encoding for high data rate communications.

[0072] While the present invention has been described according to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as claimed.


Claims

1. A method of encoding code words comprising the steps of:

(a) storing in memory, parameters associated with each of a plurality of macro matrix entries of a low-density parity check matrix (HM), the matrix (HM) comprising an information portion (Hi) to be applied to the information bits (ci) of a systematic low-density parity check (LDPC) codeword vector (c) and a parity portion (Hp) to be applied to the parity bits (cp) of the codeword vector and wherein the matrix has a column and row block structure in which each entry represents a pxp submatrix block and each non-zero entry indicates that the corresponding pxp submatrix block is a cyclically shifted identity matrix; and characterized by

(b) factoring the low density macro parity check matrix (HM) to a form

wherein

B is an invertible cyclic pxp submatrix (page 14, lines 6) occupying the jth block row and the jth block column position of the factored parity check matrix (Hf), j being the position of a selected block column within the parity portion (Hp) of the low-density parity check matrix (H);

α is a submatrix of one column block by (n-1) block rows in the corresporiding macro parity check matrix (HM),



and

are submatrices corresponding to the upper and lower portions of the information portion (Hi) of the factored parity check matrix (Hf)

Hfp is a submatrix having a block upper triangular structure corresponding to the remaining portion of the parity portion of the factored parity check matrix (Hf) and wherein

all of the submatrices in the factored parity check matrix (Hf) are block matrices within which each block is a pxp cyclic matrix with a weight that is not constrained to 1;

(c) receiving an information word (ci) to be encoded (42);

(d) computing right-hand side values (RHS) for the jth block row of the factored parity check matrix (Hf)containing submatrix B by multiplying the information word (ci) by the information portion (Hi) of the parity check matrix (HM) (44);

(e) computing a matrix vector product (rJ) for the jth block row containing submatrix B (46);

(f) solving the parity bits (cpJ) for the jth block column containing submatrix B according to cp,J = B-1 rJ (48);

(g) computing updated right hand side values (RHS) by adding to the previous right hand side value, the vector product (rJ) of the solved parity bits (cpJ) of the Jth block column (50);

(h) solving the parity bits for the Nth block column according to

wherein the Nth block column contains non-zero entries in an Mth block row having a non-zero entries over all but the Jth block column in the parity portion (Hp) of the low density parity check matrix (HM) and where rl is the matrix vector product for the Mth block row in block row of the updated right-hand side value (52)

(i) repeating step (g) and (h) if any block columns in the macro parity check matrix contain unsolved parity bits, wherein in step (g) the solved parity bits for the Nth block column are used to update the right-hand side values (53).


 
2. The method of claim 1, wherein the non-zero entries of the factored parity block matrix (Hf) comprise a weight value indicating the number of shifted diagonals contained within that entry, and shift values indicating the position of the shifted diagonals.
 
3. An encoder (38) for generating a code word according to a low-density parity check code, comprising:

a matrix value memory (82) arranged to store, parameters associated with each of a plurality of macro matrix entries of a low-density parity check matrix (HM), the matrix (HM) comprising an information portion (Hi) to be applied to the information bits (ci) of a systematic low-density parity check (LDPC) codeword vector (c) and a parity portion (Hp) to be applied to the parity bits (cp) of the codeword vector and wherein the matrix has a column and row block structure in which each entry represents a pxp submatrix block and each non-zero entry indicates that the corresponding pxp submatrix block is a cyclically shifted identity matrix; and characterized by

processing means (88, 100) adapted to
factor the low density macro parity check matrix (HM) to a form

wherein

B is an invertible cyclic pxp submatrix (page 14, lines 6) occupying the jth block row and the jth block column position of the factored parity check matrix (Hf), j being the position of a selected block column within the parity portion (Hp) of the low-density parity check matrix (H);

a is a submatrix of one column block by (n-1) block rows in the corresponding macro parity check matrix (HM);



and

are submatrices corresponding to the upper and lower portions of the information portion (Hi) of the factored parity check matrix (Hf);

Hfp is a submatrix having a block upper triangular structure corresponding to the remaining portion of the parity portion of the factored parity check matrix (Hf) and wherein

all of the submatrices in the factored parity check matrix (Hf) are block matrices within which each block is a pxp cyclic matrix with a weight that is not constrained to

receive an information word (ci) to be encoded ;

compute right-hand side values (RHS) for the jth block row of the factored parity check matrix (Hf)containing submatrix B by multiplying the information word (ci) by the information portion (Hi) of the parity check matrix (HM);

compute a matrix vector product (rJ) for the jth block row containing submatrix B;

solve the parity bits (cpJ) for the jth block column containing submatrix B according to cp,J = B-1 rJ;

compute updated right hand side values (RHS) by adding to the previous right hand side value, the vector product (rJ) of the solved parity bits (cpJ) of the Jth block column (50); and

solve the parity bits for the Nth block column according to

wherein the Nth block column contains non-zero entries in an Mth block row having a non-zero entries over all but the Jth block column in the parity portion (Hp) of the low density parity check matrix (HM) and where rl is the matrix vector product for the Mth block row in block row of the updated right-hand side value.


 
4. The encoder of claim 3, wherein the non-zero entries of the factored parity block matrix (Hf) comprises a weight value indicating the number of shifted diagonals contained within that entry, and shift values indicating the position of the shifted diagonals.
 
5. The encoder of claim 3, wherein the processing means comprises:

programmable logic circuitry; and

program memory for storing instructions that are executable by the programmable logic circuitry.


 
6. The encoder of any of claims 3 to 5, wherein the processing means comprises:

a cyclic multiply unit (88), coupled to the matrix value memory (82), and comprising:

a shifter (104) for circularly shifting a selected portion of the information bit vector (ci);

an exclusive-OR function(106) for performing a bitwise exclusive-OR operation on the output of the shifter (104) and right-hand side product values; and

a controller (100) for controlling the operation of the cyclic multiply unit (88) and accessing of the matrix value memory (82); and

wherein the cyclic multiply unit (88) further comprises an accumulator (108), for storing shifter result values.


 


Ansprüche

1. Verfahren zum Codieren von Codewörtern mit den folgenden Schritten:

(a) Speichern von Parametern, die jedem von mehreren Makro-Matrixeinträgen einer Low-Density-Parity-Check-Matrix (HM) zugeordnet sind, in Speicher, wobei die Matrix (HM) einen auf die Informationsbit (ci) eines systematischen Low-Density-Parity-Check- bzw. LDPC-Codewortvektors (c) anzuwendenden Informationsteil (Hi) und einen auf die Paritätsbit (cp) des Codewortvektors anzuwendenden Paritätsteil (Hp) umfasst und wobei die Matrix eine Spalten- und Zeilenblockstruktur aufweist, worin jeder Eintrag einen pxp-Submatrixblock repräsentiert und jeder von 0 verschiedene Eintrag angibt, dass der entsprechende pxp-Submatrixblock eine zyklisch verschobene Einheitsmatrix ist; und gekennzeichnet durch

(b) Faktorisieren der Low-Density-Makro-Parity-Check-Matrix (HM) auf eine Form

wobei

B eine invertierbare zyklische pxp-Submatrix (Seite 14, Zeilen 6) ist, die die j-te Blockzeilen- und die j-te Blockspaltenposition der faktorisierten Parity-Check-Matrix (Hf) einnimmt, wobei j die Position einer ausgewählten Blockspalte in dem Paritätsteil (Hp) der Low-Density-Parity-Check-Matrix (H) ist;

α eine Submatrix von einem Spaltenblock mal (n-1) Blockzeilen in der entsprechenden Makro-Parity-Check-Matrix (HM) ist,

und

Submatrizen entsprechend dem oberen und unteren Teil des Informationsteils (Hi) der faktorisierten Parity-Check-Matrix (Hf) sind,

Hfp eine Submatrix mit einer Block-Oberes-Dreieck-Struktur entsprechend dem übrigen Teil des Paritätsteils der faktorisierten Parity-Check-Matrix (Hf) ist und wobei

alle Submatrizen in der faktorisierten Parity-Check-Matrix (Hf) Blockmatrizen sind, in denen jeder Block eine zyklische pxp-Matrix mit einem Gewicht ist, das nicht auf 1 beschränkt ist;

(c) Empfangen eines zu codierenden Informationsworts (ci) (42);

(d) Berechnen von Werten der rechten Seite (RHS) für die j-te Blockzeile der faktorisierten Parity-Check-Matrix (Hf), die die Submatrix B enthält, durch Multiplizieren des Informationsworts (ci) mit dem Informationsteil (Hi) der Parity-Check-Matrix (HM) (44);

(e) Berechnen eines Matrix-Vektor-Produkts (rJ) für die j-te Blockzeile, die die Submatrix B enthält (46) ;

(f) Lösen der Paritätsbit (cpJ) für die j-te Blockspalte, die die Submatrix B enthält, gemäß Cp,J = B-1rJ (48);

(g) Berechnen von aktualisierten Werten der rechten Seite (RHS) durch Addieren des Vektorprodukts (rJ) der gelösten Paritätsbit (cpJ) der J-ten Blockspalte zu dem vorherigen Wert der rechten Seite (50) ;

(h) Lösen der Paritätsbit für die N-te Blockspalte gemäß

wobei die N-te Blockspalte von null verschiedenen Einträge in einer M-ten Blockzeile mit einem von null verschiedenen Einträgen insgesamt bis auf die J-te Blockspalte in dem Paritätsteil (Hp) der Low-Density-Parity-Check-Matrix (HM) enthält und wobei r1 das Matrix-Vektor-Produkt für die M-te Blockzeile in der Blockzeile des aktualisierten Werts der rechten Seite ist (52),

(i) Wiederholen von Schritt (g) und (h), wenn irgendwelche Blockspalten in der Makro-Parity-Check-Matrix ungelöste Paritätsbit enthalten, wobei in Schritt (g) die gelösten Paritätsbit für die N-te Blockspalte zum Aktualisieren der Werte der rechten Seite verwendet werden (53).


 
2. Verfahren nach Anspruch 1, wobei die von null verschiedenen Einträge der faktorisierten Parity-Block-Matrix (Hf) einen Gewichtswert, der die Anzahl der in diesem Eintrag enthaltenen verschobenen Diagonalen angibt, und Verschiebungswerte, die die Position der verschobenen Diagonalen angeben, umfassen.
 
3. Codierer (38) zum Erzeugen eines Codeworts gemäß einem Low-Density-Parity-Check-Code, umfassend:

einen Matrixwertspeicher (82), ausgelegt zum Speichern von Parametern, die jedem von mehreren Makro-Matrixeinträgen einer Low-Density-Parity-Check-Matrix (HM) zugeordnet sind, wobei die Matrix (HM) einen auf die Informationsbit (ci) eines systematischen Low-Density-Parity-Check- bzw. LDPC-Codewortvektors (c) anzuwendenden Informationsteil (Hi) und einen auf die Paritätsbit (cp) des Codewortvektors anzuwendenden Paritätsteil (Hp) umfasst und wobei die Matrix eine Spalten- und Zeilenblockstruktur aufweist, worin jeder Eintrag einen pxp-Submatrixblock repräsentiert und jeder von 0 verschiedene Eintrag angibt, dass der entsprechende pxp-Submatrixblock eine zyklisch verschobene Einheitsmatrix ist; und gekennzeichnet durch

Verarbeitungsmittel (88, 100), ausgelegt zum Faktorisieren der Low-Density-Makro-Parity-Check-Matrix (HM) auf eine Form

wobei

B eine invertierbare zyklische pxp-Submatrix (Seite 14, Zeilen 6) ist, die die j-te Blockzeilen- und die j-te Blockspaltenposition der faktorisierten Parity-Check-Matrix (Hf) einnimmt, wobei j die Position einer ausgewählten Blockspalte in dem Paritätsteil (Hp) der Low-Density-Parity-Check-Matrix (H) ist;

α eine Submatrix von einem Spaltenblock mal (n-1) Blockzeilen in der entsprechenden Makro-Parity-Check-Matrix (HM) ist,



und

Submatrizen entsprechend dem oberen und unteren Teil des Informationsteils (Hi) der faktorisierten Parity-Check-Matrix (Hf) sind,

Hfp eine Submatrix mit einer Block-Oberes-Dreieck-Struktur entsprechend dem übrigen Teil des Paritätsteils der faktorisierten Parity-Check-Matrix (Hf) ist und wobei

alle Submatrizen in der faktorisierten Parity-Check-Matrix (Hf) Blockmatrizen sind, in denen jeder Block eine zyklische pxp-Matrix mit einem Gewicht ist, das nicht auf 1 beschränkt ist;

Empfangen eines zu codierenden Informationsworts (ci);

Berechnen von Werten der rechten Seite (RHS) für die j-te Blockzeile der faktorisierten Parity-Check-Matrix (Hf), die die Submatrix B enthält, durch Multiplizieren des Informationsworts (ci) mit dem Informationsteil (Hi) der Parity-Check-Matrix (HM);

Berechnen eines Matrix-Vektor-Produkts (rJ) für die j-te Blockzeile, die die Submatrix B enthält;

(f) Lösen der Paritätsbit (cpJ) für die j-te Blockspalte, die die Submatrix B enthält, gemäß Cp,J = B-1rJ;

Berechnen von aktualisierten Werten der rechten Seite (RHS) durch Addieren des Vektorprodukts (rJ) der gelösten Paritätsbit (cpJ) der J-ten Blockspalte zu dem vorherigen Wert der rechten Seite (50); und

(h) Lösen der Paritätsbit für die N-te Blockspalte gemäß

wobei die N-te Blockspalte von null verschiedenen Einträge in einer M-ten Blockzeile mit einem von null verschiedenen Einträgen insgesamt bis auf die J-te Blockspalte in dem Paritätsteil (Hp) der Low-Density-Parity-Check-Matrix (HM) enthält und wobei r1 das Matrix-Vektor-Produkt für die M-te Blockzeile in der Blockzeile des aktualisierten Werts der rechten Seite ist.


 
4. Codierer nach Anspruch 3, wobei die von null verschiedenen Einträge der faktorisierten Parity-Block-Matrix (Hf) einen Gewichtswert, der die Anzahl der in diesem Eintrag enthaltenen verschobenen Diagonalen angibt, und Verschiebungswerte, die die Position der verschobenen Diagonalen angeben, umfassen.
 
5. Codierer nach Anspruch 3, wobei die Verarbeitungsmittel Folgendes umfassen:

programmierbare Logikschaltkreise; und

Programmspeicher zum Speichern von Anweisungen, die durch die programmierbaren Logikschaltkreise ausführbar sind.


 
6. Codierer nach einem der Ansprüche 3 bis 5, wobei die Verarbeitungsmittel Folgendes umfassen:

eine mit dem Matrixwertspeicher (82) gekoppelte Einheit (88) zum zyklischen Multiplizieren, umfassend:

einen Schieber (104) zum kreisförmigen Verschieben eines ausgewählten Teils des Informationsbitvektors (ci);

eine exklusiv-ODER-Funktion (106) zum Ausführen einer bitweisen exklusiv-ODER-Operation an der Ausgabe des Schiebers (104) und Produktwerten der rechten Seite; und

eine Steuerung (100) zum Steuern des Betriebs der Einheit (88) zum zyklischen Multiplizieren und Zugreifen auf den Matrixwertspeicher (82); und

wobei die Einheit (88) zum zyklischen Multiplizieren ferner einen Akkumulator (108) zum Speichern von Schieberergebniswerten umfasst.


 


Revendications

1. Procédé de codage de mots codés comprenant les étapes consistant à :

(a) stocker dans une mémoire des paramètres associés à chaque entrée de macro-matrice d'une pluralité d'entrées de macro-matrice d'une matrice de contrôle de parité de faible densité (HM), la matrice (HM) comprenant une partie informations (Hi) qui doit être appliquée aux bits d'informations (ci) d'un vecteur (c) de mot codé de contrôle systématique de parité de faible densité (LDPC), et une partie de parité (Hp) qui doit être appliquée aux bits de parité (Cp) du vecteur de mot codé et dans lequel la matrice comporte une structure de bloc de rangée et de colonne dans laquelle chaque entrée représente un bloc de sous-matrice p x p et chaque entrée non nulle indique que le bloc de sous-matrice p x p correspondant est une matrice d'identité décalée de manière cyclique ; et caractérisé par le fait de

(b) factoriser la matrice de contrôle de parité de faible densité (HM) sous une forme

dans laquelle

B est une sous-matrice p x p cyclique pouvant être inversée (page 14, ligne 6) occupant la jème rangée de bloc et la jème position de colonne de bloc de la matrice de contrôle de parité factorisée (Hf), j étant la position d'une colonne de bloc sélectionnée dans la partie de parité (Hp) de la matrice de contrôle de parité de faible densité (H) ;

α est une sous-matrice d'un bloc de colonne par (n - 1) rangées de bloc dans la macro-matrice de contrôle de parité correspondante (HM),



et

sont des sous-matrices correspondant aux parties supérieure et inférieure de la partie informations (Hi) de la matrice de contrôle de parité factorisée (Hf)

Hfp est une sous-matrice ayant une structure triangulaire supérieure de bloc correspondant à la partie restante de la partie de parité de la matrice de contrôle de parité factorisée (Hf) et dans lequel

toutes les sous-matrices de la matrice de contrôle de parité factorisée (Hf) sont des matrices de bloc dans lesquelles chaque bloc est une matrice cyclique p x p ayant un poids qui n'est pas limité à 1 ;

(c) recevoir un mot d'information (ci) qui doit être codé (42) ;

(d) calculer des valeurs côté droit (RHS) pour la jème rangée de bloc de la matrice de contrôle de parité factorisée (Hf) contenant la sous-matrice B par multiplication du mot d'information (ci) par la partie informations (Hi) de la matrice de contrôle de parité (HM) (44) ;

(e) calculer un produit vectoriel de matrice (rJ) pour la jème rangée de bloc contenant la sous-matrice B (46) ;

(f) résoudre les bits de parité (cpJ) pour la jème colonne de bloc contenant la sous-matrice B selon cp,J = B-1 rJ (48) ;

(g) calculer des valeurs côté droit mises à jour (RHS) par ajout à la précédente valeur côté droit du produit vectoriel (rJ) des bits de parité résolus (cpJ) de la Jème colonne de bloc (50) ;

(h) résoudre les bits de parité pour la Nième colonne de bloc selon

où la Nième colonne de bloc contient des entrées non nulles dans une Mième rangée de bloc ayant des entrées non nulles sur toutes les colonnes sauf la Jème colonne de bloc dans la partie de parité (Hp) de la matrice de contrôle de parité de faible densité (HM) et où rl est le produit vectoriel de matrice pour la Mième rangée de bloc dans une rangée de bloc de la valeur côté droit mise à jour (52)

(i) répéter l'étape (g) et l'étape (h) si de quelconques colonnes de bloc dans la macro-matrice de contrôle de parité contiennent des bits de parité non résolus, dans lequel, à l'étape (g), les bits de parité résolus pour la Nième colonne de bloc sont utilisés pour mettre à jour les valeurs côté droit (53).


 
2. Procédé selon la revendication 1, dans lequel les entrées non nulles de la matrice de contrôle de parité factorisée (Hf) comprennent une valeur de pondération indiquant le nombre de diagonales décalées contenues dans cette entrée ainsi que des valeurs de décalage indiquant la position des diagonales décalées.
 
3. Codeur (38) pour générer un mot codé selon un code de contrôle de parité de faible densité, comprenant :

une mémoire de valeur de matrice (82) conçue pour stocker des paramètres associés à chaque entrée de macro-matrice d'une pluralité d'entrées de macro-matrice d'une matrice de contrôle de parité de faible densité (HM), la matrice (HM) comprenant une partie informations (Hi) qui doit être appliquée aux bits d'informations (ci) d'un vecteur (c) de mot codé de contrôle systématique de parité de faible densité (LDPC), et une partie de parité (Hp) qui doit être appliquée aux bits de parité (cp) du vecteur de mot codé et dans lequel la matrice comporte une structure de bloc de rangée et de colonne dans laquelle chaque entrée représente un bloc de sous-matrice p x p et chaque entrée non nulle indique que le bloc de sous-matrice p x p correspondant est une matrice d'identité décalée de manière cyclique ; et caractérisé par

un moyen de traitement (88, 100) conçu pour

factoriser la matrice de contrôle de parité de faible densité (HM) sous une forme

dans laquelle

B est une sous-matrice p x p cyclique pouvant être inversée (page 14, ligne 6) occupant la jème rangée de bloc et la jème position de colonne de bloc de la matrice de contrôle de parité factorisée (Hf), j étant la position d'une colonne de bloc sélectionnée dans la partie de parité (Hp) de la matrice de contrôle de parité de faible densité (H) ;

α est une sous-matrice d'un bloc de colonne par (n - 1) rangées de bloc dans la macro-matrice de contrôle de parité correspondante (HM) ;



et

sont des sous-matrices correspondant aux parties supérieure et inférieure de la partie informations (Hi) de la matrice de contrôle de parité factorisée (Hf) ;

Hfp est une sous-matrice ayant une structure triangulaire supérieure de bloc correspondant à la partie restante de la partie de parité de la matrice de contrôle de parité factorisée (Hf) et dans lequel

toutes les sous-matrices de la matrice de contrôle de parité factorisée (Hf) sont des matrices de bloc dans lesquelles chaque bloc est une matrice cyclique p x p ayant un poids qui n'est pas limité à 1 ;

recevoir un mot d'information (ci) qui doit être codé ;

calculer des valeurs côté droit (RHS) pour la jème rangée de bloc de la matrice de contrôle de parité factorisée (Hf) contenant la sous-matrice B par multiplication du mot d'information (ci) par la partie informations (Hi) de la matrice de contrôle de parité (HM) ;

calculer un produit vectoriel de matrice (rJ) pour la jème rangée de bloc contenant la sous-matrice B ;

résoudre les bits de parité (cpJ) pour la Jème colonne de bloc contenant la sous-matrice B selon Cp,J = B-1 rJ;

calculer des valeurs côté droit mises à jour (RHS) par ajout à la précédente valeur côté droit du produit vectoriel (rJ) des bits de parité résolus (cpJ) de la Jème colonne de bloc (50) ; et

résoudre les bits de parité pour la Nième colonne de bloc selon


où la Nième colonne contient des entrées non nulles dans une Mième rangée de bloc ayant des entrées non nulles sur toutes les colonnes sauf la Jème colonne de bloc dans la partie de parité (Hp) de la matrice de contrôle de parité de faible densité (HM) et où rl est le produit vectoriel de matrice pour la Mième rangée de bloc dans une rangée de bloc de la valeur côté droit mise à jour.


 
4. Codeur selon la revendication 3, dans lequel les entrées non nulles de la matrice de contrôle de parité factorisée (Hf) comprennent une valeur de pondération indiquant le nombre de diagonales décalées contenues dans cette entrée ainsi que des valeurs de décalage indiquant la position des diagonales décalées.
 
5. Codeur selon la revendication 3, dans lequel le moyen de traitement comprend :

des circuits logiques programmables ; et

une mémoire de programme pour stocker des instructions qui peuvent être exécutées par les circuits logiques programmables.


 
6. Codeur selon l'une quelconque des revendications 3 à 5, dans lequel le moyen de traitement comprend :

une unité de multiplication cyclique (88), couplée à mémoire de valeur de matrice (82), et comprenant :

un dispositif de décalage (104) pour décaler de manière circulaire une partie sélectionnée du vecteur de bit d'informations (ci) ;

une fonction OU exclusif (106) pour effectuer une opération OU exclusif au niveau des bits sur la sortie de dispositif de décalage (104) et des valeurs de produit côté droit ; et

un dispositif de commande (100) pour commander l'opération de l'unité de multiplication cyclique (88) et avoir accès à la mémoire de valeur de mémoire (82) ; et

dans lequel l'unité de multiplication cyclique (88) comprend en outre un accumulateur (108) pour stocker des valeurs de résultat de dispositif de décalage.


 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description