(19)
(11)EP 1 633 673 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.12.2019 Bulletin 2019/49

(21)Application number: 04785662.0

(22)Date of filing:  30.03.2004
(51)Int. Cl.: 
H01L 21/00  (2006.01)
B81C 1/00  (2006.01)
(86)International application number:
PCT/US2004/009661
(87)International publication number:
WO 2004/108585 (16.12.2004 Gazette  2004/51)

(54)

METHOD FOR FABRICATING MICROELECTROMECHANICAL SYSTEMS HAVING TRENCH ISOLATED CONTACTS

HERSTELLUNGSVERFAHREN FÜR MIKROELEKTROMECHANISCHE SYSTEME MIT GRABENISOLIERTEN KONTAKTEN

PROCEDE DE FABRICATION DE SYSTEMES MICROELECTROMECANIQUES AVEC CONTACTS ISOLES PAR DES TRANCHEES


(84)Designated Contracting States:
DE FR GB IT SE

(30)Priority: 04.06.2003 US 455555

(43)Date of publication of application:
15.03.2006 Bulletin 2006/11

(60)Divisional application:
19151217.7 / 3527529

(73)Proprietor: ROBERT BOSCH GMBH
70442 Stuttgart (DE)

(72)Inventors:
  • PARTRIDGE, Aaron
    Palo Alto, CA 94301 (US)
  • LUTZ, Markus
    Palo Alto, CA 94306 (US)
  • KRONMUELLER, Silvia
    71409 Schwaikheim (DE)


(56)References cited: : 
EP-A2- 1 464 615
DE-A1- 19 961 578
US-B1- 6 635 509
DE-A1- 10 005 555
US-A1- 2002 016 058
  
  • KENNY ET AL: "An Integrated Wafer-Scale Packaging Process for MEMS", ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION,, 1 November 2002 (2002-11-01), pages 51-54, XP008107777,
  • LEDERMANN N ET AL: "Sputtered silicon carbide thin films as protective coating for MEMS applications", SURFACE AND COATINGS TECHNOLOGY, ELSEVIER, AMSTERDAM, NL, vol. 125, no. 1-3 1 March 2000 (2000-03-01), pages 246-250, XP027328829, ISSN: 0257-8972 [retrieved on 2000-03-01]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

BACKGROUND



[0001] This invention relates to electromechanical systems and techniques for fabricating microelectromechanical and nanoelectromechanical systems; and more particularly to fabricating or manufacturing microelectromechanical and nanoelectromechanical systems with high performance integrated circuits on a common substrate.

[0002] Microelectromechanical systems ("MEMS"), for example, gyroscopes, resonators and accelerometers, utilize micromachining techniques (i.e., lithographic and other precision fabrication techniques) to reduce mechanical components to a scale that is generally comparable to microelectronics. MEMS typically include a mechanical structure fabricated from or on, for example, a silicon substrate using micromachining techniques.

[0003] The mechanical structures are typically sealed in a chamber. The delicate mechanical structure may be sealed in, for example, a hermetically sealed metal container (for example, a TO-8 "can", see, for example, U.S. Pat. No. 6,307,815) or bonded to a semiconductor or glass-like substrate having a chamber to house, accommodate or cover the mechanical structure (see, for example, U.S. Pat. Nos. 6,146,917; 6,352,935; 6,477,901; and 6,507,082). In the context of the hermetically sealed metal container, the substrate on, or in which, the mechanical structure resides may be disposed in and affixed to the metal container. The hermetically sealed metal container also serves as a primary package as well.

[0004] In the context of the semiconductor or glass-like substrate packaging technique, the substrate of the mechanical structure may be bonded to another substrate whereby the bonded substrates form a chamber within which the mechanical structure resides. In this way, the operating environment of the mechanical structure may be controlled and the structure itself protected from, for example, inadvertent contact. The two bonded substrates may or may not be the primary package for the MEMS as well.

[0005] MEMS that employ a hermetically sealed metal container or a bonded semiconductor or glass-like substrate to protect the mechanical structures tend to be difficult to cost effectively integrate with high performance integrated circuitry on the same substrate. In this regard, the additional processing required to integrate the high performance integrated circuitry, tends to either damage or destroy the mechanical structures.

[0006] Another technique for forming the chamber that protects the delicate mechanical structure employs micromachining techniques. (See, for example, International Published Patent Applications Nos. WO 01/77008 A1 and WO 01/77009 A1). In this regard, the mechanical structure is encapsulated in a chamber using a conventional oxide (SiO2) deposited or formed using conventional techniques (i.e., oxidation using low temperature techniques (LTO), tetraethoxysilane (TEOS) or the like). (See, for example, WO 01/77008 A1, FIGS. 2-4). When implementing this technique, the mechanical structure is encapsulated prior to packaging and/or integration with integrated circuitry.

[0007] While employing a conventional oxide to encapsulate the mechanical structures of the MEMS may provide advantages relative to hermetically sealed metal container or a bonded semiconductor or glass-like substrate, a conventional oxide, deposited using conventional techniques, often exhibits high tensile stress at, for example, corners or steps (i.e., significant spatial transitions in the underlying surface(s)). Further, such an oxide is often formed or deposited in a manner that provides poor coverage of those areas where the underlying surface(s) exhibit significant spatial transitions. In addition, a conventional oxide (deposited using conventional techniques) often provides an insufficient vacuum where a vacuum is desired as the environment in which the mechanical structures are encapsulated and designed to operate. These shortcomings may impact the integrity and/or performance of the MEMS.

[0008] Moreover, a conventional oxide, deposited using conventional techniques, may produce a film on the mechanical structures during the encapsulation process. This film may impact the integrity of the mechanical structures and, as such, the performance or operating characteristics of the MEMS (for example, the operating characteristics of a resonator).

[0009] There are further methods known for manufacturing an electromechanical device comprising a mechanical structure, which is arranged in a sealed chamber.

[0010] For example DE 100 05 555 A1 shows a method for manufacturing an electromechanical device, with which a partially formed device is provided, comprising a substrate on which a chamber-free sacrificial layer is disposed. On this sacrificial layer, there are mechanical structures disposed. An electrical contact area is disposed inside the sacrificial layer. The manufacturing method does not provide manufacturing steps for creating a contact via allowing to electrically connect the electromechanical device from the side being opposite to the substrate. Therefore, the manufactured electromechanical has to be electrically connected from the substrate side.

[0011] DE 199 61 578 A1 discloses a method for manufacturing a micromechanical device, with which a partially formed device is provided, comprising a substrate on which a first sacrificial layer is disposed. On this first sacrificial layer a mechanical structure is disposed. An electrical contact is disposed inside the sacrificial layer. With this method there are two manufacturing steps needed for creating the final chamber that will be sealed. In a first chamber-building step a first chamber is created in the first sacrificial layer that is disposed on the substrate. In the following manufacturing step a second sacrificial layer is disposed on the device, also filling up the existing chamber. After depositing a first encapsulation layer on the device, in a second chamber-building step the material of the second sacrificial layer is removed, exposing the final chamber in the first first sacrificial layer. Because of these two chamber-creating steps this method is elaborate and expensive.

[0012] There is a need for MEMS manufacturing methods (for example, gyroscopes, resonators, temperature sensors and/or accelerometers) that overcome one, some or all of the shortcomings of the conventional materials and techniques.

SUMMARY OF THE INVENTION



[0013] The present invention is a method for manufacturing an electromechanical device as claimed in claim 1.

[0014] The trench surrounds the contact via to electrically isolate the contact.

[0015] The method may further include depositing an insulating layer on at least a portion of the trench and, thereafter, depositing an highly conductive material on the contact and over the insulating layer to provide electrical connection to the contact. In an advantageous measure, a semiconductor material may be deposited in the trench after depositing the insulating material.

[0016] Advantageously, a second material may be deposited in the trench after deposition of the first material. The second material may be a semiconductor material.

[0017] Further advantageously, a first portion of the first encapsulation layer is comprised of a monocrystalline silicon and a second portion is comprised of a polycrystalline silicon. Therefore, a surface of the second encapsulation layer may be planarized to expose the first portion of the first encapsulation. Thereafter, a monocrystalline silicon may be grown on the first portion of the first encapsulation.

[0018] The method may further include depositing an insulating layer on at least a portion of the trench and, thereafter, depositing an highly conductive material on the contact and over the insulating layer to provide electrical connection to the contact. Advantageously, a semiconductor material may be deposited in the trench after depositing the insulating material.

BRIEF DESCRIPTION OF THE DRAWINGS



[0019] In the course of the detailed description to follow, reference will be made to the attached drawings. These drawings show different aspects of the present invention and, where appropriate, reference numerals illustrating like structures, components, materials and/or elements in different figures are labeled similarly. It is understood that various combinations of the structures, components, materials and/or elements, other than those specifically shown, are contemplated.

FIG. 1 is a block diagram of microelectromechanical system disposed on a substrate, in conjunction with interface circuitry and data processing electronics;

FIG. 2 illustrates a top view of a portion of micromechanical structure, for example, or portion of the interdigitated or comb-like finger electrode arrays of an accelerometer, in conjunction with a contact area and field region;

FIG. 3 illustrates a cross-sectional view (sectioned along dotted line a-a of FIG. 2) of the portion of the interdigitated or comb-like finger electrode array, contact area and field region of FIG. 2, in accordance with the present invention;

FIGS. 4A-4I illustrate cross-sectional views of the fabrication of the microstructure of FIG. 3 at various stages of the process, according to the present invention;

FIG. 5 illustrates a cross-sectional view of additional fabrication processes of the microstructure of FIG. 3, according to advantageous aspects not being covered by the present invention;

FIGS. 6A-6H illustrate cross-sectional views of the fabrication of the microstructure of FIG. 3 at various stages of the process, according to aspects not being covered by the present invention;

FIGS. 7A-7C illustrate, among other things, cross-sectional views of more representative illustrations of the growth of single crystal structures using non-conformal and conformal deposition, growth and/or formation techniques;

FIGS. 8A-8E illustrate cross-sectional views of the microstructure, including the isolation trench, according to aspects not being covered by the invention;

FIGS. 9A-9D and 10A-C illustrate portions of the fabrication of the interdigitated or comb-like finger electrode array microstructure of FIG. 2, sectioned along dotted line a-a, in accordance with aspects not being covered by the present invention;

FIGS. 11A-D illustrate cross-sectional views of the fabrication of the microstructure at various stages of an alternative process not being covered by the invention where the first encapsulation layer is a permeable material;

FIG. 12 illustrates a cross-sectional view of the interdigitated or comb-like finger electrode array microstructure of FIG. 2, sectioned along dotted line a-a, in accordance with another aspect not being covered by the present invention including three or more encapsulation layers;

FIG. 13A illustrates a cross-sectional view of a portion of a plurality of micromechanical structures, each having one or more electromechanical systems, which are monolithically integrated on or within the substrate of a MEMS, in accordance with the present invention;

FIG. 13B, 13C and 13D illustrate cross-sectional views of a portion of a micromechanical structure, having a plurality of microstructures, which are monolithically integrated on or within the substrate of a MEMS, in accordance with the present invention;

FIG. 14A, 14C, 14D illustrate cross-sectional views of MEMS, according to the present inventions, including a micromachined mechanical structure portion and an integrated circuit portion, both portions of which are disposed or integrated on a common substrate; the MEMS shown in FIGURE 14B, 14E is not being covered by the invention; and

FIG. 15 illustrates a cross-sectional view of a portion of a micromachined micromechanical structure, having a microstructure, which includes a layer of the second encapsulation layer deposited thereon.


DETAILED DESCRIPTION



[0020] The present invention is directed to a technique of fabricating or manufacturing a MEMS device, having mechanical structures encapsulated in a chamber prior to final packaging and/or completion of the device. The material that encapsulates the mechanical structures may include one or more of the following attributes: low tensile stress, good step coverage, maintains integrity when subjected to subsequent processing, does not significantly and/or adversely affect the performance characteristics of the mechanical structures (if coated with the material during its deposition, formation and/or growth) within the chamber, maintains designed, appropriate and/or suitable encapsulation attributes over operating conditions and/or time, and/or facilitates integration with high-performance integrated circuits. The mechanical structures may be encapsulated by a semiconductor material, for example, silicon (for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon or porous polycrystalline silicon, whether doped or undoped), germanium, silicon-germanium, silicon carbide or gallium arsenide, or combinations thereof. Such materials may maintain one or more of the following attributes over typical operating conditions and the lifetime of the MEMS.

[0021] With reference to FIG. 1, a MEMS 10 includes a micromachined mechanical structure 12 that is disposed on substrate 14, for example, an undoped semiconductor-like material, a glass-like material, or an insulator-like material. The MEMS 10 may also include data processing electronics 16, to process and analyze information generated by, and/or control or monitor the micromachined mechanical structure 12. In addition, MEMS 10 may also include interface circuitry 18 to provide the information from micromachined mechanical structure 12 and/or data processing electronics 16 to an external device (not illustrated), for example, a computer, indicator/display and/or sensor.

[0022] The data processing electronics 16 and/or interface circuitry 18 may be integrated in or on substrate 14. In this regard, MEMS 10 may be a monolithic structure including mechanical structure 12, data processing electronics 16 and interface circuitry 18. The data processing electronics 16 and/or interface circuitry 18 may also reside on a separate, discrete substrate that, after fabrication, is bonded to or on substrate 14.

[0023] With reference to FIG. 2, micromachined mechanical structure 12 includes mechanical structures 20a-d disposed on, above and/or in substrate 14. The mechanical structures 20a-20d may be comprised of, for example, materials in column IV of the periodic table, for example silicon, germanium, carbon; also combinations of these, for example silicon germanium, or silicon carbide; also of III-V compounds for example gallium phosphide, aluminum gallium phosphide, or other III-V combinations; also combinations of III, IV, V, or VI materials, for example silicon nitride, silicon oxide, aluminum carbide, or aluminum oxide; also metallic silicides, germanides, and carbides, for example nickel silicide, cobalt silicide, tungsten carbide, or platinum germanium suicide; also doped variations including phosphorus, arsenic, antimony, boron, or aluminum doped silicon or germanium, carbon, or combinations like silicon germanium; also these materials with various crystal structures, including single crystalline, polycrystalline, nanocrystalline, or amorphous; also with combinations of crystal structures, for instance with regions of single crystalline and polycrystalline structure (whether doped or undoped).

[0024] Moreover, the micromachined mechanical structure 12 may be an accelerometer, gyroscope or other transducer (for example, pressure sensor, strain sensor, tactile sensor, magnetic sensor and/or temperature sensor), or resonator. The micromachined mechanical structure 12 may also include mechanical structures of a plurality of transducers or sensors including one or more accelerometers, gyroscopes, pressure sensors, tactile sensors and temperature sensors. Where micromachined mechanical structure 12 is an accelerometer, mechanical structures 20a-d may be a portion of the interdigitated or comb-like finger electrode arrays that comprise the sensing features of the accelerometer (See, for example, U.S. Pat. No. 6,122,964).

[0025] With continued reference to FIG. 2, field region 22 and contact area 24 are also disposed on or in substrate 14. The field region 22 may provide a substrate material for the electronic or electrical components or integrated circuits (for example, transistors, resistors, capacitors, inductors and other passive or active elements) of data processing electronics 16 and/or interface circuitry 18. The contact area 24 may provide an electrical path between micromachined mechanical structure 12 and data processing electronics 16, interface circuitry 18 and/or an external device (not illustrated). The field region 22 and contact area 24 may be comprised of, for example, silicon, (whether doped or undoped), germanium, silicon/germanium, silicon carbide, and gallium arsenide, and combinations thereof.

[0026] FIG. 3 illustrates a cross-sectional view of micromachined mechanical structure 12, including mechanical structures 20a-d, along dotted line a-a', in accordance with the present invention. The mechanical structures 20a-d are disposed within chamber 26. The chamber 26 is sealed or encapsulated via encapsulating layers 28a and 28b.

[0027] The encapsulating layers 28a and 28b may be comprised of, for example, a semiconductor. The encapsulating layers 28a and 28b may contain silicon (for example, monocrystalline silicon, polycrystalline silicon, amorphous silicon or porous polycrystalline silicon, whether doped or undoped), germanium, silicon/germanium, silicon carbide, and gallium arsenide (and combinations thereof). The encapsulating layers 28a and 28b may be the same materials or different materials.

[0028] The encapsulating layers 28a and 28b may be deposited, formed and/or grown using the same or different techniques. For example, encapsulating layer 28a may be a polycrystalline silicon deposited using a low pressure ("LP") chemically vapor deposited ("CVD") process (in a tube or EPI reactor) or plasma enhanced ("PE") CVD process and encapsulating layer 28b may be a doped polycrystalline silicon deposited using an atmospheric pressure ("AP") CVD process. Alternatively, for example, encapsulating layer 28a may be a silicon germanium deposited using a LPCVD process and encapsulating layer 28b may be doped polycrystalline silicon deposited using a PECVD process. Indeed, all semiconductor materials and deposition techniques, and permutations thereof, for encapsulating chamber 26, whether now known or later developed, are intended to be within the scope of the present invention.

[0029] It should be noted that the mechanical structures of one or more transducers or sensors (for example, accelerometers, gyroscopes, pressure sensors, tactile sensors and/or temperature sensors) may be contained or reside in a single chamber and exposed to an environment within that chamber. Under this circumstance, the environment contained in chamber 26 provides a mechanical damping for the mechanical structures of one or more micromachined mechanical structures (for example, an accelerometer, a pressure sensor, a tactile sensor and/or temperature sensor).

[0030] Moreover, the mechanical structures of the one or more transducers or sensors may themselves include multiple layers that are vertically and/or laterally stacked or interconnected. (See, for example, micromachined mechanical structure 12b of FIG. 13A; micromachined mechanical structure 12 of FIGS. 13B and 13C; and mechanical structures 20a and 20b, contact areas 24a and 24b, and buried contacts 24' and 24" of FIG. 13D). Thus, under this circumstance, the mechanical structures are fabricated using one or more processing steps to provide the vertically and/or laterally stacked and/or interconnected multiple layers.

[0031] The contact area 24 of micromachined mechanical structure 12 is electrically isolated from nearby electrically conducting regions (for example, second encapsulation layer 28b and/or a field region (not illustrated)). With continued reference to FIG. 3, micromachined mechanical structure 12 includes dielectric isolation regions 44a and 44b that include an insulating material disposed in trenches 46a and 46b. The dielectric isolation regions 44a and 44b (and trenches 46a and 46b) may surround contact 24 to electrically isolate contact 24 from any nearby electrically conducting regions.

[0032] With reference to FIGS. 4A and 4B, an exemplary method of fabricating or manufacturing a micromachined mechanical structure 12 may begin with a partially formed device including mechanical structures 20a-d and contact area 24 disposed on first sacrificial layer 30, for example, silicon dioxide or silicon nitride. Mechanical structures 20a-d and contact area 24 may be formed using well-known deposition, lithographic, etching and/or doping techniques as well as from well-known materials (for example, semiconductors such as silicon, germanium, silicon-germanium or gallium-arsenide). Moreover, field region 22 and first sacrificial layer 30 may be formed using well-known silicon-on-insulator fabrication techniques (FIG. 4A) or well-known formation, lithographic, etching and/or deposition techniques using a standard or over-sized ("thick") wafer (FIG. 4B). Notably, field region 22, mechanical structures 20 and contact area 24 may be comprised of single or monocrystalline structures (for example, monocrystalline silicon) as illustrated in FIG. 4A, polycrystalline structures, or both monocrystalline and polycrystalline structures as illustrated in FIG. 4B (i.e., field region 22 is comprised of a single or monocrystalline structure, for example, monocrystalline silicon, and mechanical structures 20 and contact area 24 may be comprised of polycrystalline structures, for example, polycrystalline silicon. Indeed, all techniques, materials and crystal structures for creating a partially formed device including mechanical structures 20a-d and contact area 24 disposed on first sacrificial layer 30, whether now known or later developed, are intended to be within the scope of the present invention.

[0033] With reference to FIG. 4C, following formation of mechanical structures 20a-d and contact area 24, a second sacrificial layer 32, for example, silicon dioxide or silicon nitride, may be deposited and/or formed to secure, space and/or protect mechanical structures 20a-d during subsequent processing, including the encapsulation process. In addition, an opening 34 may be etched or formed into second sacrificial layer 32 to provide for subsequent formation of an electrical contact. The opening 34 may be provided using, for example, well known masking techniques (such as a nitride mask) prior to and during deposition and/or formation of second sacrificial layer 32, and/or well known lithographic and etching techniques after deposition and/or formation of second sacrificial layer 32.

[0034] With reference to FIGS. 4D, 4E and 4F, thereafter, first encapsulation layer 28a may be deposited, formed and/or grown on second sacrificial layer 32 (see, FIG. 4D). Advantageously, the thickness of first encapsulation layer 28a in the region overlying second sacrificial layer 32 may be between 0.1 µm and 5.0 µm. The external environmental stress on, and internal stress of first encapsulation layer 28a after etching second sacrificial layer 32 may impact the thickness of first encapsulation layer 28a. Slightly tensile films may self-support better than compressive films which may buckle.

[0035] The first encapsulation layer 28a may be etched to form passages or vents 36 (see, FIG. 4E). Advantageously, the vents have a diameter or aperture size of between 0.1 µm to 2 µm.

[0036] The vents 36 are intended to permit etching and/or removal of at least selected portions of first and second sacrificial layers 30 and 32, respectively (see, FIG. 4F). For example, in one advantageous embodiment, where first and second sacrificial layers 30 and 32 are comprised of silicon dioxide, selected portions of layers 30 and 32 may be removed/etched using well known wet etching techniques and buffered HF mixtures (i.e., a buffered oxide etch) or well known vapor etching techniques using vapor HF. Proper design of mechanical structures 20a-d and sacrificial layers 30 and 32, and control of the HF etching process parameters may permit the sacrificial layer 30 to be sufficiently etched to remove all or substantially all of layer 30 around mechanical elements 20a-d and thereby release elements 20a-d to permit proper operation of MEMS 10.

[0037] In another advantageous embodiment, where first and second sacrificial layers 30 and 32 are comprised of silicon nitride, selected portions of layers 30 and 32 may be removed/etched using phosphoric acid. Again, proper design of mechanical structures 20a-d and sacrificial layers 30 and 32, and control of the wet etching process parameters may permit the sacrificial layer 30 to be sufficiently etched to remove all or substantially all of sacrificial layer 30 around mechanical elements 20a-d which will release mechanical elements 20a-d.

[0038] It should be noted that there are: (1) many suitable materials for layers 30 and/or 32 (for example, silicon dioxide, silicon nitride, and doped and undoped glass-like materials, e.g., phosphosilicate ("PSG") or borophosphosilicate ("BPSG")) and spin on glass ("SOG")), (2) many suitable/associated etchants (for example, a buffered oxide etch, phosphoric acid, and alkali hydroxides such as, for example, NaOH and KOH), and (3) many suitable etching or removal techniques (for example, wet, plasma, vapor or dry etching), to eliminate, remove and/or etch sacrificial layers 30 and/or 32. Indeed, layers 30 and/or 32 may be a doped or undoped semiconductor (for example, polycrystalline silicon, silicon/germanium or germanium) in those instances where mechanical structures 20a-d and contact area 24are the same or similar semiconductors (i.e., processed, etched or removed similarly) provided that mechanical structures 20a-d and contact area 24 are not adversely affected by the etching or removal processes (for example, where structures 20a-d and area 24 are "protected" during the etch or removal process (e.g., an oxide layer protecting a silicon based structures 20a-d) or where structures 20a-d and contact area 24 are comprised of a material that is adversely affected by the etching or removal process of layers 30 and/or 32). Accordingly, all materials, etchants and etch techniques, and permutations thereof, for eliminating, removing and/or etching, whether now known or later developed, are intended to be within the scope of the present invention.

[0039] In addition to forming vents 36, the etching process of first encapsulation layer 28a removes the material overlying contact area 24 to form contact via 38a to facilitate electrical continuity from electrical contact area 24 to a level to or above first encapsulation layer 28a. In this way, additional processing may be avoided, eliminated and/or minimized, for example, processing related to removal of the portion of first encapsulation layer 28a overlying electrical contact area 24 and deposition, formation and/or growth of a suitable material (to provide adequate electrical contact between the various layers of MEMS 10, for example, monocrystalline silicon). Indeed, the resistivity or conductivity of contact via 38 may be adjusted (for example, resistivity reduced and/or conductivity enhanced) using well-known impurity implantation techniques.

[0040] Moreover, contact 24 may remain partially, substantially or entirely surrounded by portions of first and second sacrificial layers 30 and/or 32. For example, with reference to FIG. 4F, while mechanical structures 20a-d are released from their respective underlying oxide columns, a portion 40 of sacrificial layer 32 (i.e., juxtaposed electrical contact area 24 may remain after etching or removing second sacrificial layer 32. This portion of second sacrificial layer 32 may function as an etch stop during later processing. Under this circumstance, it may be advantageous to employ materials for layers 30 and/or 32 that are consistent with the process to form trenches 46a and 46b such that the remaining portions of the second sacrificial layer 32 may function as an etch stop during formation of trenches 44a and 44b. This notwithstanding, layers 30 and/or 32 may be, for example, silicon dioxide, silicon nitride, and doped and undoped glass-like materials, and SOG.

[0041] It should be noted that an insignificant amount of material comprising second sacrificial layer 32 (or little to no second sacrificial layer 32) remains after etching second sacrificial layer 32. As such, materials for layers 30 and/or 32 may be selected with little regard to subsequent processing.

[0042] With reference to FIG. 4G, after releasing mechanical elements 20a-d, a second encapsulation layer 28b is deposited. The second encapsulation layer 28b may be, for example, a silicon-based material (for example, a polycrystalline silicon or silicon-germanium), which is deposited using, for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD, or PECVD). The deposition, formation and/or growth may be by a conformal process or non-conformal process. The material may be the same as or different from first encapsulation layer 28a. However, it may be advantageous to employ the same material to form first and second encapsulation layers 28a and 28b. In this way, for example, the thermal expansion rates are the same and the boundaries between layers 28a and 28b may enhance the "seal" of chamber 26 and enhance the integrity of fluid 42 (for example, maintaining a desired or designed pressure of fluid 42 within chamber 26 over various operating conditions and extended periods of time).

[0043] Advantageously, the second encapsulation layer 28b may be epitaxially deposited using an epitaxy reactor and conditions similar to conventional selective epitaxial silicon growth. This may be in a silane, dichlorosilane, or trichlorosilane process with H2, and/or HCl gases. These processes may typically be run from 600°C to 1400°C.

[0044] Advantageously, the thickness of second encapsulation layer 28b in the region overlying second first encapsulation layer and elements 20a-d may be between 5 µm and 25 µm. Indeed, as MEMS 10, including mechanical structure 12, scale over time and various and/or different materials are implemented, the suitable or necessary thicknesses of first encapsulation layer 28a, second encapsulation layer 28b and combination thereof are likely to change. As such, a ratio of about 1:1 to 1:10 between thicknesses of first encapsulation layer 28a and second encapsulation layer 28b may be advantageous. It is noted, however, that other ratios and thicknesses are clearly suitable (see, for example, FIGS. 9A-9D, 1A-10D and 11A-D).

[0045] As mentioned above, in the present invention, contact area 24 of micromachined mechanical structure 12 is dielectrically isolated from the surrounding conductor and/or semiconductor layers. With reference to FIG. 4H, trenches 46a and 46b may be etched. The trenches 46a and 46b may include a slight taper in order to facilitate the formation of isolation regions 44a and 44b. In this regard, an insulating material may be deposited in trenches 46a and 46b to form dielectric isolation regions 44a and 44b, respectively. The insulating material may be, for example, silicon dioxide, silicon nitride, BPSG, PSG, or SOG. It may be advantageous to employ silicon nitride because silicon nitride may be deposited in a conformal manner. Moreover, silicon nitride is compatible with CMOS processing, in the event that MEMS 10 includes CMOS integrated circuits.

[0046] It may also be advantageous to employ multiple layers of insulation materials, for example, silicon dioxide and silicon nitride or silicon dioxide and silicon. In this way, suitable dielectric isolation is provided in view of manufacturability considerations.

[0047] After formation of dielectric isolation regions 44a and 44b, it may be advantageous to substantially planarize micromachined mechanical structure 12 to provide a "smooth" surface layer and/or (substantially) planar surface using, for example, polishing techniques (for example, chemical mechanical polishing ("CMP")). In this way, the exposed planar surface of micromachined mechanical structure 12 may be a well-prepared base upon which integrated circuits (for example, CMOS transistors) and/or micromachined mechanical structure 12 may be fabricated on or in using well known fabrication techniques and equipment.

[0048] To facilitate integration of high performance integrated circuits in MEMS 10, it may be advantageous to include field region 22 that is comprised of monocrystalline silicon in or on which such circuits may be fabricated. In this regard, with reference to FIG. 5, in an embodiment not being covered by the invention, a portion of first encapsulation layer (i.e., 22a2) and/or second encapsulation layer (i.e., 22a3) that overlies field region 22a1 may be recrystalized thereby "converting" or re-arranging the crystal structure of the polycrystalline material to that of a monocrystalline or substantially monocrystalline material. In this way, transistors or other components of, for example, data processing electronics 16, that are integrated in MEMS 10 may be fabricated in monocrystalline field regions.

[0049] The portion of first encapsulation layer 28a overlying field region 22a1 may be removed, using conventional etching techniques, to expose field region 22a1. Thereafter, monocrystalline silicon may be grown on field region 22a1 to thereby provide field regions 22a2 and/or 22a3.

[0050] The portion of first encapsulation layer 28a overlying field region 22a1 may be etched to expose field region 22a1, which is comprised of monocrystalline structure. Thereafter, transistors or other active components may be integrated in or on field region 22a1 using well-known fabrication techniques.

[0051] With reference to FIGS. 6A-6H, in another set of embodiments not being covered by the invention, monocrystalline structure may be deposited, grown or formed on field region 22a1 and contact area 24 before, concurrently (simultaneously) or after deposition, formation and/or growth of first encapsulation layer 28a. For example, with reference to FIG. 6C, before or after deposition or formation of second sacrificial layer 32, an epitaxially deposited encapsulation layer of monocrystalline silicon field region 22a2 and contact via 38a may be grown to a level that is above or exceeds second sacrificial layer 32. Alternatively, monocrystalline silicon field regions 22a2 and 22b2 are not grown to a level that is above or exceeds second sacrificial layer 32 (not illustrated).

[0052] After growing monocrystalline silicon field region 22a2 and contact via 38a, first encapsulation layer 28a may be deposited, formed and/or grown. The first encapsulation layer 28a may be, for example, a silicon-based material (for example, silicon/germanium, silicon carbide, monocrystalline silicon, polycrystalline silicon or amorphous silicon, whether doped or undoped), germanium, and gallium arsenide (and combinations thereof, which is deposited and/or formed using, for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD, or PECVD). The deposition, formation and/or growth may be by a conformal process or non-conformal process. The material may be the same as or different from first monocrystalline silicon field region 22a2. In the illustrated embodiment, first encapsulation layer 28a is comprised of a polycrystalline silicon material.

[0053] The subsequent processing of micromachined mechanical structure 12 of FIGS. 6D and 6E is substantially similar to that described above with respect to FIGS. 4E and 4F. As such, the discussion above with respect to micromachined mechanical structure 12, in conjunction with FIGS. 4E and 4F, is entirely, fully and completely applicable to this set of embodiments. For the sake of brevity, that description will not be repeated but rather will be summarized.

[0054] Briefly, first encapsulation layer 28a may be etched (see, FIG. 6D) to form passages or vents 36 that are intended to permit etching and/or removal of at least selected portions of first and second sacrificial layers 30 and 32, respectively (see, FIG. 6E). Again, proper design of mechanical structures 20a-d and sacrificial layers 30 and 32, and control of the etch process parameters may permit the sacrificial layer 30 to be sufficiently etched to remove all or substantially all of layer 30 around mechanical elements 20a-d and thereby release mechanical elements 20a-d to permit proper operation of MEMS 10 (see, FIG. 6E).

[0055] After releasing mechanical elements 20a-d, second encapsulation layer 28b may be deposited, formed and/or grown (see, FIG. 6F). Before, concurrently (simultaneously) or after deposition, formation and/or growth of second encapsulation layer 28b, a monocrystalline structure may be deposited, grown or formed on field region 22a2 and contact via 38a.

[0056] The second encapsulation layer 28b may be, for example, a silicon-based material (for example, a monocrystalline silicon, polycrystalline silicon and/or silicon-germanium), which is deposited using, for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD, or PECVD). The deposition, formation and/or growth may be by a conformal process or non-conformal process. The material may be the same as or different from first encapsulation layer 28a. As mentioned above, however, it may be advantageous to employ the same material to form first and second encapsulation layers 28a and 28b in order to enhance the "seal" of chamber 26.

[0057] It should be noted that the materials and/or surfaces underlying first and second encapsulation layer 28a and 28b, as well as the techniques employed to deposit, form and/or grow first and second encapsulation layer 28a and 28b, may initially determine the crystalline structure of the underlying material. For example, in an epitaxial environment having a predetermined set of parameters, the single/mono crystalline structure of encapsulation layers 28a and/or 28b will deposit, form and/or grow in a "retreating" manner (see, FIG. 7A). In contrast, with another predetermined set of parameters, the single/mono crystalline structure of encapsulation layers 28a and/or 28b will deposit, form and/or grow in an "advancing" manner (see, FIG. 7B). The structures and elements herein may be deposited, formed and/or grown in these or other manners. Accordingly, the single/mono crystalline structure (for example, field region 22a2) that is deposited, formed and/or grown on a material having single/mono crystalline structure (for example, field region 22a1) is illustrated as depositing, forming and/or growing in the perpendicular direction (see, for example, FIG. 7C) regardless of the manner or processes of employed.

[0058] It should be further noted that the material comprising second encapsulation layer 28b may deposit, form or grow over surfaces in chamber 26 (for example, the surfaces of mechanical structures 20a-d) as the chamber is sealed or encapsulated. When depositing, forming and/or growing second encapsulation layer 28b, care may need to be taken to preserve the desired integrity of the structures and/or surfaces within chamber 26 (see, for example, FIG. 15).

[0059] Again, the subsequent processing of micromachined mechanical structure 12 of FIGS. 6G and 6H is substantially similar to that described above with respect to FIGS. 4H and 4I. The discussion above with respect to micromachined mechanical structure 12, in conjunction with FIGS. 4E and 4F, is entirely, fully and completely applicable to this set of embodiments. For the sake of brevity, that description will only be summarized.

[0060] The trenches 46a and 46b may be etched (see, FIG. 6G) and an insulating material may be deposited in trenches 46a and 46b to form dielectric isolation regions 44a and 44b, respectively (see, FIG. 6H). The insulating material may be, for example, silicon dioxide, silicon nitride, BPSG, PSG, or SOG. It may be advantageous to employ silicon nitride because silicon nitride may be deposited in a conformal manner. It may also be advantageous to employ multiple layers of insulation materials, for example, silicon dioxide and silicon nitride or silicon dioxide and silicon. In this way, suitable dielectric isolation is provided in view of manufacturability considerations. Moreover, silicon nitride is compatible with CMOS processing, in the event that MEMS 10 includes CMOS integrated circuits.

[0061] After formation of dielectric isolation regions 44a and 44b, it may be advantageous to substantially planarize micromachined mechanical structure 12 to provide a "smooth" surface layer and/or (substantially) planar surface. In this way, the exposed planar surface of micromachined mechanical structure 12 may be well-prepared base upon which integrated circuits (for example, CMOS transistors) and/or micromachined mechanical structure 12 may be fabricated on or in using well known fabrication techniques and equipment.

[0062] With reference to FIGS. 8A-E showing an embodiment not being covered by the invention, dielectric isolation regions 44a and 44b may include a slight taper in order to facilitate the formation of isolation regions 44a and 44b (see, FIG. 8B). In addition, dielectric isolation regions 44a and 44b may include a plurality of materials, including, for example, a first material 44aa (for example, silicon dioxide, silicon nitride, BPSG, PSG, or SOG) and a second material 44ab (for example, a silicon based material, for example, a polycrystalline silicon). In this way, an electrical isolation is provided by way of insulating material 44aa while a limited amount of dielectric is exposed to the surface (see, for example FIGS. 8C-D) of micromachined mechanical structure 12.

[0063] It should be noted that dielectric isolation regions 44a and 44b of FIGS. 8A-E may be employed in any of micromachined mechanical structure 12 described herein. For the sake of brevity, the discussion pertaining to FIGS. 8A-E will not be repeated for each embodiment of micromachined mechanical structure 12.

[0064] Advantageously, vents 36 and trenches 46a and 46b may be formed serially or at the same time. In one embodiment not being covered by the invention, with reference to FIG. 9A, a "thick" deposition of encapsulation layer 28a is deposited, formed and/or grown. The vents 36 may be etched, as described above, to facilitate removal of portions of first and second sacrificial layers 30 and 32 (see, FIG. 9B). The vents 36 may be filled by way of second encapsulation layer. Thereafter, trenches 46a and 46b may be etched (see, FIG. 9C) and filled, (see, FIG. 9D), as described above. Notably, chamber 26 may be "sealed" or encapsulated (FIG. 9C), and dielectric isolation regions 44a and 44b formed (FIG. 9D) using any of the techniques described above.

[0065] In another embodiment not being covered by the invention, dielectric isolation regions 44a and 44b may be formed or completed while processing the "back-end" of the integrated circuit fabrication of MEMS 10. In this regard, with reference to FIG. 10A, during deposition, formation and/or growth of insulation layer 48, trenches 46a and 46b may also be etched and filled to form dielectric isolation regions 44a and 44b. Thereafter, a contact opening 50 is etched to facilitate electrical connection to contact area 24, via contact plug 38a (see, FIG. 10B). A low resistance layer 52 may then be deposited to provide the appropriate electrical connection to contact 24 (see, FIG. 10C).

[0066] Thus, in the embodiment of FIGS. 10A-C, the processing pertaining to the dielectric isolation regions 44a and 44b may be "combined" with the insulating and contact formation step of the "back-end" of the integrated circuit fabrication of MEMS 10. In this way, fabrication costs may be reduced.

[0067] With reference to FIGS. 11A-D, in another set of embodiments not being covered by the invention, first encapsulation layer 28a may be a permeable or semi-permeable material (for example, an amorphous sputtered silicon or porous CVD and/or epitaxial deposited polycrystalline silicon). In this set of embodiments, the process of etching or removing layers 30 and 32 may be performed through the permeable or semi-permeable material comprising layer 28a. Thereafter, when depositing, forming and/or growing second encapsulation layer 28b (for example, polycrystalline silicon) on first encapsulation layer 28a, the material may migrate to, fill and/or occupy the pores of first encapsulation layer 28a. Under this circumstance, relatively little material may deposit on the surfaces of the structures within chamber 26 during deposition, formation and/or growth of second encapsulation layer 28b. As such, chamber 26 may be "sealed" or encapsulated towards the upper surfaces of first encapsulation layer 28a (i.e., the surface that are first exposed to the deposition, formation and/or growth process).

[0068] The processing pertaining to forming dielectric isolation regions 44a and 44b (FIGS. 11C and 11D) may employ any of the techniques described above. For the sake of brevity that discussion will not be repeated.

[0069] It should be noted that it may be advantageous to deposit and form material 40 on the upper surface of contact area 24 that is not removed or etched when layers 30 and 32 are removed during the etching process. In this way, the material disposed next to or near opening 34 is not removed and it may function as an etch stop during processing of trenches 46a and 46b. For example, layers 30 and/or 32 may be a silicon dioxide and material 40 may be a silicon nitride.

[0070] In one embodiment, where the permeable or semi-permeable material is an amorphous sputtered silicon or porous CVD deposited polycrystalline silicon, having a thickness of between 0.1 µm and 2 µm. After etching and/or removal of layers 30 and 32, second encapsulation layer 28b may be a thickness of between 5 µm and 25 µm.

[0071] With reference to FIG. 11B, the material comprised of first encapsulation layer 28a may also be densified and thereby "closed" and chamber 26 "sealed" using an annealing process. That is, in this embodiment, heat treating micromachined mechanical structure 12, after etching first and second sacrificial layers 30 and 32, may cause the material of layer 28a to densify thereby sealing or encapsulating chamber 26. As such, a second encapsulation layer 28b may not be necessary to seal chamber 26.

[0072] With reference to FIG. 12 showing an embodiment not being covered by the invention, the encapsulation process of chamber 26 may include three or more encapsulation layers. The second encapsulation layer 28b and third encapsulation layer 28C (or subsequent/additional layers) may be deposited, formed and/or grown to "seal" chamber 26. In particular, second encapsulation layer 28b may be, for example, a semiconductor material (for example, silicon, silicon carbide, silicon-germanium or germanium) or metal bearing material (for example, silicides or TiW), which is deposited using, for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD or PECVD). The deposition, formation and/or growth may be by a conformal process or non-conformal process. The material comprising encapsulation layer 28b may be the same as or different from first encapsulation layer 28a.

[0073] Thereafter, third encapsulation layer 28c may be deposited, formed and/or grown. The third encapsulation layer 28c may "seal" or close, or more fully "seal" or close chamber 26. The deposition, formation and/or growth of third encapsulation layer 28c may be the same as, substantially similar to, or different from that of encapsulation layers 28a and/or 28b. In this regard, third encapsulation layer 28c may be comprised of, for example, a semiconductor material, an insulator material (for example, silicon nitride or silicon oxide), plastic (for example, photo resist or low-K dielectric) or metal bearing material. The third encapsulation layer 28c may be deposited and/or formed using, for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD or PECVD). The deposition, formation and/or growth process may be conformal or non-conformal.

[0074] It should be further noted that encapsulation layer 28c (see, for example, FIG. 12) may be deposited, formed and/or grown to, for example, provide a more planar surface, an etch stop layer for subsequent processing, an insulation layer, a ground plane, a power plane, and/or enhance the "seal" of chamber 26 and thereby enhance the barrier to diffusion of fluid 42.

[0075] Depending upon the purpose or function of encapsulation layer 28c, it may be, for example, a semiconductor material (for example, a polycrystalline silicon, silicon carbide, silicon/germanium or germanium), an insulator material (for example, silicon dioxide, silicon nitride, BPSG, PSG, or SOG) or metal bearing material (for example, silicides). The encapsulation layer 28c may be, for example, deposited, formed or grown using, for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD or PECVD). The deposition, formation and/or growth may be by a conformal process or non-conformal process. The material comprising encapsulation layer 28c may be the same as or different from the other encapsulation layers.

[0076] The encapsulation process employing three or more layers may be applied to any of micromachined mechanical structure 12 described and illustrated herein. For the sake of brevity, the discussion pertaining to FIG. 12 will not be repeated for each embodiment of micromachined mechanical structure 12.

[0077] The environment (for example, the gas or gas vapor pressure) within chamber 26 determines to some extent the mechanical damping for mechanical structures 20a-d. In this regard, chamber 26 includes fluid 42 that is "trapped", "sealed" and/or contained within chamber 26. The state of fluid 42 within chamber 26 (for example, the pressure) may be determined using conventional techniques and/or using those techniques described and illustrated in non-provisional patent application entitled "Electromechanical System having a Controlled Atmosphere, and Method of Fabricating Same", which was filed on Mar. 20, 2003 and assigned Ser. No. 10/392,528 (hereinafter "the Electromechanical System having a Controlled Atmosphere Patent Application").

[0078] The inventions described and illustrated in the Electromechanical System having a Controlled Atmosphere Patent Application may be implemented with the invention described and illustrated in this application. For example, the encapsulation techniques described above may be implemented with techniques described in the Electromechanical System having a Controlled Atmosphere Patent Application to trap and/or seal a fluid having a selected, desired and/or predetermined state within the chamber. In this way, the fluid provides a desired, predetermined, appropriate and/or selected mechanical damping for mechanical structures within the chamber.

[0079] As another example, the Electromechanical System having a Controlled Atmosphere Patent Application describes a MEMS that includes a plurality of monolithically integrated micromachined mechanical structures having one or more electromechanical systems (for example, gyroscopes, resonators, temperature sensors and/or accelerometers). With reference to FIGS. 13A, in one embodiment, MEMS 10 includes a plurality of micromachined mechanical structures 12a-c that are monolithically integrated on or disposed within substrate 14. Each micromachined mechanical structure 12a-c includes one or more mechanical structures 20a-p (for the sake of clarity only a portion of which are numbered) that are disposed in chambers 26a-d.

[0080] In certain embodiments, chambers 26a-d are sealed or encapsulated using the techniques described above. The chambers 26a-d may be sealed or encapsulated in the same or substantially the same manner or using differing techniques. In this way, the plurality of structures 12a-d may be fabricated in ways that provide the same, substantially the same, different or substantially different desired, predetermined, appropriate and/or selected mechanical damping for mechanical structures 20a-p.

[0081] Indeed, in at least one embodiment, structure 12c includes a plurality of chambers, namely chambers 26c and 26d, each containing fluid 42c and 42d, respectively. The chambers 22c and 22d may be sealed or encapsulated in a manner that fluids 42c and 42d, respectively, are maintained at the same or substantially the same selected, desired and/or predetermined states. As such, in this embodiment, fluids 42c and 42d may provide the same or substantially the same desired, predetermined, appropriate and/or selected mechanical damping for mechanical structures 20h-k and 20l-p, respectively.

[0082] Alternatively, in at least another embodiment, chambers 26c and 26d may be sealed or encapsulated using different or differing techniques such that fluids 24c and 24d may be "trapped", "sealed", maintained and/or contained in chambers 26c and 26d, respectively, at different or substantially different selected, desired and/or predetermined states. In this embodiment, chambers 26c and 26d may be "sealed" using different processing techniques, different processing conditions and/or different materials (for example, gases or gas vapors). As such, after encapsulation, fluids 42c and 42d provide different or substantially different mechanical damping characteristics for mechanical structures 20h-k and 20l-p, respectively. In this way, micromachined mechanical structure 12c may include different electromechanical systems (for example, gyroscopes, resonators, temperature sensors and accelerometers) that require different or substantially different mechanical damping characteristics for optimum, predetermined, desired operation.

[0083] As mentioned above, in one set of embodiments, a monolithic structure may include mechanical structure 12 and data processing electronics 16 and/or interface circuitry 18 that are integrated on or in a common substrate. With reference to FIGS. 14A-14E, MEMS 10 includes micromachined mechanical structure 12, having structures 20a-20d and contact area 24, as well as data processing electronics 16, including integrated circuits 54 disposed in field region 22. As mentioned above, mechanical structures 20a-20d (and contact 24) may be formed from, for example, a single crystalline material (FIGS. 14, 14B and 14E) or a polycrystalline material (FIGS. 14C and 14D). Moreover, contact via 38 may also be formed from, for example, primarily a single crystalline material (FIGS. 14B and 14E) or primarily a polycrystalline material (FIGS. 14A, 14C and 14D).

[0084] It should be noted that mechanical structure 12may be electrically connected to integrated circuits 54 via low resistance layer 52. The integrated circuits 54 may be fabricated using conventional techniques.

[0085] In particular, in those instances where contact 24 is accessed directly by integrated circuitry 54, it may be advantageous to provide a low resistance electrical path. The insulation layer 48 may be deposited, formed and/or grown and patterned to provide or. facilitate interconnection with contact area 24. Thereafter, a low resistance layer 52 (for example, a heavily doped polysilicon or metal such as aluminum, chromium, gold, silver, molybdenum, platinum, palladium, tungsten, titanium, and/or copper) is formed.

[0086] Any and all of the embodiments illustrated and described herein may include multiple layers of mechanical structures, contacts areas and buried contacts that are vertically and/or laterally stacked or interconnected (see, for example, micromachined mechanical structure 12 of FIGS. 13B, 13C and 13D). Moreover, single layer and multiple layers of mechanical structures may be themselves be vertically and/or laterally stacked or interconnected (see, for example, micromachined mechanical structure 12b of FIG. 13A). Further, the resulting micromachined mechanical structure 12 may be integrated with integrated circuitry 54 on a common substrate 14. Any vertical and/or lateral location of micromachined mechanical structure 12, relative to integrated circuitry 54, may be suitable.

[0087] In addition, it should be noted that rather than depositing an insulation material in trenches 46a and 46b, it may be advantageous to deposit an oppositely doped material that would form or create a junction isolation between the contact area and the surrounding conductive materials. In this regard, the material deposited in trenches 46a and 46b may doped with impurities having an opposite conductivity relative to the impurities in first encapsulation layer 28a and/or second encapsulation layer 28b. For example, first encapsulation layer 28a may be doped with boron and the material deposited in trenches 46a and 46b may be doped with phosphorous. In this way, upon completion of the sealing or encapsulation process, junctions surrounding electrical contact area 24 are formed which electrically "isolate" contact area 24 from, for example, field region 22b.

[0088] Micromachined mechanical structure 12 may be substantially planarized using, for example, polishing techniques (for example, chemical mechanical polishing ("CMP")). In this regard, it may be advantageous to remove the layer of material used to fill trenches 46a and 46b that forms on the encapsulation layer(s) so that contact via 38 is electrically isolated by oppositely doped materials.

[0089] Moreover, with reference to FIG. 15, in those instances where the material comprising a second or subsequent encapsulation layer (for example, second encapsulation layer 28b) deposits, forms or grows over selected surfaces of the structures in chamber 26 (for example, the surfaces of mechanical structures 20a-d and field areas 22a and 22b) as chamber 26 is sealed or encapsulated, it may be advantageous to design and fabricate mechanical structures 20a-d to account for the deposition, formation or growth of the additional material. The thickness of the additional material 28b' on the surfaces of mechanical structures 20a-d may be approximately equal to the width or diameter of vent 36. Accordingly, in one set of embodiments, the design (for example, thickness, height, width and/or lateral and/or vertical relation to other structures in chamber 36) of mechanical structures 20a-d incorporates therein such additional material 28b' and the fabrication of mechanical structures 20a-d to provide a final structure includes at least two steps. A first step which fabricates mechanical structures 20a-d according to initial dimensions (for example, as described above with respect to FIGS. 4A and 4B) and a second step that includes the deposition, formation or growth of material 28b' as a result of deposition, formation or growth of at least one encapsulation layer, for example, second encapsulation layer 28b and/or subsequent encapsulation layer.

[0090] The term "depositing" and other forms (i.e., deposit, deposition and deposited) in the claims, means, among other things, depositing, creating, forming and/or growing a layer of material using, for example, a reactor (for example, an epitaxial, a sputtering or a CVD-based reactor (for example, APCVD, LPCVD, or PECVD)).


Claims

1. A method of manufacturing an electromechanical device having mechanical structures (20a, 20b, 20c, 20d) and an electrical contact (24), both overlying a substrate (14), wherein the mechanical structures (20a, 20b, 20c, 20d) reside in a sealed chamber (26), the method comprising:

providing a substrate (14) with a first sacrificial layer (30), an electrical contact (24) and mechanical structures (20, 20b, 20c, 20d), wherein the electrical contact (24) and the mechanical structures (20a, 20b, 20c, 20d) are both disposed on the first sacrificial layer (30);

depositing a second sacrificial layer (32) over the mechanical structures (20a, 20b, 20c, 20d) and at least a portion of the electrical contact (24), directly covering the mechanical structures (20a, 20b, 20c, 20d) and the portion of the electrical contact (24);

forming an opening (34) into the second sacrificial layer (32), wherein the opening (34) is positioned in a portion of the second sacrificial layer (32) which covers the electrical contact (24);

depositing a first encapsulation layer (28a) over the second sacrificial layer (32) filling up the opening (34) for forming a contact via (38a), wherein the first encapsulation layer (28a) consists of a semiconductor material;

forming at least one vent (36) through the first encapsulation layer (28a) to allow removal of at least a portion of the first and second sacrificial layer (30, 32);

removing at least a portion of the first and second sacrificial layer (30, 32) to form the chamber (26), wherein a portion (40) of the second sacrificial layer (32) remains between the chamber (26) and the contact via (38a) so that the contact via (38a) is disposed outside the chamber (26);

sealing the chamber (26) by depositing a second encapsulation layer (28b) on the first encapsulation layer (28a), wherein the second encapsulation layer (28b) consists of a semiconductor material and covers the vent (36) and the contact via (38a);

forming a trench (46a, 46b) in the first and the second encapsulation layer (28a, 28b) around the contact via (38a); and

depositing an insulating material in the trench (46a, 46b) to electrically isolate the electrical contact (24).


 
2. The method of claim 1 wherein the second encapsulation layer (28b) is comprised of polycrystalline silicon, amorphous silicon, silicon carbide, silicon/germanium, germanium, or gallium arsenide.
 
3. The method of claim 2 wherein the first encapsulation layer (28a) is comprised of a polycrystalline silicon, amorphous silicon, germanium, silicon/germanium or gallium arsenide.
 
4. The method of claim 1 further including depositing a semiconductor material in the trench (46a, 46b) after depositing the insulating material.
 
5. The method of claim 1 further including planarizing an exposed surface of the trench (46a, 46b).
 
6. The method of claim 1 wherein the insulating material is silicon dioxide or silicon nitride.
 


Ansprüche

1. Verfahren zur Herstellung eines elektromechanischen Bauelements mit mechanischen Strukturen (20a, 20b, 20c, 20d) und einem elektrischen Kontakt (24), die jeweils auf einem Substrat (14) liegen, wobei sich die mechanischen Strukturen (20a, 20b, 20c, 20d) in einer verschlossenen Kammer (26) befinden, wobei das Verfahren umfasst:

Bereitstellen eines Substrats (14) mit einer ersten Opferschicht (30), einem elektrischen Kontakt (24) und mechanischen Strukturen (20, 20b, 20c, 20d), wobei sowohl der elektrische Kontakt (24) als auch die mechanischen Strukturen (20a, 20b, 20c, 20d) auf der ersten Opferschicht (30) angeordnet sind;

Abscheiden einer zweiten Opferschicht (32) über den mechanischen Strukturen (20a, 20b, 20c, 20d) und zumindest einem Abschnitt des elektrischen Kontakts (24), die die mechanischen Strukturen (20a, 20b, 20c, 20d) und den Abschnitt des elektrischen Kontakts (24) unmittelbar bedeckt;

Bilden einer Öffnung (34) in der zweiten Opferschicht (32), wobei die Öffnung (34) in einem Abschnitt der zweiten Opferschicht (32) platziert ist, der den elektrischen Kontakt (24) bedeckt;

Abscheiden einer ersten Verkapselungsschicht (28a) über der zweiten Opferschicht (32) zum Auffüllen der Öffnung (34) zwecks Bildung einer Durchkontaktierung (38a), wobei die erste Verkapselungsschicht (28a) aus einem Halbleitermaterial besteht;

Bilden mindestens einer Abzugsöffnung (36) durch die erste Verkapselungsschicht (28a) hindurch, damit sich zumindest ein Abschnitt der ersten und zweiten Opferschicht (30, 32) entfernen lässt;

Entfernen von zumindest einem Abschnitt der ersten und zweiten Opferschicht (30, 32) zur Bildung der Kammer (26), wobei ein Abschnitt (40) der zweiten Opferschicht (32) zwischen der Kammer (26) und der Durchkontaktierung (38a) bleibt, sodass die Durchkontaktierung (38a) außerhalb der Kammer (26) angeordnet ist;

Verschließen der Kammer (26) durch Abscheiden einer zweiten Verkapselungsschicht (28b) auf der ersten Verkapselungsschicht (28a), wobei die zweite Verkapselungsschicht (28b) aus einem Halbleitermaterial besteht und die Abzugsöffnung (36) und die Durchkontaktierung (38a) bedeckt;

Bilden eines Grabens (46a, 46b) in der ersten und der zweiten Verkapselungsschicht (28a, 28b) um die Durchkontaktierung (38a) herum; und

Abscheiden eines Isoliermaterials in dem Graben (46a, 46b) zur elektrischen Isolierung des elektrischen Kontakts (24).


 
2. Verfahren nach Anspruch 1, wobei die zweite Verkapselungsschicht (28b) polykristallines Silizium, amorphes Silizium, Siliziumcarbid, Silizium/Germanium, Germanium oder Galliumarsenid umfasst.
 
3. Verfahren nach Anspruch 2, wobei die erste Verkapselungsschicht (28a) ein polykristallines Silizium, amorphes Silizium, Germanium, Silizium/Germanium oder Galliumarsenid umfasst.
 
4. Verfahren nach Anspruch 1, ferner umfassend ein Abscheiden eines Halbleitermaterials im Graben (46a, 46b) nach dem Abscheiden des Isoliermaterials.
 
5. Verfahren nach Anspruch 1, ferner umfassend ein Planarisieren einer freiliegenden Fläche des Grabens (46a, 46b).
 
6. Verfahren nach Anspruch 1, wobei das Isoliermaterial Siliziumdioxid oder Siliziumnitrid ist.
 


Revendications

1. Procédé de fabrication d'un dispositif électromécanique ayant des structures mécaniques (20a, 20b, 20c, 20d) et un contact électrique (24), les deux recouvrant un substrat (14), les structures mécaniques (20a, 20b, 20c, 20d) résidant dans une chambre étanche (26), le procédé comprenant :

la fourniture d'un substrat (14) avec une première couche sacrificielle (30), un contact électrique (24) et des structures mécaniques (20, 20b, 20c, 20d), le contact électrique (24) et les structures mécaniques (20a, 20b, 20c, 20d) étant disposés sur la première couche sacrificielle (30) ;

le dépôt d'une deuxième couche sacrificielle (32) sur les structures mécaniques (20a, 20b, 20c, 20d) et au moins une partie du contact électrique (24), couvrant directement les structures mécaniques (20a, 20b, 20c, 20d) et la partie du contact électrique (24) ;

la formation d'une ouverture (34) dans la deuxième couche sacrificielle (32), l'ouverture (34) étant positionnée dans une partie de la deuxième couche sacrificielle (32) qui recouvre le contact électrique (24) ;

le dépôt d'une première couche d'encapsulation (28a) sur la deuxième couche sacrificielle (32) remplissant l'ouverture (34) pour former un trou d'interconnexion de contact (38a), la première couche d'encapsulation (28a) consistant en un matériau semi-conducteur ;

la formation d'au moins un évent (36) à travers la première couche d'encapsulation (28a) pour permettre l'élimination d'au moins une partie des première et deuxième couches sacrificielles (30, 32) ;

la suppression d'au moins une partie de la première et de la deuxième couche sacrificielle (30, 32) pour former la chambre (26), une partie (40) de la deuxième couche sacrificielle (32) restant entre la chambre (26) et le trou d'interconnexion de contact (38a) de sorte que le trou d'interconnexion de contact (38a) est disposé hors de la chambre (26) ;

l'étanchéification de la chambre (26) par dépôt d'une deuxième couche d'encapsulation (28b) sur la première couche d'encapsulation (28a), la deuxième couche d'encapsulation (28b) étant constituée d'un matériau semi-conducteur et recouvrant l'évent (36) et le trou d'interconnexion de contact (38a) ;

la formation d'une tranchée (46a, 46b) dans les première et deuxième couches d'encapsulation (28a, 28b) autour du trou d'interconnexion de contact (38a) ; et

le dépôt d'un matériau isolant dans la tranchée (46a, 46b) pour isoler électriquement le contact électrique (24).


 
2. Procédé selon la revendication 1, la deuxième couche d'encapsulation (28b) étant constituée de silicium polycristallin, de silicium amorphe, de carbure de silicium, de silicium/germanium, de germanium ou d'arséniure de gallium.
 
3. Procédé selon la revendication 2, la première couche d'encapsulation (28a) étant constituée de silicium polycristallin, de silicium amorphe, de germanium, de silicium/germanium ou d'arséniure de gallium.
 
4. Procédé selon la revendication 1, comprenant en outre le dépôt d'un matériau semi-conducteur dans la tranchée (46a, 46b) après le dépôt du matériau isolant.
 
5. Procédé selon la revendication 1, comprenant en outre la planarisation d'une surface exposée de la tranchée (46a, 46b).
 
6. Procédé selon la revendication 1, le matériau isolant étant du dioxyde de silicium ou du nitrure de silicium.
 




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REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description