(19)
(11)EP 0 257 912 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
23.08.1989 Bulletin 1989/34

(43)Date of publication A2:
02.03.1988 Bulletin 1988/09

(21)Application number: 87307107.0

(22)Date of filing:  11.08.1987
(51)International Patent Classification (IPC)4G11C 11/40
(84)Designated Contracting States:
DE FR GB

(30)Priority: 29.08.1986 JP 203337/86
29.08.1986 JP 203366/86

(71)Applicants:
  • KABUSHIKI KAISHA TOSHIBA
    Kawasaki-shi, Kanagawa-ken 210 (JP)
  • Toshiba Micro-Computer Engineering Corporation
    Kawasaki-shi (JP)

(72)Inventors:
  • Isobe, Matsuo c/o Patent Division
    Minato-ku§Tokyo (JP)
  • Iizuka, Tetsuya c/o Patent Division
    Minato-ku§Tokyo (JP)
  • Aono, Akira c/o Patent Division
    Minato-ku§Tokyo (JP)

(74)Representative: Freed, Arthur Woolf et al
MARKS & CLERK, 57-60 Lincoln's Inn Fields
London WC2A 3LS
London WC2A 3LS (GB)


(56)References cited: : 
  
      


    (54)Static semiconductor memory device


    (57) This invention provides a static semiconductor memory device comprising, a plurality of static memory cells (10) for data storage, bit lines (11A, 11B) connected to the memory cells (10) for transferring data to and from the memory cells (10), a sense amplifier (17) having an input terminal, for amplfying the potential of the bit lines (11A, 11B) when data is transferred from the memory cells (10), and potential lowering device (30A, 30B) connected to the input terminal for lowering the potential of the input terminal of the sense amplifier (17) to a potential corresponding to substantially the optimum sensitivity of the sense amplifier (17) for increasing the speed of data transfer in the memory device.







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