(19)
(11)EP 0 135 699 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
27.09.1989 Bulletin 1989/39

(21)Application number: 84108711.7

(22)Date of filing:  24.07.1984
(51)International Patent Classification (IPC)4G11C 17/00

(54)

FET read only memory cell with with word line augmented precharging of the bit line

Festwertspeicher-FET-Zelle mit vergrösserter Bitleitungsvorladung durch eine Wortleitung

Cellule FET de mémoire morte avec mentation de précharge de ligne de bit par ligne de mot


(84)Designated Contracting States:
AT DE FR GB

(30)Priority: 20.09.1983 US 534035

(43)Date of publication of application:
03.04.1985 Bulletin 1985/14

(73)Proprietor: International Business Machines Corporation
Armonk, N.Y. 10504 (US)

(72)Inventor:
  • Kouba, Daniel J.
    Manassas, VA 22111 (US)

(74)Representative: Louet Feisser, Arnold 
Intellectual Property Department IBM Nederland N.V. Watsonweg 2
1423 ND Uithoorn
1423 ND Uithoorn (NL)


(56)References cited: : 
  
  • IBM TECHNICAL DISCLOSURE BULLETIN, vol. 16, no. 5, October 1973, page 1642, New York, US; H.O. ASKIN: "Single device push-pull read-only storage cell"
  • IBM TECHNICAL DISCLOSURE BULLETIN, vol. 15, no. 8, January 1973, pages 2371,2372, New York, US; P.W. COOK et al.: "Read-only memory fabrication by laser formed connections"
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Field of the invention



[0001] The invention broadly relates to memory circuits and more particularly relates to FET (Field Effect Transistor) semiconductor read only memory circuits.

Background of the invention



[0002] Many FET read only memory circuits have been described in the prior art, wherein a binary one or a binary zero is selectively stored at a particular location at the time of fabrication of the circuit, by permanently altering the conductivity of the FET storage device. For example, the article "Single device push-pull read-only storage cell", published in the IBM Technical Disclosure Bulletin, Vol. 16, No. 5, October 1973, page 1642, describes that the drain regions of FET storage devices can be connected either with a positive potential or alternately with ground, which will cause conductivity in either the push or the pull direction, representing either a stored "1" or a stored "0", when the respective storage devices are read out. A signal on a particular word line which is connected to the gate electrodes of the associated FET devices, renders said devices conductive, providing either an up or a down level output on the associated bit line connected to the source region of the subject FET device.

[0003] A precharging of the y-lines in an array of FET storage devices, before pulsing an x-line for read out of a storage cell, is described in the article "Read-only memory fabrication by laser formed connections", published in the IBM Technical Disclosure Bulletin, Vol. 15, No. 8, January 1973, pages 2371, 2372. When large arrays of such read only memory devices are connected in parallel to a charging node, significant problems can arise due to the leakage of charge from a node during intervening quiescent periods between the precharge stage and the conditional discharge stage. If significant quantities of charge have bled away from a node which is to be sensed for its state to indicate whether a binary one or a binary zero was stored at the accessed location, then the result of that binary sensing can be ambiguous.

Objects of the invention



[0004] It is therefore an object of the invention to provide a more reliable operation for an FET read only memory circuit.

[0005] It is still another object of the invention to provide a more reliable operation for FET read only memory circuits having large numbers of storage devices connected to a charging node or a sensing node.

[0006] It is yet a further object of the invention to provide an improved FET read only memory circuit having a more compact layout than prior art circuits, while also providing for a more reliable operation.

Summary of the invention



[0007] These and other objects, features and advantages of the invention are accomplished by the FET read only memory cell circuit claimed in Claim 1. An FET read only memory cell circuit is disclosed wherein word lines serve to augment the precharging of the bit lines. If an FET read only memory site is preprogrammed as a binary one, for example, then when its word line is pulsed, the bit line will be insured to have an affirmatively high potential, representing a binary one state. This improves the reliability of the operation of the circuit.

Description of the figures



[0008] These and other objects, features and advantages of the invention will be more fully appreciated with reference to the accompanying figures.

Fig. 1 is an overall circuit schematic diagram of the FET read only memory cell circuit with word line augmented precharging of the bit lines.

Fig. 2 is a plan view of the layout of the array of FET read only memory storage cells employed in the circuit shown in Fig. 1.

Fig. 3 is a timing diagram showing the operation of the invention.

Fig. 4 is a cross-sectional view along the section line 4-4' of Fig. 2.

Fig. 5 is a cross-sectional view along the section line 5-5' of Fig. 2.

Fig. 6 is a cross-sectional view along the section line 6-6' of Fig. 2.


Discussion of the preferred embodiment



[0009] Fig. 1 is a circuit schematic diagram of the invention. An array 10 of FET read only memory cells is accessed by a plurality of word lines 1 and 2 disposed in a horizontal direction and a plurality of bit lines A, B, C and D disposed in a vertical direction as shown in Fig. 1. The convention adopted here for naming the FET read only memory devices in the array 10 will be to designate each device as having the reference numeral 20 followed by the identity of the word line and the bit line which access that array device, expressed within parentheses. For example, the FET read only memory array device (20(1,A) refers to the FET array device in the array 10 which is accessed by the word line 1 and the bit line A. Although the array 10 shown in Fig. 1 contains eight devices connected to two word lines and four bit lines, the principle of the invention can be applied to any size read only memory array.

[0010] The bit lines A, B, C and D are respectively connected through FET devices 40(A), 40(B), 40(C) and 40(D) to a positive drain voltage of five volts, for example. A precharge signal PCO is applied to the gates of the precharge FET devices 40(A), 40(B), 40(C) and 40(D) in accordance with the precharge waveform shown in the timing diagram of Fig. 3. This applies a positive precharge potential to the bit lines A, B, C and D, respectively, as is shown by the bit line A voltage waveform in the timing diagram of Fig. 3.

[0011] The FET devices described herein are N channel FET devices. Enhancement mode N channel FET devices require a positive potential difference between the gate and the source in order to conduct current between the drain and the source thereof. N channel enhancement mode FET devices are the type of devices employed in the array 10.

[0012] The threshold voltage for an FET device can be adjusted by means of ion implantation or other well-known techniques so that the potential difference between the gate and the source of the FET device can be selectively made more positive in the case of enhancement mode FET devices, or more negative in the case of depletion mode FET devices. If the threshold voltage of an FET device is selectively adjusted so that conduction starts when there is no potential difference between the gate of the device and its source, then such a device is referred to as a zero threshold or "natural" threshold FET device.

[0013] When current is conducted from the drain to the source of an FET device, the electric potential at the source is reduced from the electric potential at the drain of the device by a quantity substantially equal to the threshold voltage for the device. In order to minimize the reduction in the potential of the bit lines A, B, C and D when they are precharged, the precharge FET devices 40(A), 40(B), 40(C) and 40(D) are fabricated as "natural" threshold FET devices.

[0014] The FET array devices in the array 10 are selectively fabricated to either discharge the respective bit line to which the array device 20 is connected or alternately to not discharge the respective bit line to which it is connected. The convention adopted herein attributes the storage of a binary zero to an FET array device in the array 10 which discharges its bit line. Alternately, the convention herein attributes a binary one to an FET array device in the array 10 which does not discharge its bit line when accessed. The FET array device 20(2,A) has been fabricated to represent a binary zero so that it will discharge its bit line A, when its word line 2 attempts to access it. This is shown in the timing diagram of Fig. 3. Alternately, the device (20(1,A) was fabricated to represent a binary one, and therefore it will not discharge its corresponding bit line A when a signal is received on its word line 1. This is also shown in the timing diagram of Fig. 3.

[0015] The sense amplifier 16 determines whether a binary zero or a binary one was stored at the FET array device in the array 10 which was accessed, by sensing the residual potential on the corresponding bit line. The transfer gates 42(A), 42(B), 42(C) and 42(D) in Fig. 1 respectively connect the bit lines A, B, C and D to the sense amplifier 16. The bit line decoder 14 has two inputs PS6 and PS7 which are decoded when the clock PC1 turns on, so that the decoder 14 outputs an enabling signal to only one of the transfer gates 42(A), 42(B), 42(C) or 42(D) corresponding to the FET array device in the array 10 which is desired to be accessed. Since it is preferred to avoid diminishing the magnitude of the residual potential on a bit line as it passes through its corresponding transfer gate, the transfer gates 42(A), 42(B), 42(C) and 42(D) are "natural" threshold FET devices. When an enabling signal from the bit line decoder 14 is applied to the gate of the transfer gate FET device 42(A), for example, the residual potential on the bit line A will be transferred to the sense amplifier 16 without a diminution in amplitude. The relationship between the time at which the decoder clock PC1 turns on and the signal input to the sense amplifier 16, is shown in the timing diagram of Fig. 3.

[0016] In accordance with the invention, the FET array devices in the array 10 are selectively fabricated to permanently represent a binary one, by selectively connecting the source/drain path of the array device between its corresponding bit line and its corresponding word line. This is shown for the FET array devices 20(1,A), 20(1,C), 20(2,B) and 20(2,D). Alternately, an FET array device in the array 10 can be selectively fabricated to represent a binary zero by connecting the source/drain path of the device between its corresponding bit line and ground potential. This is shown for the FET array devices 20(1,B), 20(1,D), 20(2,A) and 20(2,C).

[0017] For those FET array devices in the array 10 which ae fabricated to represent a binary one, for example, the FET device 20(1,A), the reason for connecting the source/drain path between the corresponding bit line A and the corresponding word line 1, is to provide an additional quantity of charge from the word line during the interval when the word line signal is present, which can pass through the source/drain path of the FET array device and which then is applied to the bit line A so as to replenish any charge on the bit line A which may have inadvertently leaked off subsequent to the precharging of that bit line. This is shown for example in the timing diagram of Fig. 3 where it is seen that the bit line A (as well as all other bit lines) will be precharged during the interval between T6 and T7 and that after this interval, the voltage on the bit line A is seen to gradually decrease. If the voltage on the bit line A were allowed to considerably decrease before the sense amplifier 16 were enabled to sample its magnitude, then the sense amplifier 16 might not be able to distinguish between the relatively higher voltage corresponding to a binary one and the relatively lower voltage corresponding to a binary zero. As is seen in the timing diagram of Fig. 3, when the word line 1 has its enabling signal turn on at time T8, a supplemental current will begin to flow from the word line 1 through the source/drain path of the FET array device 20(1,A) to the bit line A, thereby raising the potential of the bit line A to the desired higher potential representing a binary one. Thereafter, at the later time T9 when the clock signal PC1 enables the bit line decoder 14 and when the transfer gate 42(A) turns on, the amplitude of the signal input to the sense amplifier 16 rises to a fully positive voltage representing a binary one, as is desired. The timing diagram of Fig. 3 illustrates this sequence.

[0018] Thus, in accordance with the invention, an unambiguous positive voltage signal can be applied by the bit line A to the sense amplifier 16 in spite of inadvertent leakage of charge from the bit line A, by virtue of the supplementary charge provided from the word line 1 through the FET array device 20(1,A) to the bit line.

[0019] When an array device in the array 10 has been fabricated to represent a binary zero, as for example the FET array device 20(2,A), a positive going signal on the word line 2 will render the FET array device conductive, thereby providing a current path between the bit line A and ground potential so as to discharge the bit line A. Thereafter, when the bit line decoder 14 enables the transfer gate 42(A), a relatively low potential representing a binary zero will be applied to the sense amplifier 16. This can be seen in the waveforms of the timing diagram of Fig. 3. At the time T1 the precharge signal PCO on line 12 turns on and the voltage on the bit line A rises until the precharge signal PCO turns off at time T2. Thereafter, at time T3, the word line 2 has its signal turned on and the charge stored on the bit line A is then conducted through the FET array device 20(2,A) to ground potential so that the voltage on the bit line A returns to ground potential at time T4, as is shown in the timing diagram of Fig. 3. Thereafter, at time T5 when the clock PC1 turns on, thereby causing the bit line decoder 14 to turn on the transfer gate 42(A), the ground potential on the bit line A is transferred to the sense amplifier 16 and a binary zero value is read.

[0020] The structure of the FET array devices in the array 10 is shown to better advantage in the sequence of Figs. 2, 4, 5 and 6. Fig. 2 is a layout diagram of the FET array devices in the array 10 which are shown in the electrical schematic diagram of Fig. 1. Detailed cross-sectional views of the FET array devices 20(1,A) and 20(2,A) are shown in the cross-sectional view of Figs. 4, 5 and 6.

[0021] The entire circuit shown in Fig. 1 can be fabricated on a single integrated circuit chip. The integrated circuit is formed on a P-type silicon substrate 31. As is seen in the cross-sectional diagram of Fig. 4, the FET array devices 20(1,A) and 20(2,A) are formed by the N-type diffusions 32, 36 and 34 which are formed in the P-type substrate 31. The FET array devices to be formed are metal oxide semiconductor (MOS) FET devices wherein polycrystalline silicon gate electrodes 1' and 2' are formed on top of a thin gate insulator layer 50 and then the N-type doped regions 32, 36 and 34 are formed in the P-type substrate 31 by either diffusion or ion implantation techniques, as are well-known in the prior art. In the preferred embodiment, two additional levels of metal interconnection lines which are mutually orthogonal and insulated from each other are applied above the layer of polycrystalline silicon within which have been formed the gate electrodes 1' and 2'. After suitable interconnections have been patterned and interlevel via connections have been made, the entire assembly is encapsulated in an insulating medium 35 which can be silicon dioxide, polyimide, or other suitable insulating medium.

[0022] Fig. 4 is a cross-section along the section line 4-4' of Fig. 2 and shows that the word line 1 is parallel to and lies above the gate electrode 1' for the FET array device 20(1,A). The cross-sectional view in Fig. 5 along the section line 5-5' of Fig. 2 shows that the polycrystalline silicon gate electrode 1' is electrically connected by means of the interlevel via connection 44 to the metal word line 1. Thus it is seen that the word line 1 is electrically connected to the polycrystalline silicon gate electrode 1' of the FET array device 20(1,A). In a similar manner, the word line 2 is a metal line which is part of the first level metal layer of which the word line 1 is a member, and lies parallel to and above the polycrystalline silicon gate electrode 2' of the FET array device 20(2,A). The cross-sectional view of Fig. 5 shows that polycrystalline silicon gate electrodes 2' is electrically connected by means of the interlevel via connection 46 to the word line 2. The ground lines 22 and 24 are also patterned lines which are parallel to the word lines 1 and 2 and are also members of the first level metal layer out of which the word lines 1 and 2 are formed.

[0023] The central N-type doped region 36 which is shared by both devices 20(1,A) and 20(2,A), is connected by means of the interlevel metal via connection 48 and the tab 30 to the bit line A, as shown in Fig. 6.

[0024] In accordance with the invention, since a binary one representation is desired to be fabricated into the FET array device 20(1,A), the interlevel metal via connection 52 which contacts the N-type doped region 32, is selectively connected by means of the tab 26 to the word line 1 (and not to the ground line 22). The tab 26 is formed out of the first level metal layer from which the word line 1 is formed. As was described above, after the precharge signal PCO has turned off at time T7, charge begins to leak off of the bit line A and this reduced potential is applied over the tab 30 and the via interconnection 48 to the N-type doped region 36. Then at time T8 when the word line 1 goes positive, the positive going word line signal is applied by the tab 26 and the via interconnection 52 to the N-type doped region 32. Since the positive going word line signal on the word line 1 is also applied by means of the via 44 to the gate electrode 1', the N-type region 32 behaves as a drain and the N-type region 36 behaves as the source of the FET array device 20(1,A), so that a supplementary current is conducted from the word line 1 and the N-type region 32 to the N-type region 36 and the bit line A, thereby compensating for the lost charge on the bit line A, as described above.

[0025] Further in accordance with the invention, since a binary zero representation is desired to be fabricated for the FET device 20(2,A), the interlevel metal via connection 54 connecting to the N-type doped region 34 is selectively connected by means of the tab 28 to the ground line 24 (and not to the word line 2). The tab 28 is formed out of the same first level metal layer as was the ground line 24. Thus, at time T2 of the timing diagram of Fig. 3, the bit line A has a positive potential which is applied to the N-type region 36 and the ground potential of the ground line 24 is applied to the N-type region 34. Then, at the time T3 the potential of the word line 2 goes positive and this is applied through the via 46 to the gate electrode 2' of the array device 20(2,A). Since the N-type region 36 is more positive than the N-type region 34, the N-type region 36 behaves as a drain and the N-type region 34 behaves as a source so that current flows from the bit line A through the N-type region 36 to the N-type region 34 and then to the ground line 24, thereby discharging the bit line A, as described above.

[0026] It is seen from the layout diagram of Fig. 2, that the array 10 of FET read only memory devices is quite compact and represents a very high storage density. This increase in storage density is achieved in part by the connection of the source/ drain path between the word line and the bit line for those FET array devices storing a binary one representation. In the prior art, those FET array devices representing a binary one have their source/drain paths connected between the bit line and the five volt drain potential for the chip. This required running additional drain voltage lines through the array in order to enable such connection to be selectively made. The addition of extra drain voltage lines increased the overall area which had to be occupied by an array of a given information content. This requirement is completely eliminated by the invention disclosed herein, there being no necessity to run extra drain voltage lines through the array.

[0027] Although the preferred embodiment described herein uses N channel FET devices and has provided for "natural" threshold FET devices as the precharge devices 40(A) through 40(D) and also has provided for "natural" threshold devices for the transfer gates 42(A) through 42(D), other types of FET devices and technologies can be employed within the scope of the invention disclosed herein. The precharge FET devices 40(A) through 40(D) can be enhancement mode devices, for example. The transfer gate devices 42(A) through 42(D) can also be enhancement mode devices. Still further, the invention disclosed herein can also be embodied in complementary MOSFET devices, for example using P channel FET devices for the precharge FET devices 40(A) through 40(D) and N channel FET array devices for the array 10 and for the transfer gates 42(A) through 42(D). Although the word lines 1 and 2 are disclosed herein as being metal lines which are part of the first level metal layer, this embodiment was selected because metal is a better conductor than polycrystalline silicon of which the gate electrodes 1' and 2' are composed. However, it is within the scope of this invention to rely solely on the polycrystalline silicon gate electrodes 1' and 2' as the word lines for the array 10. Still further, although a single layer of polycrystalline silicon was disclosed, double layer polycrystalline silicon technologies would also be within the scope of the invention disclosed herein.

[0028] Although a specific embodiment of the invention has been disclosed, it will be understood by those having skill in the art that the foregoing and other changes in form and details may be made therein without departing from the scope of the invention as defined in the appended claims.


Claims

1. FET read only memory array (10) including a plurality of FET array devices (20) accessed by a plurality of word lines (1, 2) and outputting stored signals on a plurality of bit lines (A-D), comprising:

a first one of said FET array devices (20(1,A)) having its gate (1') connected to a first word line (1) and its source/drain path connected for representing a first stored information state;

a second one of said FET array devices (20(1,B)) having its gate (1') connected to a first word line (1) and its source/drain path connected between one of said bit lines (B) and a reference potential (22, ground level), for representing a second stored information state;


precharge means (40) connected to said bit lines (A-D), for initially providing electrical charge to each bit line;
characterized by:

said first one of said FET array devices (20(1,A)) having its source/drain path connected between one of said bit lines (A) and said first word line (1);

said first word line (1) when selected providing a supplementary charge to said one bit line (A) through said source/drain path of said first FET device (20(1,A)).


 
2. The apparatus of claim 1 wherein:

said first one of said FET array devices (20(1,A)) has its source/drain path connected between a first one of said bit lines (A) and a first one of said word lines (1) and its gate connected to said first word line (1), for representing a first stored information state; and

another one of said FET array devices (20(2,A)) has its source/drain path connected between said first one of said bit lines (A) and a reference potential (24, ground level) and its gate connected to a second one of said word lines (2), for representing a second stored information state.


 
3. FET read only memory array according to a previous claim wherein:

any one in a selected first set of said FET array devices (20) has its source/drain path selectively connected between a respective one of said bit lines and a respective one of said word lines and its gate connected to a respective one word line, for representing a first stored information state;

precharge means are connected to said bit lines, for providing electrical charge to each said bit line; and

said respective word line provides a supplementary charge to said bit line through said source/drain path of said any one FET device in said first information state; and

any one in a complementary second set of said FET array devices having its source/drain path alternately connected between said respective one of said bit lines and a reference potential, for representing a second stored information state.


 
4. The apparatus of claim 3 which further comprises:

a respective reference conductor line (22, 24) disposed proximate to any one FET device in said array, for selective connection to said reference potential;

a conductor tab (26) connected to the side of said source/drain path, of said any one FET device in said first set, opposite from said respective bit line and selectively connected to said respective word line (1) to store said first information state;

said conductor tab for any one FET device in said second set alternately (28) being connected to said respective reference potential line (24) to store said second information state.


 
5. The apparatus of any preceding claim wherein said precharge means comprises:

a first zero threshold voltage FET device (40(A)) connected between said respective bit line (A) and a second reference potential.


 
6. The apparatus of claim 5 which further comprises:

a second zero threshold voltage FET device (42(A)) connected between said respective bit line (A) and a sensing means (16), for outputting the voltage corresponding to the stored information state of said any one FET device in said array.


 
7. FET read only memory array according to any previous claim, including a plurality of FET array devices, each said array device being connected to one of a plurality of bit lines which are precharged to a first potential state during a first interval, each said array device being connected to one of a plurality of word lines which applies substantially said first potential during a second interval following said first interval, rendering the respective array device conductive, characterized by:

a first one, belonging to a first predetermined set of said FET array devices having its source connected to a first one of said bit lines, having its gate connected to a first one of said word lines, and having its drain connected to said first word line, representing a first binary state stored by said first array device, said first potential on said first word line serving to augment said precharged state of said first bit line during said second interval so that said first bit line remains at substantially said first potential during a sensing interval following said second interval;

a second one, belonging to the complementary set to the said first predetermined set of FET array devices having its drain connected to a second one of said bit lines, having its gate connected to a second one of said word lines, and having its source selectively connected to a second potential different from said first potential, representing a second binary state stored by said second array device, said second array device discharging said second bit line during said second interval so that said second bit line assumes substantially said second potential during said sensing interval;


whereby the effects of charge leaking from said bit lines can be minimized.
 


Ansprüche

1. Festwertspeicher-FET-Anordnung (10) die eine Vielzahl von FET-Zellen (20) aufweist, auf die über eine Vielzahl von Wortleitungen (1, 2) zugegriffen wird und welche gespeicherte Signale auf einer Vielzahl von Bitleitungen (A-D) ausgeben, wobei:

bei einer ersten dieser FET-Zellen (20(1,A)) deren Gate (1') an eine erste Wortleitung (1) angeschlossen ist und ihr Souce-Drain-Pfad zur Darstellung eines ersten gespeicherten Informationszustandes geschaltet ist

bei einer zweiten dieser FET-Zellen (20(1,B)) deren Gate (1') an eine erste Wortleitung (1) angeschlossen ist und ihr Source-Drain-Pfad zwischen eine der Bitleitungen (B) und ein Referenzpotential (22, Nullpegel) geschaltet ist, um einen zweiten gespeicherten Informationszustand dazustellen, und


an die Bitleitungen (A-D) Vorladungsmittel (40) geschaltet sind, um jede Bitleitung anfänglich mit elektrischer Ladung zu versorgen,
dadurch gekennzeichnet, daß

,bei der ersten dieser FET-Zellen (20(1,A)) ihr Source-Drain-Pfad zwischen eine der Bitleitungen (A) und die erste Wortleitung (1) geschaltet ist und

die erste Wortleitung (1), über den Source- Drain-Pfad der ersten FET-Zelle (20(1,A)) eine zusätzliche Ladung für die erste Bitleitung (A) zur Verfügung stellt.


 
2. Vorrichtung nach Anspruch 1, bei welcher bei der ersten der FET-Zellen (20(1,A)) deren Source-Drain-Pfad zwischen eine erste der Bitleitungen (A) und eine erste der Wortleitungen (1) und ihr Gate an die erste Wortleitung (1) geschaltet ist, um einen ersten gespeicherten Informationszustand darzustellen, und
bei einer anderen der FET-Zellen (20(2,A)) ihr Source-Drain-Pfad zwischen die erste der Bitleitungen (A) und ein Referenzpotential (24, Nullpegel) und ihr Gate an eine zweite der Wortleitungen (2) geschaltet ist, um einen zweiten gespeicherten Informationszustand darzustellen.
 
3. Festwertspeicher FET-Anordnung nach einem vorhergehenden Anspruch, bei welcher

bei jeder Zelle aus einem ausgewählten ersten Satz dieser FET-Zellen (20) ihr Source-Drain-Pfad selektiv zwischen eine entsprechende der Bitleitungen und eine entsprechende der Wortleitungen geschaltet ist, um einen ersten gespeicherten Informationszustand darzustellen.

Vorladungsmittel an diese Bitleitungen angeschlossen sind, um jede der Bitleitungen mit elektrischer Ladung zu versorgen, wobei die entsprechende Wortleitung über den Source-Drain-Pfad jeder dieser FET-Zellen in dem ersten Informationszustand eine zusätzliche Ladung für die Bitleitung zur Verfügung stellt, und

bei jeder Zelle aus einem komplementären zweiten Satz dieser FET-Zellen ihr Source-Drain-Pfad wechselweise zwischen eine entsprechende der Bitleitungen und ein Referenzpotential geschaltet ist, um einen zweiten gespeicherten Informationszustand darzustellen.


 
4. Vorrichtung nach Anspruch 3, die weiters enthält:

einen entsprechenden Referenzleiter (22, 24) der zur selektiven Verbindung mit dem Referenzpotential nahe jeder FET-Zelle in der Anordnung angeordnet ist, einen Leiterlappen (26), der an die Seite des Source-Drain-Pfades jeder der FET-Zellen in dem ersten Satz angeschlossen ist, gegenüberliegend der zugehörigen Bitleitung und selektiv an die zugehörige Wortleitung (1) geschaltet um den ersten Informationszustand zu speichern,

wobei der Leiterlappen bei jeder FET-Zelle in dem zweiten Satz wechselweise (28) mit dem zugehörigen Referenzpotentialleiter (24) verbunden ist, um den zweiten Informationszustand zu speichern.


 
5. Vorrichtung nach irgendeinem der vorgehenden Ansprüche, bei welchem die Vorladungsmittel aufweisen:

eine erste Null-Schwellwertspannungs-FET-Einrichtung (40(A)), die zwischen die zugehörige Bitleitung (A) und ein zweites Referenzpotential geschaltet ist.


 
6. Vorrichtung nach Anspruch 5, die weiters aufweist:

eine zweite Null-Schwellwertspannungs-FET-Einrichtung (42(A)), die zwischen die zugehörige Bitleitung (A) und eine Abtasteinrichtung (16) geschaltet ist, zur Ausgabe der Spannung, welche dem gespeicherten Informationszustand jeder der FET-Zellen in der Anordnung entspricht.


 
7. Festwertspeicher-FET-Anordnung nach irgendeinem der vorgehenden Ansprüche, mit einer Vielzahl von FET-Zellen, wobei jede dieser Zellen mit einer aus einer Vielzahl von Bitleitungen verbunden ist, die während eines ersten Intervalls auf einen ersten Potentialzustand vorgeladen sind und jede dieser Zellen mit einer aus einer Vielzahl von Wortleitungen verbunden ist, welche im wesentlichen das erste Potential während eines zweiten, auf das erste Intervall folgenden Intervalls anlegt und die zugehörige Zelle in den leitenden Zustand versetzt, gekennzeichnet durch:

eine erste, zu einem ersten festgelegten Satz der FET-Zellen gehörige Zelle, deren Source mit einer ersten der Bitleitungen verbunden ist, deren Gate mit einer ersten der Wortleitungen verbunden ist, und deren Drain mit der ersten Wortleitung verbunden ist, wobei ein erster, in dieser ersten Zelle gespeicherter binärer Zustand dargestellt wird und das erste Potential auf der ersten Wortleitung zur Vergrößerung des vorgeladenen Zustandes der ersten Bitleitung während des zweiten Intervalls dient, sodaß die erste Bitleitung während eines auf das zweite Intervall folgenden Abtastintervalls im wesentlichen auf dem ersten Potential verbleibt,

eine zweite, zu dem ersten festgelegten Satz der FET-Zellen komplimentären Satz gehörige Zelle, deren Drain mit einer zweiten der Bitleitungen verbunden ist, deren Gate mit einer zweiten der Wortleitungen verbunden ist und deren Source selektiv mit einem zweiten, von dem ersten Potential verschiedenen Potential verbunden ist, wobei ein zweiter, in dieser zweiten Zelle gespeicherter binärer Zustand dargestellt wird und die zweite Zelle während des zweiten Intervalls die zweite Bitleitung entlädt, sodaß während des Abtastintervalls die zweite Bitleitung im wesentlichen das zweite Potential annimmt,


wodurch die Effekte von Ladungsleckverlusten von den Bitleitungen minimalisiert werden.
 


Revendications

1. Réseau de mémoire morte FET (10) comprenant une pluralité de dispositifs de réseau FET (20) accédés par une pluralité de lignes de mot (1, 2) et fournissant des signaux stockés, sur une pluralité de lignes de bit (A-D), dans lequel:

un premier desdits dispositifs de réseau FET (20(1,A)) est connecté par sa grille (1') à une première ligne de mot (1) et est connecté par son chemin de source/drain de manière à représenter un premier état d'information stocké;

un deuxième desdits dispositifs de réseau FET (20(1,B)) est connecté par sa grille (1') à une première ligne de mot (1) et est connecté par son chemin de source/drain entre une desdites lignes de bit (B) et un potentiel de référence (22, potentiel de terre), de manière à représenter un deuxième état d'information stocké;


des moyens de précharge (40) sont connectés aux dites lignes de bit (A, D), pour fournir initialement une charge électrique à chaque ligne de bit;
caractérisé en ce que:

ledit premier desdits dispositifs de réseau FET (20(1,A)) est connecté, à son chemin de source/ drain, entre une desdites lignes de bit (A) et ladite première ligne de mot (1);

ladite première ligne de mot (1) fournit une charge supplémentaire à ladite ligne de bit (A) par l'intermédiaire dudit chemin de source/drain dudit premier dispositif FET (20(1,A)).


 
2. Appareil suivant la revendication 1, dans lequel:

ledit premier desdits dispositifs de réseau FET (20(1,A)) a son chemin de source/drain connecté entre une première desdites lignes de bit (A) et une première desdites lignes de mot (1) et sa grille connectée à ladite première ligne de mot (1), pour représenter un premier état d'information stocké; et

un autre desdits dispositifs de réseau FET (20(2,A)) a son chemin de source/drain connecté entre ladite première des lignes de bit (A) et un potentiel de référence (24, potentiel de terre) et sa grille connectée à une deuxième desdites lignes de mot (2), pour représenter un deuxième état d'information stocké.


 
3. Réseau de mémoire morte FET suivant une revendication précédente, dans lequel:

un dispositif quelconque dans un premier ensemble choisi dedits dispositifs de réseau FET (20) a son chemin de source/drain sélectivement connecté entre une ligne respective desdites lignes de bit et une ligne respective desdites lignes de mot et sa grille connectée à une ligne de mot respective, pour représenter un premier état d'information stocké;

des moyens de précharge sont connectés aux- dites lignes de bit, pour fournir une charge électrique à chaque dite ligne de bit; et

ladite ligne de mot respective fournit une charge supplémentaire à ladite ligne de bit par l'intermédiaire dudit chemin de source/drain dudit dispositif FET quelconque dans ledit premier état d'information; et

un dispositif quelconque dans un deuxième ensemble complémentaire dedits dispositifs de réseau FET a son chemin de source/drain connecté alternativement, entre ladite ligne respective desdites lignes de bit et un potentiel de référence, pour représenter un deuxième état d'information stocké.


 
4. Appareil suivant la revendication 3, qui comprend en outre:

une ligne conductrice de référence respective (22, 24) disposée à proximité d'un dispositif FET quelconque dans ledit réseau, pour une connexion sélective audit potentiel de référence;

une languette conductrice (26) connectée au côté dudit chemin de source/drain dudit dispositif FET quelconque dudit premier ensemble, à l'opposé de ladite ligne de bit respective, et sélectivement connectée à ladite ligne de mot respective (1) pour stocker ledit premier état d'information;


ladite languette conductrice pour un dispositif FET quelconque dudit deuxième ensemble étant connectée d'autre part (28) à ladite ligne de potentiel de référence respective (24), pour stocker ledit deuxième état d'information.
 
5. Appareil suivant l'une quelconque des revendications précédentes, dans lequel lesdits moyens de précharge comprennent:

un premier dispositif FET à tension de seuil nulle (40(A)) connecté entre ladite ligne de bit respective (A) et un deuxième potentiel de référence.


 
6. Appareil suivant la revendication 5, qui comprend en outre:

un deuxième dispositif FET à tension de seuil nulle (42(A)) connecté entre ladite ligne de bit respective (A) et des moyens de détection (16), pour sortir la tension correspondant à l'état d'information stocké dudit dispositif FET quelconque dudit réseau.


 
7. Réseau de mémoire morte FET suivant l'une quelconque des revendications précédentes, comprenant une pluralité de dispositifs de réseau FET, chaque dit dispositif de réseau étant connecté à l'une d'une pluralité de lignes de bit qui sont préchargées à un premier état de potentiel pendant un premier intervalle, chaque dit dispositif de réseau étant connecté à l'une d'une pluralité de lignes de mot qui applique sensiblement ledit premier potentiel pendant un deuxième intervalle suivant ledit premier intervall, rendant conducteur le dispositif de réseau respectif, caractérisé en ce que:

un premier dispositif, appartenant à un premier ensemble prédéterminé de dits dispositifs de réseau FET, a sa source connectée à une première desdites lignes de bit, a sa grille connectée à une première desdites lignes de mot, et a son drain connecté sélectivement à ladite première ligne de mot, représentant un premier état binaire stocké par ledit premier dispositif de réseau, ledit premier potentiel sur ladite première ligne de mot servant à augmenter ledit état préchargé de ladite première ligne de bit pendant ledit deuxième intervalle de sorte que ladite première ligne de bit reste sensiblement audit premier potentiel pendant un intervalle de détection suivant ledit deuxième intervalle;

un deuxième dispositif, appartenant à l'ensemble complémentaire audit premier ensemble prédéterminé dedits dispositifs de réseau FET, a son drain connecté à une deuxième desdites lignes de bit, a sa grille connectée à une deuxième desdites lignes de mot, et a sa source sélectivement connectée à un deuxième potentiel différent dudit premier potentiel, représentant un deuxième état binaire stocké par ledit deuxième dispositif de réseau, ledit deuxième dispositif de réseau déchargeant ladite deuxième ligne de bit pendant ledit deuxième intervalle de sorte que ladite deuxième ligne de bit prend sensiblement ledit deuxième potentiel pendant ledit intervalle de détection;


de sorte que les effets de fuite de charge à partir desdites lignes de bit peuvent être minimisés.
 




Drawing