(19)
(11)EP 1 760 885 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
25.03.2020 Bulletin 2020/13

(21)Application number: 06008842.4

(22)Date of filing:  27.04.2006
(51)International Patent Classification (IPC): 
H03K 3/356(2006.01)
H03K 5/133(2014.01)
H03K 5/00(2006.01)
H03K 5/07(2006.01)
H03K 5/145(2006.01)

(54)

Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth

Stromgesteuerte CMOS (C3MOS) vollständig differentielle integrierte Verzögerungszelle mit variabler Verzögerung und hoher Bandbreite

Cellule à retard intégrée complètement différentielle en CMOS (C3MOS) contrôlée en courant avec un retard variable


(84)Designated Contracting States:
DE FR GB

(30)Priority: 28.12.2005 US 320401
06.09.2005 US 714814 P

(43)Date of publication of application:
07.03.2007 Bulletin 2007/10

(73)Proprietor: Avago Technologies International Sales Pte. Limited
Singapore 768923 (SG)

(72)Inventor:
  • Cao, Jun
    Irvine, CA 94087 (US)

(74)Representative: Bosch Jehle Patentanwaltsgesellschaft mbH 
Flüggenstraße 13
80639 München
80639 München (DE)


(56)References cited: : 
EP-A- 1 420 511
US-A- 5 945 847
US-A1- 2005 110 525
US-A- 4 727 424
US-A1- 2005 015 638
US-B1- 6 911 857
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND OF THE INVENTION


    TECHNICAL FIELD OF THE INVENTION



    [0001] The invention relates generally to the field of communication devices; and, more particularly, it relates to the field of delay cells that can be implemented within such communication devices.

    DESCRIPTION OF RELATED ART



    [0002] Data communication systems have been under continual development for many years. In many broadband data communication system application, variable delay cells are employed. In such application, it is oftentimes desirable to adjust timing control between various components. One such possible implementation of a delay cell is within the context of a delay locked loop (DLL). A common approach to design a DLL is to employ a number of delay blocks. In the prior art, each of the individual delay blocks can be undesirably power consumptive. It would be desirable to have a delay block design that is more energy efficient.

    [0003] US 5,945,847 discloses a high speed logic module including a differential input formed as a pair of inductive transmission lines and a differential output also formed as a pair of inductive transmission lines.

    [0004] US 2005/015638 A1 discloses a delay circuit to delay storage of data in a data storage circuit in response to receiving a timing signal.

    [0005] US 2005/110525 A1 discloses a current-mode logic (CML) circuit that can operate stably even with low voltage power supply.

    [0006] EP 1 420 511 A1 discloses methods and circuits for phase detectors having extended linear and monotonic ranges of operation.

    [0007] US 4727424 discloses a sampled data filter employing a single chain of cascaded delay elements.

    [0008] For appropriate alignment and control of the various components within a communication system, it is very often desirable to ensure have some means by which the various signal therein can be adjusted to ensure proper alignment and timing. As such, there has been and continues to be a need for better and more efficient means by which delay cells may be implemented within communication systems and within various communication devices within such communication systems.

    BRIEF SUMMARY OF THE INVENTION



    [0009] The present invention is defined by independent claim 1 and is directed to an apparatus that is further described in the following Brief Description of the Several Views of the Drawings, the Detailed Description of the Invention, and the claims.

    [0010] According to an example, a current-controlled CMOS (C3MOS) wideband variable delay cell circuit is provided, the circuit comprising:

    a first differential transistor comprising a first source, a first gate, and a first drain;

    a second differential transistor comprising a second source, a second gate, and a second drain;

    a first current source that is coupled to the first source of the first differential transistor and to the second source of the second differential transistor;

    a first input impedance that is coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor;

    a second input impedance that is coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor;

    a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, that is coupled between the first drain of the first differential transistor and a supply voltage;

    a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, that is coupled between the second drain of the second differential transistor and the supply voltage;

    a third differential transistor comprising a third source, a third gate, and a third drain;

    a fourth differential transistor comprising a fourth source, a fourth gate, and a fourth drain;

    a second current source that is coupled to the third source of the third differential transistor and to the fourth source of the fourth differential transistor;

    wherein the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are communicatively coupled; and

    wherein the second drain of the second differential transistor, the fourth drain of the third differential transistor, and the third gate of the fourth differential transistor are communicatively coupled.



    [0011] Advantageously, the circuit further comprises:

    a first capacitor that is coupled between the first drain of the first differential transistor and the second gate of the second differential transistor; and

    a second capacitor that is coupled between the second drain of the second differential transistor and the first gate of the first differential transistor.



    [0012] Advantageously:

    the first input impedance comprises a first series inductor; and

    the second input impedance comprises a second series inductor.



    [0013] Advantageously:

    the first output resistor of the first output impedance is coupled between the first drain of the first differential transistor and the first shunt peaking inductor of the first output impedance; and

    the first shunt peaking inductor of the first output impedance is coupled between the first output resistor of the first output impedance and the supply voltage.



    [0014] Advantageously:

    the first current source is a first current source transistor;

    the second current source is a second current source transistor; and

    the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first current source transistor, and the second current source transistor comprise NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.



    [0015] Advantageously:

    the first current source is a first current source transistor;

    the second current source is a second current source transistor; and

    the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first current source transistor, and the second current source transistor comprise PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors.



    [0016] Advantageously:

    the first current source is a first variable current source;

    the second current source is a second variable current source; and

    a variable delay of the C3MOS wideband variable delay cell circuit is controlled by adjusting at least one of a first current in the first variable current source and a second current in the second variable current source.



    [0017] Advantageously:
    a delay of the C3MOS wideband variable delay cell circuit is a function of a ratio of a first current in the first current source divided by a sum comprising the first current in the first current source and the second current in the second current source.

    [0018] Advantageously:
    the C3MOS wideband variable delay cell circuit is one delay cell of a plurality of delay cells implemented within an n-tap finite impulse response (FIR) filter.

    [0019] According to an example, a current-controlled CMOS (C3MOS) wideband variable delay cell circuit is provided, the circuit comprising:

    a wideband differential transistor pair comprising a first differential input, a second differential input, a first differential output, and a second differential output;

    a first current source that is operable to provide current to the wideband differential transistor pair;

    a cross-coupled differential transistor pair comprising a third differential input, a fourth differential input, a third differential output, and a fourth differential output;

    a second current source that is operable to provide current to the cross-coupled differential transistor pair;

    a first input impedance that communicatively couples a first differential input signal to the first differential input of the wideband differential transistor pair;

    a second input impedance that communicatively couples a second differential input signal to the second differential input of the wideband differential transistor pair;

    a first output impedance that communicatively couples the first differential output of the wideband differential transistor pair to a power supply voltage;

    a second output impedance that communicatively couples the second differential output of the wideband differential transistor pair to the power supply voltage;

    wherein the second differential output of the wideband differential transistor pair, the third differential input of the cross-coupled differential transistor pair, and the third differential output of the cross-coupled differential transistor pair are communicatively coupled;

    wherein the first differential output of the wideband differential transistor pair, the fourth differential input of the cross-coupled differential transistor pair, and the fourth differential output of the cross-coupled differential transistor pair are communicatively coupled;

    wherein a variable delay of the C3MOS wideband variable delay cell circuit is controlled by adjusting at least one of a first current in the first current source and a second current in the second current source.



    [0020] Advantageously:
    a delay of the C3MOS wideband variable delay cell circuit is a function of a ratio of a first current in the first current source divided by a sum comprising the first current in the first current source and the second current in the second current source.

    [0021] According to an example:

    the wideband differential transistor pair comprises:

    a first differential transistor comprising a first source, a first gate that comprises the first differential input of the wideband differential transistor pair, and a first drain that comprises the second differential output of the wideband differential transistor pair;

    a second differential transistor comprising a second source, a second gate that comprises the second differential input of the wideband differential transistor pair, and a second drain that comprises the first differential output of the wideband differential transistor pair; and

    a first current source that is coupled to the first source of the first differential transistor and to the second source of the second differential transistor;

    the cross-coupled differential transistor pair comprises:

    a third differential transistor comprising a third source, a third gate, and a third drain;

    a fourth differential transistor comprising a fourth source, a fourth gate, and a fourth drain;

    a second current source that is coupled to the third source of the third differential transistor and to the fourth source of the fourth differential transistor;

    the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are communicatively coupled; and

    the second drain of the second differential transistor, the fourth drain of the third differential transistor, and the third gate of the fourth differential transistor are communicatively coupled.



    [0022] Advantageously:

    a first capacitor that is coupled between the first differential input of the wideband differential transistor pair and the first differential output of the wideband differential transistor pair; and

    a second capacitor that is coupled between the second differential input of the wideband differential transistor pair and the second differential output of the wideband differential transistor pair.



    [0023] Advantageously:

    the first input impedance comprises a first series inductor; and

    the second input impedance comprises a second series inductor.



    [0024] Advantageously:

    the first output impedance comprises a first output resistor and a first shunt peaking inductor connected in series; and

    the second output impedance comprises a second output resistor and a second shunt peaking inductor connected in series.



    [0025] According to an example, a current-controlled CMOS (C3MOS) wideband variable delay cell circuit is provided, the circuit comprising:

    a first differential transistor comprising a first source, a first gate, and a first drain;

    a second differential transistor comprising a second source, a second gate, and a second drain;

    a first current source that is coupled to the first source of the first differential transistor and to the second source of the second differential transistor;

    a first series inductor that is coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor;

    a second series inductor that is coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor;

    a first output impedance, comprising a first output resistor and a first shunt peaking inductor connected in series, such that the first output resistor is coupled between the drain of the first differential transistor and the first shunt peaking inductor, and the first shunt peaking inductor is coupled between the first output resistor and a supply voltage;

    a second output impedance, comprising a second output resistor and a second shunt peaking inductor connected in series, such that the second output resistor is coupled between the drain of the second differential transistor and the second shunt peaking inductor, and the second shunt peaking inductor is coupled between the second output resistor and the supply voltage;

    a first capacitor that is coupled between the drain of the first differential transistor and the gate of the second differential transistor;

    a second capacitor that is coupled between the drain of the second differential transistor and the gate of the first differential transistor;

    a third differential transistor comprising a third source, a third gate, and a third drain;

    a fourth differential transistor comprising a fourth source, a fourth gate, and a fourth drain;

    a second current source that is coupled to the third source of the third differential transistor and to the fourth source of the fourth differential transistor;

    wherein the first drain of the first differential transistor, the third drain of the third differential transistor, and the fourth gate of the fourth differential transistor are communicatively coupled; and

    wherein the second drain of the second differential transistor, the fourth drain of the third differential transistor, and the third gate of the fourth differential transistor are communicatively coupled.



    [0026] Advantageously:

    the first current source is a first variable current source;

    the second current source is a second variable current source; and

    a variable delay of the C3MOS wideband variable delay cell circuit is controlled by adjusting at least one of a first current in the first variable current source and a second current in the second variable current source.



    [0027] Advantageously:
    a delay of the C3MOS wideband variable delay cell circuit is a function of a ratio of a first current in the first current source divided by a sum comprising the first current in the first current source and the second current in the second current source.

    [0028] Advantageously:
    the C3MOS wideband variable delay cell circuit is one delay cell of a plurality of delay cells implemented within an n-tap finite impulse response (FIR) filter.

    [0029] Advantageously:

    the first current source is a first current source transistor;

    the second current source is a second current source transistor; and

    the first differential transistor, the second differential transistor, the third differential transistor, the fourth differential transistor, the first current source transistor, and the second current source transistor comprise NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors or PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors.



    [0030] Other features and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings.

    BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS



    [0031] 

    FIG. 1 illustrates an example of a current-controlled CMOS (C3MOS) wideband data amplifier circuit.

    FIG. 2 illustrates an embodiment of a variable delay cell.

    FIG. 3 illustrates another embodiment of a variable delay cell.

    FIG. 4 illustrates an embodiment of a two-path adjustable high bandwidth delay cell.

    FIG. 5 illustrates an embodiment of a wideband variable delay cell.

    FIG. 6 illustrates an embodiment of delay through a cross-coupled differential pair (normalized) in response to current in a buffer stage (normalized).


    DETAILED DESCRIPTION OF THE INVENTION



    [0032] Various embodiments of the invention provide for ultra high-speed logic circuitry implemented in silicon complementary metal-oxide-semiconductor (CMOS) process technology. A distinction is made herein between the terminology "CMOS process technology" and "CMOS logic." CMOS process technology as used herein refers generally to a variety of well established CMOS fabrication processes that form a field-effect transistor over a silicon substrate with a gate terminal typically made of polysilicon material disposed on top of an insulating material such as silicon dioxide. CMOS logic, on the other hand, refers to the use of complementary CMOS transistors (n-channel and p-channel, implemented using NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors or PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors) to form various logic gates and more complex logic circuitry, wherein zero static current is dissipated. Embodiments of the invention use current-controlled mechanisms to develop a family of very fast current-controlled CMOS (C3MOS or C3MOS™) logic that can be fabricated using a variety of conventional CMOS process technologies, but that unlike conventional CMOS logic does dissipate static current. C3MOS logic or current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) logic are used herein interchangeably.

    [0033] Various C3MOS circuit techniques are described in greater detail in commonly-assigned U.S. Patent Application Serial No. 09/484,856, now U.S. Patent 6,424,194 B1, entitled "Current Controlled CMOS Logic Family," by A. Hairapetian.

    [0034] Other techniques have been developed to increase the gain-bandwidth product of CMOS circuitry. For example, shunt peaking is one approach that has resulted in improved gain-bandwidth product. Shunt peaking involves putting an inductor in series with the output resistor to expand the bandwidth of the circuit. Such inductive broadbanding technique combined with C3MOS circuitry is described in greater detail in commonly-assigned U.S. Patent Application Serial No. 09/610,905, now U.S. Patent 6,340,899 B1, entitled "Current-Controlled CMOS Circuits with Inductive Broadbanding," by M. Green.

    [0035] In commonly-assigned U.S. Patent Application Serial No. 10/028,806, now U.S. Patent 6,624,699 B2, entitled "Current-controlled CMOS wideband data amplifier circuits," by Guangming Yin and Jun Cao, the current-controlled CMOS wideband data amplifier circuits disclosed therein having expanded bandwidth are designed to achieve such the goal of having a flat frequency response over a very wide frequency range, where maximum bandwidth expansion is achieved by using series inductor peaking with Miller capacitance cancellation technique and shunt inductor peaking in current controlled CMOS (C3MOS or Current-controlled CMOS wideband data amplifier circuits) circuits.

    [0036] FIG. 1 illustrates an example 100 of a current-controlled CMOS (C3MOS) wideband data amplifier circuit. A current source transistor can be biased by a bias voltage so that a constant current flows from drain to source in the current source transistor. Two separate differential transistors compose a wideband differential transistor pair. A first differential transistor has its gate tied to the negative end of a first series peaking inductor L1, while a positive differential input signal INP is coupled to the positive end of the first series peaking inductor L1. Similarly, a second differential transistor has its gate tied to the negative end of a second series peaking inductor L2, while a negative differential input signal INN is coupled to the positive end of the second series peaking inductor L2.

    [0037] Assuming that the first and second differential transistors are identical, then the first and second series peaking inductors L1 and L2 have the same inductance. A first output resistor R3 has its negative end tied to the drain of the first differential transistor, and has its positive end tied to the negative end of a first shunt peaking inductor L3. A second output resistor R4 has its negative end tied to the drain of the second differential transistor, and has its positive end tied to the negative end of a second shunt peaking inductor L4. The positive ends of the first and second shunt peaking inductors L3 and L4 are tied to the positive supply voltage (shown as VCC).

    [0038] Preferably, the first and second output resistors R3 and R4 have the same resistance value R, and the first and second shunt peaking inductors L3 and L4 have the same inductances. A first capacitor C1 (which may be referred to as a first Miller cancellation capacitor C1) has its positive end coupled to the drain of the second differential transistor, and has its negative end coupled to the gate of the first differential transistor. A second capacitor C2 (which may be referred to as a second Miller cancellation capacitor C2) has its positive end coupled to the drain of the first differential transistor, and has its negative end coupled to the gate of the second differential transistor. A first output signal OUTP is taken at the drain of the second differential transistor, and the second output signal OUTN is taken at the drain of the first differential transistor.

    [0039] Input series inductors (LI and L2) resonate with the capacitance at the input of the differential pair at high frequencies and thus extend the bandwidth of the amplifier. In addition, at high frequencies, the inductors (L1 and L2) act as high impedance chokes between the termination resistors (shown as two series connected 50 Ω resistors) and the capacitors and thus also improve the input reflection for the C3MOS wideband data amplifier circuit of this embodiment 100.

    [0040] FIG. 2 illustrates an embodiment 200 of a variable delay cell. As mentioned above, there is a need in the art for delay cells within many broadband data communication applications. Also, variable delay cells provide for even greater flexibility and applicability than fixed delay type delay cells. This embodiment 200 shows a basic building block of a data synchronization circuit. The input data (DIN) is retimed by a flip-flop (FF) driven by a clock signal (CLK). For the FF to operate correctly, the input data (DIN) and clock (CLK) must satisfy one or more certain timing requirements. A delay cell is often inserted between the input data (DIN) and the FF so that the timing relation between the clock (CLK) and data (DIN) at the input of the FF can be adjusted to compensate for any phase variations of the input signals or circuit delay variations due to changes in process, voltage supply or temperature (PVT). As the input data (DIN) runs at an ever increasing rate, the delay cell needs to have continuously higher and higher bandwidth in order to preserve the signal integrity of the input data.

    [0041] FIG. 3 illustrates another embodiment 300 of a variable delay cell. This embodiment 300 is another example by which a variable delay cell can be employed. The embodiment 300 is a 5-tap finite impulse response (FIR) filter that is constructed to process the input data (DIN). For the FIR filter to work as designed, each delay cell (i.e., delay cells 310, 320, 330, and 340) should have the same delay in time which is usually inversely proportional to the data rate. Similar to the embodiment 200 of the FIG. 2, variable delay cells are desirable to compensate the circuit delay variations due to changes in PVT conditions. Furthermore, if the input data rate may vary, the delay cell also needs to provide corresponding changes in delay. Since multiple delay cells (i.e., delay cells 310, 320, 330, and 340) are usually connected in tandem, it's very important for the delay cells to have relatively high bandwidth in regard to the data rate.

    [0042] In the embodiment 300 of a variable delay cell implemented using a 5-tap FIR filter, a goal is to have a data stream with an equal delay (e.g., Δtn) between each of the various components of the data stream. In the embodiment 300, there are 5 components of the data stream. Typically, this delay (e.g., Δtn) is the same, and the delays of each of these delay cells 310, 320, 330, and 340 may be adjusted together.

    [0043] Another possible embodiment by which a variable delay cell can be implemented is to add a variable capacitive load at the output of conventional data buffers (e.g., differential pairs). However, there is a fundamental limitation on such an approach. For those circuits whose small-signal transfer function can be approximated by a single-pole response, the bandwidth and delay are directly coupled together. For example, the 10% - 90% rise/fall time in response to an input step equals to 0.35/BW (where BW is the -3dB bandwidth of the small signal response of the circuit). The larger is the delay amount, then the smaller is the bandwidth. As a result, the minimum bandwidth requirement on the delay cell puts an upper limit of the delay amount if such a circuit is employed. On the other hand, the smaller is the delay amount, then the larger is the bandwidth the circuit needs to have, which usually means more power and larger area the delay cell needs to have if a simple single-pole buffer is employed.

    [0044] FIG. 4 illustrates an embodiment 400 of a two-path adjustable high bandwidth delay cell. This embodiment 400 employs two separate data paths for the input data. One of the data paths has a relatively smaller amount of propagation delay (shown as buffer(s) with small delay 410), and the other of the data paths has a relatively larger amount of propagation delay (shown as buffer(s) with large delay 420). The signal passes through the two different paths are then combined together at a summing stage. The relative strength of the two paths can be adjusted (using a control block 430) and thus enable the overall data path to have a variable delay. To implement the slow path, several fast buffers can be connected in series in order to have a large enough propagation delay while preserving signal integrity.

    [0045] For transmission rates of 10 Gbps (Giga-bits per second) or higher, CMOS data buffers generally consume a significant amount of power due to limitations of the technology. In the two-path embodiment 400 of the FIG. 4 for a variable delay cell, at least three high-speed blocks need to be powered up, including the summer. The summer is especially power consumptive because it has two pairs of full-rate data input which will add a significant amount lot of parasitic loading to the high speed data path. Furthermore, the input data are connected to both the quick path and the slow path. If this combined input is connected to the output of a front buffer, this configuration will significantly increase the loading to the previous stage and thus reduce the overall bandwidth of the data path. If the combined input is connected to the input pads of the chip directly, it will cause a severe degradation of the matching between the input of the receiver and the traces on the printed circuit board (PCB) due to the excessive capacitance loading. This results in large amount of reflections and will degrade the integrity of the input data significantly. Another potential issue of the two path implementation is when the signals that have been passed going through the two different paths are combined together at the summer, additional jitter may be generated if the delay between the two path differs significantly. It would be most desirable to have a high bandwidth variable delay cell that would not have increased power and loading requirements across a wide variety of applications.

    [0046] The embodiment 400 mixes two types of buffers together: a slow buffer and a fast buffer. The larger delay that is required or desired in a particular application inherently incurs a lower bandwidth in the embodiment 400. The lower bandwidth in such an instance acts as a low pass filter (LPF). This LPF filtering may corrupt the signal undesirably due to the low frequency cut-off. Undesirable inter-symbol Interference (ISI) may also be introduced because of this LPF filtering. In very high speed, broadband application, such effects can significantly reduce overall performance.

    [0047] FIG. 5 illustrates an embodiment 500 of a wideband variable delay cell. In this embodiment 500, the input of the signal is connected to a current-controlled CMOS (C3MOS) wideband data amplifier circuit having expanded bandwidth that is similar to the example 100 of the FIG. 1. The operation of such a wideband data amplifier circuit having expanded bandwidth is also described in commonly-assigned U.S. Patent Application Serial No. 10/028,806, now U.S. Patent 6,624,699 B2, entitled "Current-controlled CMOS wideband data amplifier circuits," by Guangming Yin and Jun Cao. In such a C3MOS wideband data amplifier circuit having expanded bandwidth, maximum bandwidth expansion is achieved by using series inductor peaking with miller capacitance cancellation technique and shunt inductor peaking in current controlled CMOS circuit (C3MOS or C3MOS).

    [0048] Connected to the output of the wideband data buffer having expanded bandwidth (that includes the differential transistor pair M1 and M2, i.e. a wideband differential transistor pair) is a cross-coupled differential pair (that includes the differential transistor pair M3 and M4, i.e. a cross-coupled differential transistor pair) as the regenerative stage for the data. In this embodiment 500, there are therefore two very fast operating blocks [(1) wideband data buffer and (2) cross-coupled differential pair] that operate cooperatively to perform the functionality of a wideband variable delay cell that is appropriate for broadband applications.

    [0049] To vary the delay, the currents of the buffer stage and the cross-coupled differential pair stage can be adjusted (e.g., using a control block 530). When all the current passes through the buffer stage and the cross-coupled differential pair stage current source is turned off, the circuit behaves just like a wideband data amplifier having expanded bandwidth as described and referenced above (i.e., the example 100 of the FIG. 1 and within U.S. Patent 6,624,699 B2). With the high bandwidth achieved by various design skills, the delay through the delay cell can be very small. To increase the delay, the current going through the buffer stage is reduced and the current going through the cross-coupled differential pair stage is increased by the same amount. For the output signal to reach full swing, it has to go through the regenerative process at the cross-coupled differential pair to be amplified, and thus the delay is increased. A first-order analysis of the embodiment 500 of such a variable delay cell can be done based on a two-step approximation, as shown below.

    [0050] Since the buffer stage of the variable delay cell has very high bandwidth, the delay from input to output at this stage is very small. It is reasonable to assume the delay through the buffer stage is a relatively constant value (denoted as Tb); the delay variation of the delay cell is mostly contributed by the regenerative process of the cross-coupled differential pair stage (denoted as Tr). In the two-step approximation, the signal through the delay cell is divided into two steps. In the first step, the signal Vin is buffered by the input stage and appear at the output after a delay of T0, taking a value of Vm. Vm is equal to the current passing through the buffer stage (Ib) times the load resistance (R). In the second step, the signal Vm at the input of the cross-coupled differential pair goes through the positive feedback of the cross-coupled differential pair and gets regenerated until reaching the value of V0, after a delay of Tr. The voltage, V0, is a fixed value, determined by the total current (I0 = Ib + Ir) and load resistance (V0 = R·I0).

    [0051] If it assumed that Ib = x·I0, then Ir = (1-xI0. The value of x can be changed between 1 and 0, where x = 1 means that all the current is going through the buffer stage. At the output, which is also the input of the cross-coupled differential pair (that includes the differential transistor pair M3 and M4), after T0 of delay vm = x·I0·R. It is noted that the output voltage of a regenerative cross-coupled differential pair increases exponentially with time and is proportional to the initial voltage as indicated below.

    where τ is the characteristic time constant of the cross-coupled differential pair, which is inversely proportional to the gain of the cross-coupled differential pair. For CMOS transistors, the gain is proportional to the square root of the biasing current in the first order as indicated below.







    [0052] FIG. 6 illustrates an embodiment 600 of delay through a cross-coupled differential pair (normalized) in response to current in a buffer stage (normalized). This embodiment 600 shows the normalized delay trough the cross-coupled differential pair stage,

    as a function of the normalized current in the buffer stage

    It is evident that as the current passing through the buffer stage becomes smaller, the delay through the cross-coupled differential pair stage becomes bigger. The total delay through the delay cell is T = Tb + Tr. Thus by changing the current distribution between the buffer stage (including the differential transistor pair M1 and M2) and cross-coupled differential pair stage (including the differential transistor pair M3 and M4) (i.e., which involves changing the value of x), the amount of the delay can be readily adjusted.

    [0053] This control of the two currents, Ib and Ir, and their relationship, may be performed using a control block (e.g., control block 530 in the embodiment 500 of the FIG. 5). It is noted that the total current (I0 = Ib+Ir) required in the embodiment 500 is kept constant, but merely the relationship (or relationship) between these 2 currents, Ib and Ir, is controlled thereby controlling the overall delay. For example, a variable delay of such a variable delay cell circuit can be controlled by adjusting at least one of a first current, Ib, in a first variable current source and a second current, Ir, in the second variable current source. A variable delay of such a variable delay cell circuit can be controlled can be viewed as being a function of a ratio of a first current, Ib, in the first current source divided by a sum that includes the first current in the first current source and the second current in the second current source (e.g., total current (I0 = Ib + Ir)). Also, because this total current (I0 = Ib + Ir) remains unchanged, then the DC level of the delay cell output incurred by the load resistance also remains unchanged.

    [0054] As the value of x approaches 1, then the total delay a variable delay cell (e.g., the embodiment 500 of the FIG. 5) approaches the delay of the wideband data buffer (that includes the differential transistor pair M1 and M2). As the value of x approaches 0 (zero), then the total delay a variable delay cell (e.g., the embodiment 500 of the FIG. 5) approaches the maximum possible delay of the device that includes the delay of both the wideband data buffer (that includes the differential transistor pair M1 and M2) and the cross-coupled differential pair (that includes the differential transistor pair M3 and M4).

    [0055] Various embodiments of the invention presented herein provide for a large amount of delay to be incurred (which is selectable and variable, as desired in any of a wide variety of applications) with a minimal amount of signal quality degradation (i.e., minimal or no ISI).

    [0056] One of many advantages of this novel design is that all the bandwidth extension techniques as referenced above with respect to a wideband data amplifier circuit having expanded bandwidth can be readily applied to the variable delay cell. In the embodiment 500 of FIG. 5, series input inductors L1 and L2, shunt peaking inductors L3 and L4, and negative miller capacitors C1 and C2 are all added so that the stage including differential transistor pair M1 and M2 can achieve high bandwidth with minimum increase of power. As the bandwidth of the buffer stage increases, a lower end of the delay value reduces and thus the variable delay range is increased without compromising the signal integrity. In addition, as the buffer stage becomes much faster than the cross-coupled differential pair stage, the predictions of the two-step approximation become more accurate.

    [0057] By eliminating the double path (as depicted in the embodiment 400 of the FIG. 4), the embodiment 500 of the FIG. 5 shows an integrated delay cell that does not require the summing stage and thus reduces the power significantly. There is no extra capacitive loading added to the high speed path at the input. The additional capacitance due to the drains of the cross-coupled differential pair transistors at the output can be easily compensated by the shunt inductor. As a result, it is much easier to incorporate the integrated stage into the data path without compromising the signal integrity or degrading the impedance matching.

    [0058] From the embodiment 500 of the FIG. 5, it is clear that the amount of delay can be changed continuously by implementing continuous control signals for the two current sources (i.e., using control block 530). A programmable delay cell can also be readily implemented by replacing the two current sources (and) with a series of smaller current source, each can be turn on or off using digital control signals.

    [0059] In summary, a fully differential current-controlled CMOS (C3MOS) integrated wideband delay cell is presented herein. At the buffer stage, bandwidth extension techniques such as shunt peaking, series inductive peaking can be readily applied to increase the range of the flat frequency response. A cross-coupled differential pair stage is added to the output of the buffer to add delay from input to output through the regenerative process of the cross-coupled differential transistor pair connected in a positive feedback configuration. The delay can be adjusted by varying the current distribution between the buffer stage and the cross-coupled differential pair stage. The integrated delay cell can then accommodate a large amount of delay while at the same time maintain a high bandwidth for the data path, without adding load to the input and without adding power consumption.

    [0060] It is also noted that the methods described within the preceding figures can also be performed within any appropriate system and/or apparatus design (communication systems, communication transmitters, communication receivers, communication transceivers, and/or functionality described therein) without departing from the scope of the invention.

    [0061] In view of the above detailed description of the invention and associated drawings, other modifications and variations will now become apparent. It should also be apparent that such other modifications and variations can be effected without departing from the scope of the invention.


    Claims

    1. A current-controlled CMOS, C3MOS, wideband variable delay cell circuit, the circuit comprising:

    a first differential transistor (M1) comprising a first source, a first gate, and a first drain;

    a second differential transistor (M2) comprising a second source, a second gate, and a second drain;

    a first current source (Ib) that is coupled to the first source of the first differential transistor (M1) and to the second source of the second differential transistor (M2);

    a first input impedance that is coupled between a first differential input of the C3MOS wideband variable delay cell circuit and the first gate of the first differential transistor (M1);

    a second input impedance that is coupled between a second differential input of the C3MOS wideband variable delay cell circuit and the second gate of the second differential transistor (M2);

    a first output impedance, comprising a first output resistor (R3) and a first shunt peaking inductor (L3) connected in series, that is coupled between the first drain of the first differential transistor (M1) and a supply voltage (Vcc);

    a second output impedance, comprising a second output resistor (R4) and a second shunt peaking inductor (L4) connected in series, that is coupled between the second drain of the second differential transistor (M2) and the supply voltage (Vcc);

    a third differential transistor (M3) comprising a third source, a third gate, and a third drain;

    a fourth differential transistor (M4) comprising a fourth source, a fourth gate, and a fourth drain;

    a second current source (Ir) that is coupled to the third source of the third differential transistor (M3) and to the fourth source of the fourth differential transistor (M4);

    wherein the second drain of the second differential transistor (M2), the fourth drain of the fourth differential transistor (M4), and the third gate of the third differential transistor (M3) are directly coupled to form a first differential output node OUTP of the C3MOS wideband variable delay cell circuit,

    wherein the first drain of the first differential transistor (M1), the third drain of the third differential transistor (M3), and the fourth gate of the fourth differential transistor (M4) are directly coupled to form a second differential output node OUTN of the C3MOS wideband variable delay cell circuit,

    wherein the C3MOS wideband variable delay cell circuit is configured to reduce the current of the first current source while the current of the second current source is increased by the same amount to increase a variable delay of the C3MOS wideband variable delay cell circuit, wherein:

    the first input impedance comprises a first series inductor (L1); and

    the second input impedance comprises a second series inductor (L2).


     
    2. The circuit of claim 1, further comprising:

    a first capacitor (C2) that is coupled between the first drain of the first differential transistor (M1) and the second gate of the second differential transistor (M2); and

    a second capacitor (C1) that is coupled between the second drain of the second differential transistor (M2) and the first gate of the first differential transistor (M1).


     
    3. The circuit of claim 1, wherein:

    the first output resistor (R3) of the first output impedance is coupled between the first drain of the first differential transistor (M1) and the first shunt peaking inductor (L3) of the first output impedance; and

    the first shunt peaking inductor (L3) of the first output impedance is coupled between the first output resistor (R3) of the first output impedance and the supply voltage (Vcc).


     
    4. The circuit of claim 1, wherein:

    the first current source (Ib) is a first current source transistor;

    the second current source (Ir) is a second current source transistor; and

    the first differential transistor (M1), the second differential transistor (M2), the third differential transistor (M3), the fourth differential transistor (M4), the first current source transistor, and the second current source transistor comprise NMOS (Negative-Channel Metal-Oxide Semiconductor) transistors.


     
    5. The circuit of claim 1, wherein:

    the first current source (Ib) is a first current source transistor;

    the second current source (Ir) is a second current source transistor; and

    the first differential transistor (M1), the second differential transistor (M2), the third differential transistor (M3), the fourth differential transistor (M4), the first current source transistor, and the second current source transistor comprise PMOS (Positive-Channel Metal-Oxide Semiconductor) transistors.


     
    6. The circuit of claim 1, wherein:
    the variable delay of the C3MOS wideband variable delay cell circuit is a function of a ratio of a first current in the first current source (Ib) divided by a sum comprising the first current in the first current source (Ib) and the second current in the second current source (Ir).
     
    7. The circuit of claim 1, wherein:

    the first current source (Ib) is a first variable current source;

    the second current source (Ir) is a second variable current source; and

    the variable delay of the C3MOS wideband variable delay cell circuit is controlled by adjusting at least one of a first current in the first variable current source and a second current in the second variable current source.


     
    8. An n-tap finite impulse response (FIR) filter comprising plurality of delay cells, wherein the circuit of claim 1 is one delay cell of the plurality of delay cells.
     


    Ansprüche

    1. Stromgesteuerte CMOS, C3MOS, breitbandvariable Verzögerungszellenschaltung, wobei die Schaltung aufweist:

    einen ersten differentiellen Transistor (M1), der eine erste Source, ein erstes Gate und ein erstes Drain aufweist;

    einen zweiten differentiellen Transistor (M2), der eine zweite Source,

    ein zweites Gate und ein zweites Drain aufweist;

    eine erste Stromquelle (Ib), die an die erste Source des ersten differentiellen Transistors (M1) und an die zweite Source des zweiten differentiellen Transistors (M2) gekoppelt ist;

    eine erste Eingangsimpedanz, die zwischen einen ersten differentiellen Eingang der C3MOS breitbandväriablen Verzögerungszellenschaltung und das erste Gate des ersten differentiellen Transistors (M1) geschaltet ist;

    eine zweite Eingangsimpedanz, die zwischen einen zweiten differentiellen Eingang der C3MOS breitbandvariablen Verzögerungszellenschaltung und das zweite Gate des zweiten differentiellen Transistors (M2) geschaltet ist;

    eine erste Ausgangsimpedanz, die einen ersten Ausgangswiderstand (R3) und eine erste Nebenschluss-Versteilerungsspule bzw. Shunt Peaking Inductor (L3) aufweist, die in Reihe geschaltet sind, und die zwischen das erste Drain des ersten differentiellen Transistors (M1) und eine Versorgungsspannung (Vcc) geschaltet ist;

    eine zweite Ausgangsimpedanz, die einen zweiten Ausgangswiderstand (R4) und eine zweite Nebenschluss-Versteilerungsspule bzw. Shunt Peaking Inductor (L4) aufweist, die in Reihe geschaltet sind, und die zwischen das zweite Drain des zweiten differentiellen Transistors (M2) und die Versorgungsspannung (Vcc) geschaltet ist;

    einen dritten differentiellen Transistor (M3), der eine dritte Source, ein drittes Gate und ein drittes Drain aufweist;

    einen vierten differentiellen Transistor (M4), der eine vierte Source, ein viertes Gate und ein viertes Drain aufweist;

    eine zweite Stromquelle (Ir), die an die dritte Source des dritten differentiellen Transistors (M3) und an die vierte Source des vierten differentiellen Transistors (M4) gekoppelt ist;

    wobei das zweite Drain des zweiten differentiellen Transistors (M2), das vierte Drain des vierten differentiellen Transistors (M4) und das dritte Gate des dritten differentiellen Transistors (M3) direkt gekoppelt sind, um einen ersten differentiellen Ausgangsknoten OUTP der C3MOS breitbandvariablen Verzögerungszellenschaltung zu bilden,

    wobei das erste Drain des ersten differentiellen Transistors (M1), das dritte Drain des dritten differentiellen Transistors (M3) und das vierte Gate des vierten differentiellen Transistors (M4) direkt gekoppelt sind, um einen zweiten differentiellen Ausgangsknoten OUTN der C3MOS breitbandvariablen Verzögerungszellerischaltung zu bilden,

    wobei die C3MOS breitbandvariable Verzögerungszellenschaltung dazu konfiguriert ist, den Strom der ersten Stromquelle zu reduzieren, während der Strom der zweiten Stromquelle um denselben Betrag erhöht wird, um eine variable Verzögerung der C3MOS breitbandvariablen Verzögerungszellenschaltung zu vergrößern, wobei:

    die erste Eingangsimpedanz eine erste Reihenspule (L1) aufweist; und

    die zweite Eingangsimpedanz eine zweite Reihenspule (L2) aufweist.


     
    2. Schaltung nach Anspruch 1, die des Weiteren aufweist:

    einen ersten Kondensator (C2), der zwischen das erste Drain des ersten differentiellen Transistors (M1) und das zweite Gate des zweiten differentiellen Transistors (M2) geschaltet ist; und

    einen zweiten Kondensator (C1), der zwischen das zweite Drain des zweiten differentiellen Transistors (M2) und das erste Gate des ersten differentiellen Transistors (M1) geschaltet ist.


     
    3. Schaltung nach Anspruch 1, wobei:

    der erste Ausgangswiderstand (R3) der ersten Ausgangsimpedanz zwischen das erste Drain des ersten differentiellen Transistors (M1) und die erste Nebenschluss-Versteilerungsspule (L3) der ersten Ausgangsimpedanz geschaltet ist; und

    die erste Nebenschluss-Versteilerungsspule (L3) der ersten Ausgangsimpedanz zwischen den ersten Ausgangswiderstand (R3) der ersten Ausgangsimpedanz und die Versorgungsspannung (Vcc) geschaltet ist.


     
    4. Schaltung nach Anspruch 1, wobei:

    die erste Stromquelle (Ib) ein erster Stromquellentransistor ist;

    die zweite Stromquelle (Ir) ein zweiter Stromquellentransistor ist; und

    der erste differentielle Transistor (M1), der zweite differentielle Transistor (M2), der dritte differentielle Transistor (M3), der vierte differentielle Transistor (M4), der erste Stromquellentransistor und der zweite Stromquellentransistor NMOS (Negative Channel Metal-Oxide Semiconductor)-Transistoren aufweisen.


     
    5. Schaltung nach Anspruch 1, wobei:

    die erste Stromquelle (Ib) ein erster Stromquellentransistor ist;

    die zweite Stromquelle (Ir) ein zweiter Stromquellentransistor ist; und

    der erste differentielle Transistor (M1), der zweite differentielle Transistor (M2), der dritte differentielle Transistor (M3), der vierte differentielle Transistor (M4), der erste Stromquellentransistor und der zweite Stromquellentransistor PMOS (Positive Channel Metal-Oxide Semiconductor) -Transistoren aufweisen.


     
    6. Schaltung nach Anspruch 1, wobei:
    die variable Verzögerung der C3MOS breitbandvariablen Verzögerungszellenschaltung eine Funktion eines Verhältnisses eines ersten Stroms in der ersten Stromquelle (Ib) dividiert durch eine Summe ist, die den ersten Strom in der ersten Stromquelle (Ib) und den zweiten Strom in der zweiten Stromquelle (Ir) aufweist.
     
    7. Schaltung nach Anspruch 1, wobei:

    die erste Stromquelle (Ib) eine erste variable Stromquelle ist;

    die zweite Stromquelle (Ir) eine zweite variable Stromquelle ist; und

    die variable Verzögerung der C3MOS breitbandvariablen Verzögerungszellenschaltung gesteuert wird durch Einstellen von wenigstens einem von einem ersten Strom in der ersten variablen Stromquelle und einem zweiten Strom in der zweiten variablen Stromquelle.


     
    8. Filter mit begrenztem Impulsansprechen bzw. Finite Impulse Response (FIR) -Filter mit n Abgriffen, das eine Vielzahl von Verzögerungszellen aufweist, wobei die Schaltung nach Anspruch 1 eine Verzögerungszelle der Vielzahl von Verzögerungszellen ist.
     


    Revendications

    1. Circuit cellulaire à retard variable à large bande, C3MOS, commandé par courant, CMOS, le circuit comprenant:

    un premier transistor différentiel (M1) comprenant une première source, une première grille et un premier drain ;

    un deuxième transistor différentiel (M2) comprenant une deuxième source, une deuxième grille et un deuxième drain ;

    une première source de courant (Ib) qui est couplée à la première source du premier transistor différentiel (M1) et à la deuxième source du deuxième transistor différentiel (M2) ;

    une première impédance d'entrée qui est couplée entre une première entrée différentielle du circuit cellulaire à retard variable à large bande C3MOS et la première grille du premier transistor différentiel (M1) ;

    une seconde impédance d'entrée qui est couplée entre une deuxième entrée différentielle du circuit cellulaire à retard variable à large bande C3MOS et la deuxième grille du deuxième transistor différentiel (M2) ;

    une première impédance de sortie, comprenant une première résistance de sortie (R3) et un premier inducteur de crête de dérivation (L3) connectés en série, qui est couplée entre le premier drain du premier transistor différentiel (M1) et une tension d'alimentation (Vcc) ;

    une seconde impédance de sortie, comprenant une seconde résistance de sortie (R4) et un second inducteur de crête de dérivation (L4) connectés en série, qui est couplée entre le deuxième drain du deuxième transistor différentiel (M2) et la tension d'alimentation (Vcc) ;

    un troisième transistor différentiel (M3) comprenant une troisième source, une troisième grille et un troisième drain ;

    un quatrième transistor différentiel (M4) comprenant une quatrième source, une quatrième grille et un quatrième drain ;

    une deuxième source de courant (Ir) qui est couplée à la troisième source du troisième transistor différentiel (M3) et à la quatrième source du quatrième transistor différentiel (M4) ;

    dans lequel le deuxième drain du deuxième transistor différentiel (M2), le quatrième drain du quatrième transistor différentiel (M4) et la troisième grille du troisième transistor différentiel (M3) sont couplés directement pour former un premier nœud de sortie différentiel OUTP du circuit cellulaire à retard variable à large bande C3MOS,

    dans lequel le premier drain du premier transistor différentiel (M1), le troisième drain du troisième transistor différentiel (M3) et la quatrième grille du quatrième transistor différentiel (M4) sont couplés directement pour former un second nœud de sortie différentiel OUTN du circuit cellulaire à retard variable à large bande C3MOS,

    dans lequel le circuit cellulaire à retard variable à large bande C3MOS est conçu pour réduire le courant de la première source de courant pendant que le courant de la deuxième source de courant augmente de la même quantité pour augmenter un retard variable du circuit cellulaire à retard variable à large bande C3MOS, dans lequel :

    la première impédance d'entrée comprend un premier inducteur en série (L1) ; et

    la seconde impédance d'entrée comprend un second inducteur en série (L2).


     
    2. Circuit selon la revendication 1, comprenant en outre :

    un premier condensateur (C2) qui est couplé entre le premier drain du premier transistor différentiel (M1) et la deuxième grille du deuxième transistor différentiel (M2) ; et

    un second condensateur (C1) qui est couplé entre le deuxième drain du deuxième transistor différentiel (M2) et la première grille du premier transistor différentiel (M1).


     
    3. Circuit selon la revendication 1, dans lequel :

    la première résistance de sortie (R3) de la première impédance de sortie est couplée entre le premier drain du premier transistor différentiel (M1) et le premier inducteur de crête de dérivation (L3) de la première impédance de sortie ; et

    le premier inducteur de crête de dérivation (L3) de la première impédance de sortie est couplé entre la première résistance de sortie (R3) de la première impédance de sortie et la tension d'alimentation (Vcc).


     
    4. Circuit selon la revendication 1, dans lequel :

    la première source de courant (Ib) est un premier transistor de source de courant ;

    la deuxième source de courant (Ir) est un deuxième transistor de source de courant ; et

    le premier transistor différentiel (M1), le deuxième transistor différentiel (M2), le troisième transistor différentiel (M3), le quatrième transistor différentiel (M4), le premier transistor de source de courant et le deuxième transistor de source de courant comprennent des transistors NMOS (semi-conducteur à oxyde métallique à canal négatif).


     
    5. Circuit selon la revendication 1, dans lequel :

    la première source de courant (Ib) est un premier transistor de source de courant ;

    la deuxième source de courant (Ir) est un deuxième transistor de source de courant ; et

    le premier transistor différentiel (M1), le deuxième transistor différentiel (M2), le troisième transistor différentiel (M3), le quatrième transistor différentiel (M4), le premier transistor de source de courant et le deuxième transistor de source de courant comprennent des transistors PMOS (semi-conducteur à oxyde métallique à canal positif).


     
    6. Circuit selon la revendication 1, dans lequel :
    le retard variable du circuit cellulaire à retard variable à large bande C3MOS est une fonction d'un rapport d'un premier courant dans la première source de courant (Ib) divisée par une somme comprenant le premier courant dans la première ressource de courant (Ib) et le second courant dans la deuxième source de courant (Ir).
     
    7. Circuit selon la revendication 1, dans lequel :

    la première source de courant (Ib) est une première source de courant variable ;

    la deuxième source de courant (Ir) est une deuxième source de courant variable ; et

    le retard variable du circuit cellulaire à retard variable à large bande C3MOS est contrôlé en réglant au moins un d'un premier courant dans la première source de courant variable et d'un second courant dans la deuxième source de courant variable.


     
    8. Filtre de réponse impulsionnelle finie à n prises (FIR) comprenant une pluralité de cellules de retard, dans lequel le circuit selon la revendication 1 est une cellule de retard parmi la pluralité de cellules de retard.
     




    Drawing























    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description