(19)
(11)EP 1 782 464 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
11.04.2012 Bulletin 2012/15

(21)Application number: 05768741.0

(22)Date of filing:  28.07.2005
(51)International Patent Classification (IPC): 
H01L 21/78(2006.01)
H01L 23/544(2006.01)
H01L 21/683(2006.01)
(86)International application number:
PCT/JP2005/014261
(87)International publication number:
WO 2006/013910 (09.02.2006 Gazette  2006/06)

(54)

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICES

HERSTELUNGSVERFAHREN FÜR HALBLEITERBAUELEMENTE

MÉTHODE DE FABRICATION DE DISPOSITIFS SEMI-CONDUCTEURS


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

(30)Priority: 02.08.2004 JP 2004225104

(43)Date of publication of application:
09.05.2007 Bulletin 2007/19

(73)Proprietor: Panasonic Corporation
Kadoma-shi Osaka 571-8501 (JP)

(72)Inventors:
  • HAJI, Hiroshi c/o Matsushita Elec. Industrial Co., Ltd.
    Chuo-ku, Osaka-shi, Osaka 540-6319 (JP)
  • ARITA, Kiyoshi c/o Matsushita Elec. Industrial Co., Ltd.
    Chuo-ku, Osaka-shi, Osaka 540-6319 (JP)
  • NISHINAKA, Teruaki c/o Matsushita Elec. Industrial Co., Ltd.
    Chuo-ku, Osaka-shi, Osaka 540-6319 (JP)

(74)Representative: Eisenführ, Speiser & Partner 
Postfach 10 60 78
28060 Bremen
28060 Bremen (DE)


(56)References cited: : 
JP-A- 63 261 843
US-A- 5 633 173
US-B1- 6 605 479
JP-A- 2002 273 884
US-A1- 2004 137 700
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Technical Field



    [0001] The present invention relates to a dicing method for a (semiconductor wafer in which a semiconductor wafer with a plurality semiconductor devices formed thereon is diced into the respective separate semiconductor devices by application of plasma etching, and a manufacturing method for semiconductor devices including such a dicing method involving the plasma etching as a part of its process.

    Background Art



    [0002] In order to mark defective elements on a semiconductor wafer without introducing foreign matters to be generated thereby and to make it possible to provide marks having a uniform size and easy to recognize, by checking characteristics of a multiplicity of elements as formed on a semiconductor wafer, before etching the surface of any defective element for marking the same, it is proposed in JP 63261843; A multiplicity of elements are formed on a semiconductor wafer, and a first positive-type photoresist is applied on the surface of the wafer except a region where a measuring electrode is provided. After checking characteristics of the elements, parts of the first photoresist located on the surface of defective elements are exposed so that windows are opened in those parts. Second photoresist is applied on the windows of the first photoresist located on the measuring electrode. Then, the surface of each defective element not covered with the first or second photoresist is etched so that such element is broken. When the first and second photoresists are removed, the surface of the defective element is marked by a window opened in an insulation film on the defective element. In this manner, any defective element can be marked and discriminated reliably, not dependent on its dimensional difference.

    [0003] In order to produce a high-quality, good-yield and superior-thermal stability head chip with a small number of defects whose cutting resistance can be reduced by dicing along scribe lines whereat liquid supply holes are etched simultaneously when formed at a dicing time after joining a heater board wafer and a top plate wafer, it is proposed in JP 2002273884: A silicon wafer having a front face of a <110> face is used as a material for forming a top plate. Simultaneously with forming liquid supply holes to the silicon wafer by anisotropic etching, alignment marks and scribe lines are etched to the same plane as a plane of supply ports of the liquid supply holes, whereby the top plate wafer is formed. The top plate wafer is joined to the heater board wafer where a plurality of heaters are formed. The joined two wafers are diced at the same time by dicing blades along the scribe lines, cut and separated to individual head chips.

    [0004] Conventionally, in manufacturing of such semiconductor devices, after a plurality of semiconductor devices are formed on a circuit formation face of a semiconductor wafer, the formed semiconductor devices undergo an inspection, (mainly an inspection of electric characteristic), and based on the result of quality check, flawed (bad) semiconductor devices are marked, for example, on their surfaces, so as to be visibly distinguishable from other semiconductor devices for management of the flawed semiconductor devices.

    [0005] As such conventional marking methods, a method for forming bad marks on the surface of the flawed semiconductor devices with inks and a method for forming bad marks through formation of resist films are known (see, e.g., Japanese unexamined patent publication No. 2000-124270 A).

    Disclosure of Invention



    [0006] After the inspection of the semiconductor devices, and formation of bad marks on the flawed semiconductor devices reflecting the result of the inspection, polishing process is performed on the face of the opposite side for the circuit formation face of the semiconductor wafer as a thinning processing of the semiconductor wafer to the level of, for example, a thickness of 100 µm or smaller.

    [0007] However, by forming such bad marks (formed on the circuit formation face), smooth protuberant portions (protuberance layer) are formed only on portions of the circuit formation face of the semiconductor wafer where the bad marks are formed. Thus, with the protuberant portions partially formed on the circuit formation face, as a result of polishing process performed on the opposite face, smooth recess portions are formed in turn on portions corresponding to the places where the protuberant portions are formed on the pertinent face. This causes such problem as degraded quality of semiconductor devices as the formation of the bad marks aiming at quality management of the semiconductor devices contrarily hinders the uniformity of the thickness of manufactured semiconductor devices. Particularly, the thinned semiconductor wafer is often required a higher-level uniformity of the thickness, making occurrence of such a problem more prominent.

    [0008] An object of the present invention is to provide, for solving the problem, a dicing method for semiconductor wafer capable of distinguishing flawed semiconductor devices from other semiconductor devices while preventing degradation of the quality of the respective semiconductor devices in a semiconductor wafer, a manufacturing method for semiconductor devices, and a formation apparatus for semiconductor wafer dicing masks for use during dicing of the semiconductor devices.

    [0009] In order to accomplish the object, the present invention is defined by the terms of the claims, and exemplified as shown below.

    [0010] According to a first aspect of the present invention, there is provided a manufacturing method for semiconductor devices comprising:

    placing a mask on a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, while defining dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices and partially exposing the mask placement-side surface on a flawed semiconductor device among the respective semiconductor devices; and

    dicing (separating or dividing) the semiconductor wafer into the respective semiconductor devices along the defined dicing lines and removing an exposed portion of the flawed semiconductor device so as to form a removed portion as a distinguishing mark for the flawed semiconductor device, by applying plasma etching to the mask placement-side surface of the semiconductor wafer, thereby the separated respective semiconductor devices distinguishably from the flawed semiconductor devices are manufactured, under the additional conditions of claim 1.

    According to a second aspect of the present invention, now integrated into claim 1, there is provided the manufacturing method for semiconductor devices as defined in the first aspect, wherein the mask is placed so as to partially expose the surface of the flawed semiconductor device on basis of position information for the flawed semiconductor device in the semiconductor wafer.



    [0011] According to a third aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the first aspect, further comprising:

    obtaining position information for the flawed semiconductor device in the semiconductor wafer before placing the mask, wherein

    the mask is placed on basis of the obtained position information for the flawed semiconductor device.



    [0012] According to a fourth aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in second aspect, wherein the position information for the flawed semiconductor device is formed by using a result of an inspection performed on the respective semiconductor devices in the semiconductor wafer.

    [0013] According to a fifth aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the first aspect, wherein in placing of the mask,

    the mask is placed so as to cover the entire mask placement-side surface of the semiconductor wafer, and then

    parts of the mask are removed in conformity with the respective positions of the dicing lines on the semiconductor wafer so as to partially expose the surface of the semiconductor wafer to define the dicing lines, and a part of the mask on the flawed semiconductor device is removed so as to partially expose the surface of the flawed semiconductor device.



    [0014] According to a sixth aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the fifth aspect, wherein the mask is removed by irradiating a laser beam to the mask of the semiconductor wafer while moving the laser beam relatively along to the surface of the semiconductor wafer.

    [0015] According to a seventh aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the sixth aspect, wherein the laser beam is relatively moved on basis of preset mask data.

    [0016] According to an eighth aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the sixth aspect, wherein the laser beam is relatively moved, on basis of position information for the dicing lines and position information for the flawed semiconductor device in the semiconductor wafer.

    [0017] According to a ninth aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the first aspect, wherein the mask is placed so as to expose an almost central area of the surface of the flawed semiconductor device in an almost circular shape.

    [0018] According to a tenth aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the first aspect, further comprising:

    removing the respective masks from the mask placement-side surface of the semiconductor wafer, after dicing the semiconductor and removing the exposed portion.



    [0019] According to an eleventh aspect of the present invention, there is provided the manufacturing method for semiconductor devices as defined in the fourth aspect, wherein
    after the inspection of the respective semiconductor devices, thinning of the semiconductor wafer is performed, and then
    the mask is placed on the thinned semiconductor wafer.

    [0020] According to a twelfth aspect of the present invention, now integrated in claim 1, there is provided a manufacturing method for semiconductor devices comprising:

    placing a mask on a mask placement-side surface of a semiconductor wafer in which a plurality of semiconductor devices are formed, while defining dicing lines for dicing the semiconductor wafer into the respective separate semiconductor devices and entirely exposing the mask placement-side surface on a flawed semiconductor device among the respective semiconductor devices; and

    dicing the semiconductor wafer into the respective semiconductor devices along the defined dicing lines and removing the flawed semiconductor device entirely, by applying plasma etching to the mask placement-side surface of the semiconductor wafer, thereby the separated respective semiconductor devices are manufactured.



    [0021] According to a thirteenth aspect of the present invention, now integrated in claim 2, there is provided the manufacturing method for semiconductor devices as defined in the twelfth aspect, wherein the mask is placed so as to entirely expose the surface of the flawed semiconductor device on basis of position information for the flawed semiconductor device in the semiconductor wafer.

    [0022] According to the first aspect of the present invention, when a mask for defining dicing lines of the respective semiconductor devices is placed on the mask placement-side surface of the semiconductor wafer, the placement is performed so as to partially expose the surface of a flawed semiconductor device, and then plasma etching is applied, so that the semiconductor wafer is diced into the respective separate semiconductor devices along the dicing lines and at the same time (simultaneously) an exposed portion of the flawed semiconductor device is removed so as to form the removed portion into a flawed semiconductor device distinguishing mark (bad mark). Thus, by forming the flawed semiconductor device distinguishing mark through plasma etching in the final stage of the manufacturing process of the semiconductor devices, it becomes possible to prevent occurrence of such conventional problem that bad marks with use of inks and resist films which are formed as prominent portions cause dispersion of the thickness of the semiconductor wafer through the thinning processing.

    [0023] Moreover, the plasma etching for dicing the semiconductor device into the respective separate semiconductor devices allows the dicing together with the formation of the bad marks, which makes it possible to provide a dicing method for semiconductor wafers capable of realizing efficient formation of the bad marks, i.e., a manufacturing method for semiconductor devices.

    [0024] Therefore, it becomes possible to efficiently form the distinguishing marks allowing clear distinction of the flawed semiconductor device from other semiconductor devices without degrading the quality of the semiconductor devices, and to stabilize the quality of the diced semiconductor devices.

    [0025] According to the second aspect or the third aspect of the present invention, by conducting such placement of the mask based on the position information for the flawed semiconductor device, it becomes possible to specifically realize the formation of the bad marks and the dicing with use of, for example, automated apparatuses and the like.

    [0026] According to the fourth aspect of the present invention, since the position information for such a flawed semiconductor device is position information formed based on the result of the inspection performed on the respective semiconductor devices, the information obtained from the inspection process can be directly linked to the formation of the bad marks on the flawed semiconductor devices, thereby allowing reliable formation of the bad marks.

    [0027] According to the fifth aspect of the present invention, the formation of the mask is achieved by placing the mask in such a way as to cover the entire mask placement-side surface of the semiconductor wafer and by applying processing to partially remove the placed mask.

    [0028] According to the sixth aspect, the seventh aspect or the eighth aspect of the present invention, the processing of the mask can be specifically realized with use of laser beams. Moreover, by relatively moving the laser beam and the semiconductor wafer during such processing based on mask data and position information for the flawed semiconductor device, the mask at a desired position will be credibly removed

    [0029] According to the ninth aspect of the present invention, by placing the mask so as to expose an almost central area of the surface of the flawed semiconductor device in an almost circular shape, the dicing lines defined by the mask are definitely positioned between the flawed semiconductor devices and the adjacent semiconductor devices, which makes it possible to maintain the uniformity of etching of dicing position portions in the plasma etching operation and to provide high-quality semiconductor devices.

    [0030] According to another aspect of the present invention, during the placement of the mask, instead of being partially exposed, the surface of the flawed semiconductor device is totally exposed, so that the flawed semiconductor device itself is removed by the plasma etching. Thus, removing the flawed semiconductor device itself makes it possible to credibly prevent the flawed semiconductor device from being confused with other semiconductor devices.

    [0031] Moreover, by incorporating such semiconductor wafer dicing methods of the respective aspects in the manufacturing process of semiconductor devices, it becomes possible to provide a manufacturing method for semiconductor devices capable of covering acquisition of the position information for flawed semiconductor devices from the inspection process to dicing of the semiconductor wafer into the respective separate semiconductor devices performed together with formation of the bad marks.

    Brief Description of Drawings



    [0032] These and other aspects and features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings, in which:

    Fig. 1 is a schematic diagram for showing a plasma processing apparatus for use in the manufacturing process of semiconductor devices according to a first embodiment of the present invention;

    Fig. 2 is a schematic diagram for showing a laser processing apparatus for use in the manufacturing process of the semiconductor devices in the first embodiment of the present invention;

    Fig. 3 is a flowchart showing the procedures of the semiconductor device manufacturing process in the first embodiment;

    Fig. 4A is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which a semiconductor wafer has semiconductor devices formed thereon;

    Fig. 4B is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer has a protective sheet being applied in a protective sheet application process;

    Fig. 4C is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer is subjected to a polishing process;

    Fig. 4D is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer is subjected to a damaged layer removal process;

    Fig. 5A is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer has a mask layer formed in a mask layer formation process;

    Fig. 5B is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer has a dicing line mask removal portion and a bad mark mask removal portion formed in a mask layer partial removal process;

    Fig. 5C is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer is subjected to etching in a plasma dicing process;

    Fig. 5D is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer is diced into respective separate semiconductor devices;

    Fig. 5E is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer has the mask removed in a mask layer removal process;

    Fig. 5F is a schematic explanatory view for explaining each process in the flowchart in Fig. 3, in which the semiconductor wafer has a die bonding sheet applied thereto;

    Fig. 6 is a schematic perspective view showing the semiconductor wafer having a mask pattern formed thereon;

    Fig. 7 is a schematic perspective view showing the semiconductor wafer having the mask removed after the plasma dicing;

    Fig. 8A is a schematic explanatory view for explaining part of the manufacturing process of semiconductor devices according to a second embodiment of the present invention, in which the semiconductor wafer has a mask layer formed in the mask layer formation process;

    Fig. 8B is a schematic explanatory view for explaining part of the manufacturing process of semiconductor devices according to the second embodiment of the present invention, in which the semiconductor wafer has the mask layer partially removed in the mask layer partial removal process;

    Fig. 8C is a schematic explanatory view for explaining part of the manufacturing process of semiconductor devices according to the second embodiment of the present invention, in which the semiconductor wafer is subjected to etching in the plasma dicing process;

    Fig. 8D is a schematic explanatory view for explaining part of the manufacturing process of semiconductor devices according to the second embodiment of the present invention, in which the semiconductor wafer is diced into respective separate semiconductor devices;

    Fig. 8E is a schematic explanatory view for explaining part of the manufacturing process of semiconductor devices according to the second embodiment of the present invention, in which a semiconductor wafer has the mask removed in the mask layer removal process;

    Fig. 8F is a schematic explanatory view for explaining part of the manufacturing process of semiconductor devices according to the second embodiment of the present invention, in which the semiconductor wafer has a die bonding sheet applied thereto;

    Fig. 9 is a schematic perspective view for showing the semiconductor wafer having mask patterns formed thereon in the second embodiment; and

    Fig. 10 is a schematic perspective view for showing the semiconductor wafer having the mask removed after the plasma dicing in the second embodiment.


    Best Mode for Carrying Out the Invention



    [0033] Before the description of the present invention proceeds, it is to be noted that like parts are designated by like reference numerals throughout the accompanying drawings.

    [0034] Hereinbelow, the embodiment of the present invention will be described in detail with reference to the drawings.

    [0035] For describing a semiconductor wafer dicing method and a semiconductor device manufacturing method according to a first embodiment of the present invention, first, the structure of the apparatuses for use in the dicing method and the manufacturing method will be described.

    [0036] Fig. 1 shows a schematic diagram schematically showing the structure of a plasma processing apparatus 101 exemplifying the semiconductor wafer dicing apparatus for implementing the semiconductor wafer dicing method in the first embodiment. The plasma processing apparatus 101 applies plasma etching to a semiconductor wafer having a plurality of semiconductor devices formed thereon to conduct dicing (plasma dicing) of the semiconductor wafer into respective separate semiconductor devices. First, the outlined structure of the plasma processing apparatus 101 will be described hereinbelow with reference to Fig. 1.

    [0037] As shown in Fig. 1, the plasma processing apparatus 101 has a vacuum chamber 11 that includes a processing chamber 12 of an enclosed space for applying plasma processing to a semiconductor wafer 1. Inside the vacuum chamber 11, a lower electrode 13 and an upper electrode 14 are parallely disposed facing each other. Moreover, on the upper face of the lower electrode 13 as viewed in the drawing, a mounting face 13a on which an almost disc-shaped semiconductor wafer 1 can be mounted is formed, and the semiconductor wafer 1 is mounted on the mounting face 13a in the state that the entire periphery thereof is surrounded by an insulating ring 18. Moreover, the mounting face 13a has a function to suck and hold the mounted semiconductor wafer 1 in a releasably way through vacuum suction or electrostatic suction. The lower electrode 13 is disposed inside the processing chamber 12 through an insulator 12a, with the lower electrode 13 and the processing chamber 12 being electrically insulated through the insulator 12a.

    [0038] Moreover, in the upper electrode 14, a gas supply hole 14a, which is a passage to supply plasma generation gas to the inside of a space (electric discharge space) formed between the upper electrode 14 and the lower electrode 13, is formed in such a way as to go through the inside of the upper electrode 14. Moreover, one end of the gas supply hole 14a in the upper electrode 14 formed to be linked to the outside of the vacuum chamber 11 is connected to a plasma generation gas supply unit 17 provided outside of the vacuum chamber 11, which makes it possible to supply, for example, a fluorinated plasma generation gas from the plasma generation gas supply unit 17 to the processing chamber 12 through the gas supply hole 14a. It is to be noted that at some midpoint of the gas supply passage extending between the plasma generation gas supply unit 17 and the one end of the gas supply hole 14a, a flow regulating valve 16 exemplifying a gas flow rate regulating portion for regulating a supply gas flow rate to a desired flow rate is provided. Further, a porous plate 15 is seated on the lower surface of the upper electrode 14 as viewed in the drawing, which makes it possible to supply the plasma generation gas supplied through the gas supply hole 14a to the inside of the processing chamber 12 in such a way as to be evenly sprayed to the semiconductor wafer 1 mounted on the mounting face 13a of the lower electrode 13 through the porous plate 15.

    [0039] Moreover, the plasma processing apparatus 101 has an air discharging pump 19 exemplifying an evacuation apparatus for reducing the pressure in the processing chamber 12 to a desired pressure (i.e., vacuumizing the processing chamber 12) by evacuating the processing chamber 12. Moreover, an RF power supply unit 20 is electrically connected to the lower electrode 13, which makes it possible to apply high-frequency voltage to the lower electrode 13 from the RF power supply unit 20.

    [0040] In the thus-structured plasma processing apparatus 101, after the semiconductor wafer 1 is mounted on the mounting face 13a of the lower electrode 13 and the vacuum chamber 11 is enclosed, the processing chamber 12 is evacuated and vacuumized by the air discharging pump 19 and a high-frequency voltage is applied to the lower electrode 13 by driving the RF power supply unit 20 while a specified amount of the plasma generation gas is supplied to the processing chamber 12 from the plasma generation gas supply unit 17, by which fluorinated plasma is generated between the electric discharge space between the upper electrode 14 and the lower electrode 13. By irradiating thus-generated plasma to the surface of the semiconductor wafer 1, etching (i.e., plasma etching) of the irradiated surface can be implemented. It is to be noted that the plasma processing apparatus 101 has a cooling unit 21 for cooling the semiconductor wafer 1 mounted on the mounting face 13a of the lower electrode 13 through the mounting face 13a by circulating a coolant inside the lower electrode 13 Thus, the presence of the cooling unit 21 makes it possible to prevent the temperature of the semiconductor wafer 1 from increasing beyond a specified temperature from the heat generated during plasma processing.

    [0041] Description is now given of the structure of a laser processing apparatus 102 exemplifying the formation apparatus for semiconductor wafer dicing masks, in which during plasma dicing by such a plasma processing apparatus 101, a mask layer placed on the surface of a semiconductor wafer 1 is processed with a laser beam along the dicing positions of respective semiconductor devices to form dicing lines, with reference to the schematic block diagram in Fig. 2.

    [0042] As shown in Fig. 2, the laser processing apparatus 102 has a wafer holding unit 40 (wafer holding device) for holding the semiconductor wafer 1 having a mask layer 5 formed thereon in the state of being exposed in a releasably way. A moving plate moving head 37 equipped with a laser irradiation unit 39 and a camera 38 is provided on the wafer holding unit 40 is, and further a moving apparatus (device) 35 for moving the moving plate moving head 37 relatively to the wafer holding unit 40 is provided along the surface of the semiconductor wafer 1 in the state of being held by the wafer holding unit 40. Thus, the moving apparatus 35 moving the moving plate moving head 37 allows the laser irradiation unit 39 and the camera 38 attached to the moving plate moving head 37 to be moved relatively to the wafer holding unit 40. Moreover, the laser irradiation unit 39 is capable of irradiating the laser beam generated by a laser generation unit 36 to the semiconductor wafer 1 disposed below. It is to be noted that in the first embodiment, the laser irradiation apparatus (device) comprises the laser irradiation unit 39 and the laser generation unit 36.

    [0043] The camera 38 is an infrared camera for picking images of the semiconductor wafer 1 disposed below by infrared light. In this case, images of a circuit pattern or distinguishing marks on the circuit formation face of the semiconductor wafer 1 may be picked up through the mask layer 5. Then, the image pick-up result is inputted into a recognition section 34 included in a laser processing control unit 30 exemplifying a control device, where recognition processing is performed to detect the position and the circuit pattern arrangement of the semiconductor wafer 1.

    [0044] Moreover, the laser processing control unit 30 comprises a control section 33 for controlling laser generation operation by the laser generation unit 36, moving operation by the moving apparatus 35 and recognition processing by the recognition section 34, an operation/input section 31 for operating and commanding the control by the control section 33, and a work data storage section 32 for storing data which is referred during control operation by the control section 33. The work data storage section 32 stores data on dicing positions (dicing lines or parting lines) of respective semiconductor devices on the semiconductor wafer 1 and data on the width of the dicing lines formed at the dicing positions (dicing width), i.e., the removal width of the mask layer removed along the dicing positions. Data write onto the work data storage section 32 is executable by the operation/input section 31.

    [0045] When laser processing of the semiconductor wafer 1 is executed in the laser processing apparatus 102 having such structure, the control section 33 controls the moving apparatus 35 based on an actual position data of the semiconductor wafer 1 detected by the recognition section 34 and the data on the dicing positions stored in the work data storage section 32. With this, the moving apparatus 35 makes it possible to move the laser irradiation unit 39 along the dicing positions on the upper face of the semiconductor wafer 1. Further, by the control section 33 controlling the laser generation unit 36 based on the data on the width of the dicing lines, it becomes possible to irradiate a laser beam with an output appropriate for removing the mask layer 5 with a removal width corresponding to the width of the dicing lines from the laser irradiation unit 39. By executing such laser processing, it becomes possible to form a mask pattern with only a portion corresponding to the dicing lines for separating the semiconductor devices from each other being removed in the mask layer 5 on the surface of the semiconductor wafer 1.

    [0046] Description is now given of a series of the manufacturing processes of respective semiconductor devices including the dicing of the semiconductor wafer 1 performed with use of the thus-structured laser processing apparatus 102 and the plasma processing apparatus 101. For the description, Fig. 3 shows a flowchart showing the procedures in the manufacturing process of the semiconductor devices, and further Figs. 4A, 4B, 4C, 4D, 5A, 5B, 5C, 5D, 5E and 5F show schematic explanatory views for explaining the procedures of the manufacturing process.

    [0047] First, in step S1 in the flowchart of Fig. 3, the processing such as film formation, exposure and etching is applied to a circuit-formation-face 1a that is a first surface of the semiconductor wafer 1 to form a plurality of circuit formation portions 2 which become semiconductor devices as shown in Fig. 4A (semiconductor device formation process). Further, in each of the circuit formation portions 2, a plurality of external connection electrodes 3 are formed from conductive materials in the state of being exposed from the circuit-formation-face 1a.

    [0048] Next, in order to determine whether or not the semiconductor wafer 1 having respective circuit formation portions 2 and the external connection electrodes 3 formed thereon has any defect portions in its formation state, the formation states of the respective circuit formation portions 2 and the external connection electrodes 3 are inspected (semiconductor device inspection process, step S2). In this inspection, it is mainly inspected whether or not the circuit formation portions 2 and the external connection electrodes 3 have any defects in their electric characteristics. Based on the result of the inspection, the quality check is performed by every circuit formation portion 2, and with respect to those circuit formation portions 2 determined to be flawed, their position information for the semiconductor wafer 1 is formed and stored. Such position information may be stored in a storage device included in the inspection apparatus for performing the inspection or may be stored in a storage device included in a management system for managing the entire manufacturing process of semiconductor devices and the like. The type of the storage configuration may take various forms as long as the position information is stored in the state accessible in the following processes. Further, the position information is created and maintained not only in the case of the position information for those circuit formation portions 2 determined to be flawed, but in the case of the position information for the circuit formation portions 2 determined, on the contrary, to be acceptable, so that the acceptable circuit formation portions 2 may be distinguished from the flawed circuit formation portions 2.

    [0049] Next, as shown in Fig. 4B, a protective sheet 4 is applied to the circuit-formation-face 1a through an adhesive agent so as to prevent the circuit-formation-face 1a of the semiconductor wafer 1 after completion of the inspection process from being damaged during each processing thereafter (protective sheet application process, step S3). It is to be noted that the protective sheet 4 for use is formed into almost the same shape as the external shape of the semiconductor wafer 1 so as to cover the entire circuit-formation-face 1a and not to protrude outward from the end portion of the semiconductor wafer 1. By using the protective sheet 4 in such a shape, it becomes possible to prevent such damage that during the following processes such as plasma processing, the protective sheet 14 protruding from the semiconductor wafer 1 is burnt by plasma from occurring.

    [0050] Next, in step S41 in Fig. 3, a polishing process for thinning the thickness of the semiconductor wafer 1 is performed. More specifically, as shown in Fig. 4C, with the circuit-formation-face 1a of the semiconductor wafer 1 being on the lower side as viewed in the drawing, the semiconductor wafer 1 is placed on a holding table 42 through the protective sheet 4 and the placing position is held. In this state, a processing-target-face 1b (second surface or mask placement-side surface on which a mask is placed in the following processes) that is a surface on the opposite side of the circuit-formation-face 1a of the semiconductor wafer 1 is polished by using a grinding wheel 41. On the lower face of the grinding wheel 41 as viewed in the drawing, a grinding stone is fixed, and the grinding stone is rotated along the processing-target-face 1b of the semiconductor wafer 1 in the state of being in contact with the surface to perform polishing of the processing-target-face 1b. By such polishing treatment, the semiconductor wafer 1 is thinned to have a thickness of about 100 µm or smaller, e.g., 50 µm in the first embodiment.

    [0051] In the vicinity of the surface of the processing-target-face 1b of the semiconductor wafer 1 subjected to the polishing process, a damaged layer retaining stress imparted by polishing with the grinding wheel 41 is formed. Such a damaged layer being left on the formed semiconductor devices degrades the resistance of the semiconductor devices, and causes deterioration of their quality. In order to prevent such deterioration of the quality, the damaged layer formed on the processing-target-face 1b of the semiconductor wafer 1 is removed as shown in Fig. 4D (damaged layer removal process, step S42). For example, as shown in Fig. 4D, an etching solution (sulfuric acid, nitric acid, phosphoric acid, fluorinated acid, etc.) 51 is brought into contact with the damaged layer formed on the processing-target-face 1b of the semiconductor wafer 1 so as to remove the damaged layer by corroding the damaged layer by the chemical reaction (wet etching treatment). It is to be noted that instead of by using the wet etching treatment as the removal processing of the damaged layer, the damaged layer may be removed by applying plasma etching to the processing-target-face 1b (plasma etching process), or the damaged layer may be removed by performing polishing on the processing-target-face 1b. Moreover, the process combining the polishing process in step S41 and the damaged layer removal process in step S42 constitutes the thinning process in step S4.

    [0052] After such a thinning process is applied, as shown in Fig. 5, a mask layer 5 is formed on the processing-target-face 1b of the semiconductor wafer 1 (mask layer formation process, step S51). The mask layer 5 is for forming mask patterns for use in the later-described plasma dicing process, the mask pattern being formed from a material, such as aluminum and resin, having tolerance against plasma produced with use of fluorinated gasses.

    [0053] In the case of using aluminum, a method for forming an aluminum thin film on the processing-target-face 1b by deposition and a method for applying a foil-like aluminum thin film are used. In the case of using resin, a method for applying a resin formed in a film shape and a method for coating the processing-target-face 1b with a liquid resin by spin coat method and the like may be used.

    [0054] Next, as shown in Fig. 5B, partial removal of the mask layer 5 by laser processing is performed (mask layer partial removal process, step S52). More specifically, in the laser processing apparatus 102 shown in Fig. 2, the semiconductor wafer 1 having the mask layer 5 formed on the processing-target-face 1b is placed on the wafer holding unit 40 through the protective sheet 4 which is applied to the circuit-formation-face 1a, and the placing position is held. After that, while the camera 38 is moved by the moving apparatus 35 along the surface of the semiconductor wafer 1, an image of the circuit patterns of the semiconductor wafer 1 is obtained. By performing recognition processing of the obtained image in the recognition section 34, the actual position of the semiconductor wafer 1 is recognized. The control section 33 controls the moving apparatus 35 based on the result of the recognition processing and the position data on the dicing positions (positions of the dicing lines) stored in the work data storage section 32, and moves the laser irradiation unit 39 along the dicing positions of the semiconductor wafer 1. While moving the laser irradiation unit 39, the control section 33 controls the laser generation unit 36 based on the data on the width of the dicing lines, and irradiates a laser beam with an output appropriate for removing the mask layer 5 with a removal width corresponding to the width. With such irradiation of the laser beam 39a, a dicing mask removal portion 5a where the mask layer 5 is partially removed is formed at the dicing positions of the respective semiconductor devices as shown in Fig. 5B.

    [0055] In the work data storage section 32 of the laser processing apparatus 102, the position information of the flawed circuit formation portions 2 created based on the inspection result of the previously performed semiconductor device inspection process (step S2), i.e., the position information for the flawed semiconductor devices, are inputted through the operation/input section 31. Such input of the position information may be conducted through wireless communication means, wire communication means or storage media. During removal processing of the mask layer 5 along the dicing positions, the control section 33 controls the moving apparatus 35, the laser generation unit 36 and the laser irradiation unit 39 based on the position information for the flawed semiconductor devices held in the work data storage section 32 so as to irradiate the laser beam 39a to the mask layer 5 placed on the processing-target-face 1b of the flawed semiconductor devices, by which the mask layer 5 is partially removed so as to expose a part of the processing-target-face 1b of the flawed semiconductor devices.

    [0056] More specifically, in the semiconductor wafer 1 shown in Fig. 5B, if a semiconductor device positioned on the left end as viewed in the drawing is a flawed semiconductor device, and then the mask layer 5 is partially removed so as to expose an almost central area of the processing-target-face 1b of the flawed semiconductor device in an almost circular shape. A portion of the mask layer 5 partially removed by such way is a bad mark mask removal portion 5b on which a bad mark (flawed semiconductor device distinguishing mark) is formed in the following plasma dicing process. In the case where a plurality of flawed semiconductor devices is present on the semiconductor wafer 1, the partial removal of the mask layer 5 is executed so as to partially expose the surfaces of all the flawed semiconductor devices.

    [0057] As for the semiconductor devices determined not to be flawed but to be acceptable, the partial removal of the mask layer 5 is not executed. Portions of the mask layer 5 remaining after portions corresponding to the dicing mask removal portion 5a and the bad mark mask removal portion 5b are removed make masks 5C, and portions (surfaces) of the masks 5C are portions to which etching is not applied during the later-executed plasma dicing.

    [0058] Moreover, in the semiconductor device inspection process, the inspection of the semiconductor devices (circuit formation portions 2) is performed from the side of the circuit-formation-face 1a, whereas in the laser processing apparatus 102, the mask layer 5 disposed on the side of the processing-target-face 1b of the semiconductor wafer 1 is processed. Therefore, the position information for the flawed semiconductor devices created and obtained during the inspection process is handled as information in which the upper and lower faces of the semiconductor wafer 1 being inverted in the laser processing. Moreover, the position information of such flawed semiconductor devices and dicing line data may be combined to constitute mask data for formation of mask patterns.

    [0059] Thus, by executing a mask pattern formation process (S5) composed of the combination of the mask layer formation process in step S51 and the mask layer partial removal process in step S52, for example, mask patterns 5b as shown in the schematic perspective view of the semiconductor wafer 1 in Fig. 6 are formed. Such mask patterns 5b comprises the dicing line mask removal portions 5a, the bad mark mask removal portions 5b and the masks 5c, and in the case of the semiconductor wafer 1 shown in Fig. 6, three flawed semiconductor devices are present. Although description is given of the case where in the outer peripheral portion of the semiconductor wafer 1, the mask layer 5 on a portion without the semiconductor devices is also removed in Fig. 6, the present embodiment is not limited to this case and therefore is applicable to the case where, for example, the mask layer 5 on this portion is not removed.

    [0060] Next, by performing plasma etching on the semiconductor wafer 1 with the mask patterns 5d being formed thereon, dicing of the semiconductor wafer 1 into respective separate semiconductor devices (plasma dicing process, step S6) is performed.

    [0061] More specifically, in the plasma processing apparatus 101 shown in Fig. 1, the semiconductor wafer 1 is placed on the placing face 13a of the lower electrode 13 through the protective sheet 4 with the processing-target-face 1b having the mask patterns 5d formed thereon being the upper face. Then, the vacuum chamber 11 is enclosed and the air discharging pump 19 is driven to vacuumize the processing chamber 12 (e.g., to approx 100 Pa), while a gas is supplied at a flow rate regulated by the flow regulating valve 16 from the plasma generation gas supply unit 17 to the inside of the processing chamber 12 through the gas supply hole 14a and the porous plate 15. In such a state, a high-frequency voltage is applied to the lower electrode 13 from the RF power supply unit 20 so that plasma is generated in the electric discharge space between the upper electrode 14 and the lower electrode 13.

    [0062] As shown in Fig. 5C, a plasma 61 generated in the electric discharge space is irradiated to the mask patterns 5d formed on the processing-target-face 1b of the semiconductor wafer 1 in the state of being placed on the placing face 13a of the lower electrode 13. With such irradiation of the plasma 61, the surfaces of the processing-target-face 1b corresponding to the dicing mask removal portions 5a and the bad mark mask removal portions 5b, which are the exposed surfaces without the mask 5C formed thereon, are irradiated with the plasma 61. By such irradiation of the plasma, the exposed surfaces of the processing-target-face 1b are subjected to etching.

    [0063] By application of plasma etching to the exposed surfaces of the processing-target-face 1b of the semiconductor wafer 1, the thickness of portions of the semiconductor wafer 1 corresponding to the exposed surfaces are thinned, and the portions are removed at the end. With this, as shown in Fig. 5D, the semiconductor wafer 1 is diced into respective separate semiconductor devices 1d along dicing lines 1c, and almost circular-shaped through hole are formed as bad marks 1e in a central area of flawed semiconductor devices 1f along the bad mark mask removal portions 5b.

    [0064] After that, as shown in Fig. 5E, the masks 5c remaining on the processing-target-faces 1b of the diced semiconductor devices 1d and the flawed semiconductor devices 1f are removed by applying, for example, ashing (mask layer removal process, step S7). Fig. 7 shows a schematic perspective view of the semiconductor wafer 1 subjected to the mask layer removal process. As shown in Fig. 7, the respective semiconductor devices 1d and the flawed semiconductor devices 1f are separated into respective pieces, and in the central area of the each of the flawed semiconductor devices 1f, the bad mark 1e is formed as an almost circular-shaped through hole.

    [0065] After that, as shown in Fig. 5F, an adhesive sheet (die bonding sheet) 6 is applied to the processing-target-face 1b of the semiconductor wafer 1 (die bonding sheet application process, step S8), and the protective sheet 4 protecting the circuit-formation-face 1a of the semiconductor wafer 1 is removed. The adhesive sheet 6 herein has a size larger than the semiconductor wafer 1 and is fixed to its surrounding by an unshown wafer-ring (jig). Holding the wafer-ring allows handling of the semiconductor wafer 1. With this, the manufacturing process of semiconductor devices is completed.

    [0066] Thus, each circuit-formation-face 1a of the semiconductor devices 1d in the state of adhering to the adhesive sheet 6 is sucked and held by, for example, a suction nozzle, and in this state, the suction nozzle is raised so that the sucked and held semiconductor devices 1d can be removed from the adhesive sheet 6 and be picked up. During such suction and picking-up by the suction nozzle, an image of the circuit-formation-face 1a of the semiconductor devices 1d is obtained by an image pickup apparatus and the image is subjected to recognition processing, by which those semiconductor devices 1d to be picked up are identified. As shown in Fig. 5F, since the flawed semiconductor device 1f has the circular-shaped through hole formed as the bad mark 1e, light reflectance on its circuit-formation-face 1a is largely difference from the circuit-formation-face 1a of the other semiconductor devices 1d, which makes it possible to clearly distinguish the flawed semiconductor device 1f from the other semiconductor devices 1d during the above-stated recognition processing. Therefore, it becomes possible to securely prevent the flawed semiconductor device 1f from being picked up by mistake during picking-up of the semiconductor devices 1d.

    [0067] Moreover, suction and holding of the semiconductor devices 1d by the suction nozzle is implemented by sucking and holding the almost central area of the circuit-formation-face 1a, and since the flawed semiconductor device 1f has the almost circular-shaped through hole formed as the bad mark 1e, suction and holding of the circuit-formation-face 1a of the flawed semiconductor device can also be structurally prevented.

    [0068] Moreover, the bad mark 1e formed on such flawed semiconductor devices 1f allows an operator to clearly recognize by sight, thereby making it possible to clearly distinguish the flawed semiconductor device 1f from the other semiconductor devices 1d.

    [0069] The size of the bad mark 1e formed on such flawed semiconductor devices 1f (i.e., the size of the bad mark mask removal portion 5b) is determined by depending on the size (planar size) of semiconductor devices (or flawed semiconductor devices), and is preferably determined, for example, in the size range of about 10% to 40% of the size of the semiconductor device. Particularly, the size of the bad mark 1e is preferably not less than the size which enables the visible recognition apparatus to surely recognize whether or not the bad mark 1e is formed on a certain semiconductor device 1d, when the semiconductor device 1d is sucked and held from the semiconductor wafer 1 which was diced and is covered with the adhesive sheet 6 in a die bonding apparatus or the like.

    [0070] It is to be understood the bad mark 1e is not limited to those formed as the through holes as describe above. For example, instead of the case where a portion of the semiconductor wafer 1 corresponding to the exposed surface in the bad mark mask removal portion 5b is completely removed, the bad mark may be formed by removing a part thereof, e.g., about a half depth thereof. However, in the case where "partial removal" is conducted, the formed bad mark needs to have a recognizable size. Therefore, in the present specification, "removal" of the exposed portion in the bad mark mask removal portion herein signifies not only the case of "complete" removal but also the case of "partial" removal.

    [0071] Moreover, the formation of the bad marks 1e for clearly distinguishing such flawed semiconductor devices 1f from the other semiconductor devices 1d is achieved by performing plasma dicing with use of the bad mark mask removal portions 5b formed together with the dicing mask removal portions 5a which defines the dicing lined in the mask pattern formation process. Therefore, an additional new process for formation of such bad marks 1e is not necessary, and therefore forming of the bad marks 1e make efficient.

    [0072] Moreover, the bad mark 1e is not formed as the prominent portion with use of inks and resist layers like conventional bad marks but formed as the almost-circular-shaped through hole, and further, since the formation of the bad mark 1e is performed after the thinning processing of the semiconductor wafer 1 is executed, recess portions and the like formed on the surface of the semiconductor wafer 1 due to the thinning processing can be surely prevented, thereby allowing manufacturing of high-quality semiconductor devices. It is to be noted that since the size and the prominence height of the respective external connection electrodes 3 formed on the circuit-formation-face 1a of the respective semiconductor devices are sufficiently smaller (e.g., about 1/5 to 1/10 times) than the size and the prominence height of the prominent portion of the conventional bad mark formed with use of inks and the resist layers, the extrusions or indentions of the circuit-formation-face 1a caused by formation of these external connection electrodes 3 can be sufficiently absorbed by the protective sheet 4 applied to the circuit-formation-face 1a, and will not exert an influence during the thinning processing.

    [0073] Moreover, by forming the bad mark mask removal portion 5b as the almost circular-shaped through hole in the center area of the processing-target-face 1b of the flawed semiconductor device 1f, the dicing mask removal portions 5a can be formed between the flawed semiconductor device 1f and the adjacent semiconductor devices 1d. Thus, by applying plasma etching in the state that the dicing mask removal portion 5a is formed in between all the adjacent semiconductor devices on the semiconductor wafer 1 regardless of the shape of the dicing mask removal portion 5a, the etching state can be maintained almost uniform. Therefore, plasma dicing can be conducted under the uniform conditions despite whether adjacent semiconductor devices are the flawed semiconductor devices or not, which makes it possible to manufacture high-quality semiconductor devices.

    [0074] It is to be noted that the present invention is not limited to this embodiment and is applicable to other various aspects. For example, Figs. 8A, 8B, 8C, 8D, 8E, and 8F show the schematic explanatory views for showing part of the procedures in the manufacturing method for semiconductor devices according to a second embodiment of the present invention. The manufacturing method for semiconductor devices in the second embodiment, which is performed in the procedures similar to those in the flowchart in Fig. 3 showing the procedures in the manufacturing method in the first embodiment, is different from the first embodiment in the point that the formation of the bad mark is not involved and the flawed semiconductor device itself is removed by etching during plasma etching. Hereinbelow, description is given on the different point.

    [0075] First, as shown in Fig. 8A, a mask layer 5 is formed on a processing-target-face 1b of the semiconductor wafer 1 after thinning processing is applied and removal the damaged layer is performed. After that, in the laser processing apparatus 102, the formed mask layer 5 is processed with the laser beam 39a to form the dicing mask removal portion 5a along dicing positions (positions of the dicing lines). In this case, based on position information of the flawed semiconductor devices, processing with the laser beam 39a is performed so as to totally remove the mask layer 5 placed on the processing-target-face 1b of the flawed semiconductor devices. More specifically, as shown in Fig. 8B, if it is determined that a circuit formation portion 2 disposed on the left end as viewed in the drawing is flawed based on the position information of the flawed semiconductor devices, the mask layer 5 disposed on the entire processing-target-face 1b of the flawed semiconductor device is removed by irradiation of the laser beam 39a, and the entire surface thereof is put in the state of being exposed. Herein, Fig. 9 shows a schematic perspective view of the semiconductor wafer 1 with the mask patterns 5d formed thereon by such partial removal of the mask layer 5. In Fig. 9, portions denoted by reference numeral P1 correspond to the flawed semiconductor devices with the mask layer 5 removed, and on this semiconductor wafer 1, three flawed semiconductor devices are present.

    [0076] Then, as shown in Fig. 8C, plasma etching is applied to the semiconductor wafer 1 having the mask pattern 5d formed thereon in the plasma processing apparatus 101. With this, the processing-target-face 1b with the dicing mask removal portion 5a formed thereon and the processing-target-face 1b of the flawed semiconductor devices are irradiated with the plasma 61 and are subjected to etching. As a result, as shown in Fig. 8D, the semiconductor wafer 1 is diced into respective separate semiconductor devices 1d and the flawed semiconductor devices themselves are removed and eliminated.

    [0077] After that, the mask removal process is performed as shown in Fig. 8F, and further, the die bonding sheet application process is performed as shown in Fig. 8, by which the manufacturing process of semiconductor devices is completed.

    [0078] Fig. 10 shows a schematic perspective view of the semiconductor wafer 1 on which the flawed semiconductor devices are removed and which is diced into respective separate semiconductor devices 1d as viewed from the side of the processing-target-face 1b. Fig. 10 indicates that semiconductor devices 1d are removed (eliminated) at three locations as denoted by reference numeral P2 on the semiconductor wafer 1.

    [0079] On such a semiconductor wafer 1, the flawed semiconductor devices are completely removed and eliminated, and therefore as shown in Fig. 8F, the respective semiconductor devices 1d in the final manufacturing stage do not include the flawed semiconductor devices themselves. Therefore, during picking-up of the semiconductor devices 1d performed thereafter, picking-up of the flawed semiconductor devices by mistake can be prevented completely.

    [0080] Although in each of the embodiments, description has been made of the case where the mask layer 5 formed on the semiconductor wafer 1 is processed with a laser beam based on the position information of the flawed semiconductor devices created and obtained in the semiconductor device inspection process, the present invention is not limited to this case.

    [0081] Instead of this case, the mask constituting the mask patterns created in advance based on the position information of the flawed semiconductor devices may be placed on the processing-target-face 1b of the semiconductor wafer 1 so as to partially or completely expose the surface of the flawed semiconductor devices.

    [0082] Moreover, in the case where the inspection process in the manufacturing process of semiconductor devices is performed separately from the processes following the mask formation process, the mask data created in combination of the position information of the flawed semiconductor devices and dicing line information may be inputted into the laser processing apparatus 102 for processing the mask layer 5 based on the mask data.

    [0083] More particularly, when the mask patterns, which are for use in plasma dicing, are placed so as to (partially or completely) expose the surface of the flawed semiconductor devices, the bad marks may be formed on the flawed semiconductor devices, or the flawed semiconductor devices themselves may be eliminated, and the method therefore may take various forms.

    [0084] Moreover, the bad mark mask removal portion 5b is not limited to those formed as almost circular-shaped through holes as shown in the first embodiment, but may include those formed as, for example, polygon-shaped or oval-shaped through holes. Further, a plurality of the bad mark mask removal portions 5b may be formed for one flawed semiconductor device 1f. Further, in the case where a flawed semiconductor device 1f is disposed on the outermost portion of the semiconductor wafer 1 in Fig. 6, instead of forming the bad mark mask removal portion in an almost central area of the flawed semiconductor device 1f, the bad mark mask removal portion may be formed so as to exclude the peripheral end side where the semiconductor devices 1d are not disposed adjacently. In such a case, the bad mark mask removal portion 5b may still be formed between the adjacent semiconductor devices 1d to maintain the uniformity of etching.


    Claims

    1. A manufacturing method for semiconductor devices comprising:

    placing (551) a mask (5) on a mask placement-side surface (1b) that is a surface on an opposite side of a circuit-formation-surface (1a) of a semiconductor wafer (1) in which a plurality of semiconductor devices are formed;

    defining (552) dicing lines (1c) for dicing the semiconductor wafer into the respective separate semiconductor devices (1d) and partially or entirely exposing the mask placement-side surface on a flawed semiconductor device (1f) among the respective semiconductor devices; and

    dicing (36) the semiconductor wafer into the respective semiconductor devices along the defined dicing lines (1c), and at the same time, in case of a partial exposure of the mask placement-side surface, removing an exposed portion of the flawed semiconductor device (1f) so as to form a removed portion as a distinguishing mark for the flawed semiconductor device or, in case of an entire exposure of the mask placement-side surface, removing the flawed semiconductor device (1f) entirely, by applying plasma etching to the mask placement-side surface (1b) of the semiconductor wafer (1), thereby the separated respective semiconductor devices (1d) distinguishably from the flawed semiconductor devices (1f) are manufactured.


     
    2. The manufacturing method for semiconductor devices as defined in claim 1,
    wherein the mask (5) is placed so as to partially or entirely expose the surface of the flawed semiconductor device (1f) on basis of position information for the flawed semiconductor device in the semiconductor wafer (1).
     
    3. The manufacturing method for semiconductor devices as defined in claim 1, further comprising:

    obtaining position information for the flawed semiconductor device (1f) in the semiconductor wafer (1) before placing the mask (5), wherein

    the mask (5) is placed on basis of the obtained position information for the flawed semiconductor device (1f).


     
    4. The manufacturing method for semiconductor devices as defined in claim 2,
    wherein the position information for the flawed semiconductor device (1f) is formed by using a result of an inspection (S2) performed on the respective semiconductor devices in the semiconductor wafer (1).
     
    5. The manufacturing method for semiconductor devices as defined in claim 1, wherein in placing of the mask,
    the mask (5) is placed so as to cover the entire mask placement-side surface (1 b) of the semiconductor wafer, and then
    parts of the mask (5) are removed in conformity with the respective positions of the dicing lines (1c) on the semiconductor wafer (1) so as to partially expose the surface of the semiconductor wafer (1) to define the dicing lines (1 c), and a part of the mask (5) or the entire mask (5) on the flawed semiconductor device (1f) is removed so as to partially or entirely expose the surface of the flawed semiconductor device (1f).
     
    6. The manufacturing method for semiconductor devices as defined in claim 5,
    wherein the mask (5) is removed by irradiating (S52) a laser beam to the mask (5) of the semiconductor wafer (1) while moving the laser beam relatively along to the surface of the semiconductor wafer (1).
     
    7. The manufacturing method for semiconductor devices as defined in claim 6,
    wherein the laser beam is relatively moved on basis of preset mask data.
     
    8. The manufacturing method for semiconductor devices as defined in claim 6,
    wherein the laser beam is relatively moved, on basis of position information for the dicing lines (1c) and position information for the flawed semiconductor device (1f) in the semiconductor wafer (1).
     
    9. The manufacturing method for semiconductor devices as defined in claim 1,
    wherein the mask (5) is placed so as to expose an almost central area of the surface of the flawed semiconductor device (1f) in an almost circular shape.
     
    10. The manufacturing method for semiconductor devices as defined in claim 1, further comprising:

    removing (S7) the respective masks from the mask placement-side surface (1b) of the semiconductor wafer (1), after dicing the semiconductor and removing (S52) the exposed portion.


     
    11. The manufacturing method for semiconductor devices as defined in claim 4, wherein
    after the inspection (S2) of the respective semiconductor devices, thinning of the semiconductor wafer (1) is performed, and then
    the mask (5) is placed on the thinned semiconductor wafer (1).
     


    Ansprüche

    1. Herstellungsverfahren für Halbleitervorrichtungen, mit:

    Platzieren (551) einer Maske (5) auf einer Masken-Platzier-Seiten-Oberfläche (1b), die eine Oberfläche auf einer gegenüberliegenden Seite einer Schaltungs-Bildungs-Oberfläche (1a) eines Halbleiter-Wafers (1) ist, in dem eine Mehrzahl von Halbleitervorrichtungen gebildet sind,

    Definieren (552) von Trennlinien (1c) zum Trennen des Halbleiter-Wafers in jeweilige getrennte Halbleitervorrichtungen (1d) und zum teilweisen oder vollständigen Freilegen der Masken-Platzier-Seiten-Oberfläche auf einer fehlerhaften Halbleitervorrichtung (1f) aus den jeweiligen Halbleitervorrichtungen, und

    Trennen (36) des Halbleiter-Wafers in jeweilige Halbleitervorrichtungen entlang der definierten Trennlinien (1c) und, zur gleichen Zeit, Entfernen eines freigelegten Teils der fehlerhaften Halbleitervorrichtung (1f) im Fall einer teilweisen Freilegung der Masken-Platzier-Seiten-Oberfläche, um so einen entfernten Bereich als ein Unterscheidungsmerkmal für die fehlerhafte Halbleitervorrichtung zu bilden, oder vollständiges Entfernen der fehlerhaften Halbleitervorrichtung (1f) durch Ausüben von Plasma-Ätzen auf der Masken-Platzier-Seiten-Oberfläche (1 b) des Halbleiter-Wafers (1) im Fall einer vollständigen Freilegung der Masken-Platzier-Seiten-Oberfläche, wodurch die getrennten jeweiligen Halbleitervorrichtungen (1d) von den fehlerhaften Halbleitervorrichtungen (1f) unterscheidbar hergestellt werden.


     
    2. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 1,
    wobei die Maske (5) so auf Basis von Positionsinformation für die fehlerhafte Halbleitervorrichtung in dem Halbleiter-Wafer (1) platziert ist, dass die Oberfläche der fehlerhaften Halbleitervorrichtung (1f) teilweise oder vollständig freigelegt ist.
     
    3. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 1, ferner mit:

    Beschaffen von Positionsinformation für die fehlerhafte Halbleitervorrichtung (1f) in dem Halbleiter-Wafer (1) vor einem Platzieren der Maske (5), wobei

    die Maske (5) auf Basis der beschafften Positionsinformation für die fehlerhafte Halbleitervorrichtung (1f) platziert wird.


     
    4. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 2,
    wobei die Positionsinformation für die fehlerhafte Halbleitervorrichtung (1f) unter Verwendung eines Ergebnisses einer Inspektion (S2) gebildet wird, die an den jeweiligen Halbleitervorrichtungen in dem Halbleiter-Wafer (1) durchgeführt wird.
     
    5. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 1, wobei beim Platzieren der Maske
    die Maske (5) platziert wird, so dass sie die gesamte Masken-Platzier-Seiten-Oberfläche (1 b) des Halbleiter-Wafers bedeckt, und dann
    Teile der Maske (5) entsprechend den jeweiligen Positionen der Trennlinien (1c) auf dem Halbleiter-Wafer (1) entfernt werden, um so teilweise die Oberfläche des Halbleiter-Wafers (1) freizulegen, um die Trennlinien (1c) zu definieren, und ein Teil der Maske (5) oder die gesamte Maske (5) auf der fehlerhaften Halbleitervorrichtung (1f) entfernt wird, um so teilweise oder vollständig die Oberfläche der fehlerhaften Halbleitervorrichtung (1f) freizulegen.
     
    6. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 5,
    wobei die Maske (5) durch Bestrahlen (S52) eines Laserstrahls auf die Maske (5) des Halbleiter-Wafers (1) entfernt wird, während der Laserstrahl relativ entlang der Oberfläche des Halbleiter-Wafers (1) bewegt wird.
     
    7. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 6.
    wobei der Laserstrahl auf Basis von voreingestellten Maskendaten relativ bewegt wird.
     
    8. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 6,
    wobei der Laserstrahl auf Basis von Positionsinformation für die Trennlinien (1c) und Positionsinformation für die fehlerhafte Halbleitervorrichtung (1f) in dem Halbleiter-Wafer (1) relativ bewegt wird.
     
    9. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 1,
    wobei die Maske (5) derart platziert wird, dass ein nahezu mittlerer Bereich der Oberfläche der fehlerhaften Halbleitervorrichtung (1f) in einer nahezu kreisförmigen Form freigelegt wird.
     
    10. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 1, ferner mit:

    Entfernen (S7) der jeweiligen Masken von der Masken-Platzier-Seiten-Oberfläche (1b) des Halbleiter-Wafers (1) nach einem Trennen der Halbleiter und Entfernen (S52) des freigelegten Teils.


     
    11. Herstellungsverfahren für Halbleitervorrichtungen nach Anspruch 4, wobei
    nach der Inspektion (S2) der jeweiligen Halbleitervorrichtungen ein Verdünnen des Halbleiter-Wafers (1) ausgeführt wird und dann
    die Maske (5) auf dem verdünnten Halbleiter-Wafer (1) platziert wird.
     


    Revendications

    1. Procédé de fabrication pour des dispositifs semi-conducteurs comprenant le fait :

    de placer (551) un masque (5) sur une surface (1b) côté placement de masque qui est une surface sur un côté opposé d'une surface (la) de formation de circuit d'une plaquette semi-conductrice (1) où une pluralité de dispositifs semi-conducteurs sont formés ;

    de définir (552) des lignes de découpe (1c) pour découper la plaquette semi-conductrice en dispositifs semi-conducteurs séparés (1d) respectifs et exposer partiellement ou totalement la surface (1b) côté placement de masque sur un dispositif semi-conducteur défectueux (1f) parmi les dispositifs semi-conducteurs respectifs ; et

    de découper (36) la plaquette semi-conductrice en dispositifs semi-conducteurs respectifs le long des lignes de découpe (1c) définies et au même temps, dans le cas d'une exposition partielle de la surface côté placement de masque, d'enlever une partie exposée du dispositif semi-conducteur défectueux (1f) afin de former une partie enlevée comme une marque de distinction du dispositif semi-conducteur défectueux ou, dans le cas d'une exposition totale de la surface côté placement de masque, d'enlever totalement le dispositif semi-conducteur défectueux (1f), en appliquant une gravure par plasma à la surface (1b) côté placement de masque de la plaquette semi-conductrice (1), ainsi les dispositifs semi-conducteurs séparés (1d) respectifs sont fabriqués distinctement des dispositifs semi-conducteurs défectueux (1f).


     
    2. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 1,
    dans lequel le masque (5) est placé de manière à exposer partiellement ou totalement la surface du dispositif semi-conducteur défectueux (1f) sur la base d'informations de position pour le dispositif semi-conducteur défectueux dans la plaquette semi-conductrice (1).
     
    3. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 1, comprenant en outre le fait:

    d'obtenir des informations de position pour le dispositif semi-conducteur défectueux (1f) dans la plaquette semi-conductrice (1) avant de placer le masque (5), où

    la masque (5) est placé sur la base des informations de position obtenues pour le dispositif semi-conducteur défectueux (1f).


     
    4. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 2,
    dans lequel les informations de position pour le dispositif semi-conducteur défectueux (1f) sont formés en utilisant le résultat d'une inspection (S2) effectuée sur les dispositifs semi-conducteurs respectifs dans la plaquette semi-conductrice (1).
     
    5. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 1, dans lequel dans l'étape de placement du masque,
    le masque (5) est placé de manière à couvrir la totalité de la surface (1b) côté placement de masque de la plaquette semi-conductrice, et ensuite
    des parties du masque (5) sont enlevées en conformité avec les positions respectives des lignes de découpe (1c) sur la plaquette sem-conductrice (1), de manière à exposer partiellement la surface de la plaquette semi-conductrice (1) pour définir les lignes de découpe (1c), et une partie du masque (5) en entier sur le dispositif semi-conducteur défectueux (1f) est enlevé(e) de manière à exposer partiellement ou totalement semi-conducteur défectueux (1f).
     
    6. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 5,
    dans lequel le masque (5) est enlevé par irradiation (S52) du masque (5) de la plaquette semi-conductrice (1) par un faisceau laser tout en conférant un mouvement relatif au faisceau laser le long de la surface de la plaquette semi-conductrice (1).
     
    7. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 6, dans lequel le faisceau laser se déplace en un mouvement relatif sur la base de données de masque prédéfinies.
     
    8. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 6,
    dans lequel le faisceau laser se déplace en un mouvement relatif, sur la base d'informations de position pour les lignes de découpe (1c) et des informations de position pour le dispositif semi-conducteur défectueux (1f) dans la plaquette semi-conductrice (1).
     
    9. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 1,
    dans lequel le masque (5) est placé de manière à exposer une zone presque centrale de la surface du dispositif semi-conducteur défectueux (1f) en une forme presque circulaire.
     
    10. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 1, comprenant en outre le fait :

    d'enlever (S7) les masques respectifs de la surface (1b) côté placement de masque de la plaquette semi-conductrice (1), après avoir découpé le semi-conducteur et enlevé (S52) la partie exposée.


     
    11. Procédé de fabrication pour des dispositifs semi-conducteurs tel que défini dans la revendication 4, dans lequel
    après l'inspection (S2) des dispositifs semi-conducteurs respectifs, l'amincissement de la plaquette semi-conductrice (1) est mis en oeuvre, et ensuite
    le masque (5) est placé sur la plaquette semi-conductrice (1) amincie.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description