(19)
(11)EP 1 844 394 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
26.07.2017 Bulletin 2017/30

(21)Application number: 06706256.2

(22)Date of filing:  17.01.2006
(51)Int. Cl.: 
G06F 9/44  (2006.01)
(86)International application number:
PCT/EP2006/000351
(87)International publication number:
WO 2006/077068 (27.07.2006 Gazette  2006/30)

(54)

OPERATING-SYSTEM-FRIENDLY BOOTLOADER

BETRIEBSSYSTEMFREUNDLICHER BOOTLOADER

DISPOSITIF D'INITIALISATION DE SYSTEME D'EXPLOITATION CONVIVIAL


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR

(30)Priority: 22.01.2005 US 40798

(43)Date of publication of application:
17.10.2007 Bulletin 2007/42

(60)Divisional application:
17175703.2

(73)Proprietor: Telefonaktiebolaget LM Ericsson (publ)
164 83 Stockholm (SE)

(72)Inventors:
  • SVENSSON Mats
    SE-224 74 Lund (SE)
  • ROSENBERG Michael
    SE-247 33 Södra Sandby (SE)
  • BAUER Niclas
    SE-23734 Bjärred (SE)
  • AULIN Peter
    SE-217 53 Malmö (SE)

(74)Representative: Ericsson 
Patent Development Torshamnsgatan 21-23
164 80 Stockholm
164 80 Stockholm (SE)


(56)References cited: : 
US-A- 5 155 833
US-A1- 2002 138 156
US-A- 6 012 142
  
  • HYDE J: "HOW TO MAKE PENTIUM PROS COOPERATE" BYTE, MCGRAW-HILL INC. ST PETERBOROUGH, US, vol. 21, no. 4, April 1996 (1996-04), pages 177-178, XP000586039 ISSN: 0360-5280
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description


[0001] This invention relates to initialization of electronic systems having multiple programmable processors.

[0002] The process of starting, or booting up, an electronic system having a programmable processor connected to one or more memory devices for storing program instructions, or code, and data is not as simple as it might seem at first glance. An important part of the reason for this is the need for the processor to begin operation in a well-defined state.

[0003] The traditional ways of loading program code and data to a bare system are either by "pushing" the code and data into the system's random-access memory (RAM) directly or by using a bootloader. The bootloader, which is sometimes called a boot loader or a bootstrap loader, is a set of instructions (i.e., program code, sometimes called "boot code") that can be either "pushed" into the system's RAM or loaded into the RAM from a non-volatile memory, such as read-only memory (ROM). In its execution by the processor, the bootloader then "drags" in the rest of the code and data and starts the system.

[0004] Examples of prior mechanisms for starting processor systems, including bootloaders, are U.S. Patents No. 5,652,886 to Tulpule et al. and No. 6,490,722 to Barton et al. and U.S. Patent Application Publication No. US 2002/0138156 A1 to Wong et al. Barton et al., for example, describes a two-stage bootloader in which the second stage finds, verifies, and loads the operating system. In Wong et al., a multiprocessor system uses a master processor coupled to a ROM to transfer boot code to slave processors, with memory controllers in the slave processors denying memory access requests until the boot code has been transferred to their RAMs.

[0005] As indicated by Barton et al. and Wong et al., for example, starting up a multi-processor system, which can be generally considered as having a master or host processor, i.e., the system that orders the boot, and one or more slave or client processors, i.e., the system to be booted, is even more complicated than starting up a single-processor system.
U.S. Patent No. 5,155,833 to Cullison et al. describes a master-slave multiprocessor in which the slave processor has a RAM array that serves at initialization time as the slave processor's boot memory and during normal operation as the slave processor's cache memory. The master processor writes the slave processor's boot program into the RAM array, e.g., after a system reset.

[0006] Advantages of the "push" method are that it requires no code to execute in the slave during boot and that the only synchronization required is to hold the slave in a reset state and release it when loading is finished. Nevertheless, the "push" method works only when the memory or memories of the slave are visible to the host. This visibility can be implemented in several ways. For example, a memory may be visible on the address and data busses of both the host and the slave processors or direct memory access (DMA) transfers may be allowed from the host's memory or memories to the slave's memory or memories.

[0007] When the slave's memory to be loaded is invisible to the host, the "push" method cannot be used. In that situation, some form of bootloading must be used. As noted above, the bootloader technique requires either that boot code can be pushed onto the slave (which in this case is not possible) or that the slave can load code from a non-volatile memory. The bootloader then initiates a transfer of code from the host to the slave and finishes loading the memory.

[0008] Multi-processor systems in which some or all of a slave's memory is not visible to a host are possible. In such systems, it can be advantageous to take advantage of well-established software frameworks for loading and interprocessor communication, which render traditional bootloaders undesirable. Moreover, a bootloader can conflict with the operating system, which can be said to want to have control over the entire system and all of the memory.

[0009] Among the problems faced when integrating a bootloader with an operating system (OS) are ensuring that code that is not yet loaded is not executed, efficiently loading code to a memory or memories invisible to the host, and synchronizing with the host the loading and booting of the slave(s). Moreover, it is necessary to determine which portions of the system must be loaded to memories visible to both host and slave processors and how the binary image to be loaded should be arranged for the bootloader to work together with the OS. Another issue that can be important is the integration of the bootloader and the OS, as an already established framework for communication between host and slave then can be used during loading. Such a framework typically would include one or more primitives for communication that rely on OS-features.

SUMMARY



[0010] This invention provides, in one aspect, a method of loading information including a bootloader into a slave processor in a multi-processor system that includes a master processor and the slave processor. The method includes the steps of resetting the slave processor and holding the slave processor in a reset state; pushing a first part of the information into a first memory that is accessible by the master and slave processors, the first part of the information including the bootloader; booting the slave processor; starting an operating system in the slave processor, including blocking scheduling of processes having program code located in a second memory that is accessible by the slave processor and inaccessible by the master processor; reserving an intermediate storage area in the first memory; sending to the master processor information about a location and size of the intermediate storage area reserved; based on the sent information, loading the intermediate storage area with a second part of the information to be loaded into the second memory; sending a first message to the slave processor that indicates the intermediate storage area has been loaded and whether loading is finished or more information is to be loaded; copying information in the intermediate storage area to the second memory; sending a second message to the master processor that indicates that information in the intermediate storage area has been copied; and releasing the blocking of scheduling of processes having program code located in the second memory.

[0011] In another aspect of the invention, a multi-processor system includes a host processor, at least one client processor, a first memory accessible by the host and client processors, a second memory accessible by the client processor and not accessible by the host processor, and a bootloader. The first memory includes an intermediate storage area, and the bootloader includes a host part and a client part. The host part is loadable into the first memory and has a first stage and a second stage. The first stage resets and holds the client processor in a reset state and pushes information into the first memory. The second stage is initiated by the client part, loads the intermediate storage area with information to be loaded to the second memory, and sends to the client part a first message indicating the intermediate storage area is loaded. The client part is loadable into the first memory, starts an operating system including initially blocking scheduling of all processes having program code located in the second memory, copies information loaded into the intermediate storage area to the second memory, sends to the host part a second message indicating information has been copied, and releasing the blocking of scheduling of processes having program code located in the second memory.

[0012] In another aspect of the invention, a computer-readable medium contains a computer program for loading information including a bootloader into a slave processor in a multi-processor system that includes a master processor and the slave processor. The computer program performs the steps of the method summarized above.

BRIEF DESCRIPTION OF THE DRAWINGS



[0013] The various features, objects, and advantages of this invention will be understood by reading this description in conjunction with the drawings, in which:

FIG. 1 depicts a multi-processor system;

FIG. 2 is a flowchart of an OS-friendly bootloader; and

FIG. 3 depicts an example of an organization of an intermediate storage area.


DETAILED DESCRIPTION



[0014] As noted above, a conventional bootloader can conflict with the operating system of a multi-processor system. This application describes an OS-friendly bootloader and methods that meet the challenge of integrating an OS with a bootloader in systems in which the host and a client have a communication mechanism that requires the OS for the mechanism to work and the client has two memory systems: one visible to both host and client and one visible only to the client.

[0015] FIG. 1 depicts such a multi-processor system 100 that includes a host processor 102 and a client processor 104. It will be appreciated that although FIG. 1 shows one client processor 104, more can be provided. It will also be appreciated that the host and client processors may be any programmable electronic processors. In the example depicted in FIG. 1, the processor 102 is shown as the central processing unit (CPU) of an advanced RISC machine (ARM), and the processor 104 is shown as the CPU of a digital signal processor (DSP) device. The dashed line in FIG. 1 depicts the hardware boundary between the host and slave devices, in this example, the ARM and the DSP, and also a non-volatile memory 106. The memory 106 may be a ROM, a flash memory, or other type of non-volatile memory device.

[0016] Most commercially available DSP devices include on-chip memories, and as indicated in FIG. 1, the DSP includes "internal" single-access RAM (SARAM) and dual-access RAM (DARAM) 108, as well as an "external" RAM (XRAM) 110. An intermediate storage area, indicated by the dashed line, is defined within the memory 108 as described in more detail below. The arrows in FIG. 1 indicate access paths, e.g., busses and DMA paths, between the CPUs and the memories. The ARM host CPU 102 can access the non-volatile memory 106 and the SARAM and DARAM 108 of the DSP, but not the DSP's XRAM 110, and the DSP slave CPU 104 can access all of the RAMs 108, 110.

[0017] The SARAM and DARAM 108 can be loaded from the non-volatile memory 106 by the trivial "push" method. When code needs to be loaded to the XRAM 110 during boot, however, a bootloader solution is required because the XRAM 110 is invisible to, i.e., not accessible by, the CPU 102 and so boot code cannot be pushed to the XRAM 110.

[0018] As described in more detail below and in connection with the flow chart of FIG. 2, an OS-friendly bootloader advantageously has a host part and a client part that is loaded into a memory or memories visible to both the master and the slave (e.g., SARAM and DARAM 108).

[0019] The host part of the OS-friendly bootloader may be considered as including two stages or modes of operation. The first stage resets and holds the slave 104 in the reset state (Step 202) and pushes information (program instructions and/or data) (Step 204) in the usual way from the non-volatile memory 106 into the commonly visible memories 108. The information pushed into these memories is mainly the bootloader, the OS, and any necessary start-up code for the OS. It should be appreciated that an application or applications or parts thereof may also be pushed into these memories at start-up and may start executing during the loading of the "external" memory 110. When this "push" is finished (Step 206), the slave 104 is allowed to boot (Step 208) and to start up the OS (e.g., it is released from the reset state) and its normal communication mechanisms (Step 210). The host part then awaits a message from the slave, which initiates operation of its second stage as described in more detail below.

[0020] The slave part of the OS-friendly bootloader that is loaded ("pushed" by the host part's first stage) into the commonly visible memories 108 starts the operating system, carrying out the following operations (Step 210). First, interrupt handlers are created. The code for the interrupt handlers must be located in the memory that is already loaded because an interrupt may occur at any time. Second, data structures (e.g., process control blocks and stacks) of common processes, i.e., processes that run in both the host and the slave, are created. It should be understood that since these common processes have not yet executed, their code may be loaded at a later time and may very well be located in "external" memory visible only to the slave, e.g., XRAM 110. Third, the system idle process is created. The code for the idle process must be located in the memory that is already loaded because the idle process is the process selected to run by the OS if there is nothing useful to do. Fourth, the scheduling of at least all processes residing in, i.e., having program code or data located in, the "external" memory 110 is blocked. Execution of processes residing in the "internal" memory can thus advantageously start or continue in parallel with the loading of the "external" memory as noted above. It is also possible to stop scheduling all processes except the idle process, but this is not necessary. Making this blocking the last thing done before the OS scheduler switches on ensures that the code in these processes will not run when the scheduler releases. Finally, the OS scheduler is released, which allows the OS to start executing code and scheduling processes. It will be understood that since at least all external-memory-process scheduling was blocked, all that the OS can now do is schedule interrupts and the idle process.

[0021] At this point, the slave 104 is partly up and running. The slave part of the OS-friendly bootloader has been loaded, and the slave's idle process is executing. The slave's OS can schedule and execute code in response to interrupts and can schedule the idle process and any unblocked processes having code residing in internal memory. OS mechanisms for which all code and data accesses are in memory that has already been loaded (SARAM and DARAM 108, in this example) are available, including the usual communication mechanisms. These OS communication mechanisms, being high-level abstractions of DMA, shared memory, and structured registers, are more capable than simple semaphores and enable the host processor to communicate efficiently with a processor (the slave) that has not completely started, which is to say a processor that is executing mainly only the OS, interrupt services, and processes residing in "internal" RAM.

[0022] The idle process reserves a block of memory in the slave's heap of memory that is located in the memory visible to the host, such as "internal" memory 108 (Step 212). As described in more detail below, this reserved block of memory is used for intermediate storage of information (code and/or data) to be transferred to the slave-private memory, i.e., the memory that is invisible to the host, such as "external" XRAM 110. The slave's idle process advantageously uses the established communication mechanisms to send to the host (Step 214) information about the address and size or length of the intermediate storage area reserved in the previous step. After sending the information, which may be contained in one or more suitable messages, the slave blocks, awaiting a message from the host. While "blocked", the slave does not conduct any further loading activities until it receives the host's response.

[0023] It will be understood that whether the slave's OS acts on an interrupt at this stage depends on the nature of the interrupt. Since many OS mechanisms (like those used to communicate with the host, for example) rely on interrupts, and it cannot be known in advance when an interrupt will occur, all interrupt code must have been loaded into "internal" memory. In that respect, interrupts are served during the second stage of the bootloading. Nevertheless, if an interrupt is to trigger a chain of events such as processes starting to do some data processing and the code or data for those processes are located or will be located in "external" memory, the interrupt is blocked and the interrupt service puts the request in the "in-queue" of that process so that the request will be served after booting has finished and that process can execute.

[0024] On receipt of the slave's information, the second stage of the host bootloader fills the intermediate storage area with information (code and/or data) to be loaded into the slave's invisible memory (Step 216). Code and data is pushed to the intermediate storage area in the usual way because this area is memory that both processors can access, but the push is activated through the OS communication mechanisms.

[0025] The host now sends a message to the slave (Step 218) that indicates the intermediate storage area has been loaded and whether loading is finished or more code and/or data is available. This is the message the slave is waiting for. The host in turn now blocks, awaiting a message from the slave. The slave copies the contents of the intermediate storage area to appropriate locations in its slave-private memory (Step 220), thereby implementing its actual loading. The slave then sends a message to the host (Step 222) that indicates that the slave has copied the contents of the intermediate storage area.

[0026] If there is more code and/or data to load (Step 224), this cycle of copying and messaging (Steps 216-224) can be repeated as many times as required. When the loading is finished, i.e., when no more information needs to be copied to the slave, the slave releases the blocking of processes that were blocked earlier, thereby allowing scheduling of code in its slave-private memory (Step 226). Loading is now complete.

[0027] As described above, the host fills the intermediate storage area in the memory 108 with code and data that the slave further copies to end destinations in the slave-private memory 110. Perhaps the simplest way of doing this is to precede all code and data in the intermediate storage area with a tag that contains the destination address and length of the block to be loaded. FIG. 3 depicts one example of such an organization of the intermediate storage area. A block of code and/or data to be transferred into the intermediate storage area includes a header that indicates the length of the block and where it is to be loaded in the slave memory, i.e., the destination address. As indicated by the dashed lines in FIG. 3, several such blocks may be concatenated in the intermediate storage area.

[0028] The information (code and data) to be loaded can be arranged in many ways in the intermediate storage area and memories. Often the information is arranged as blocks of consecutive information that are to be loaded to different addresses, and thus an arbitrarily chosen size of the intermediate storage area may not match the sizes of all such blocks. Still, it should be understood that the system will operate more efficiently when the intermediate storage area is always filled. This means that if the blocks to be loaded are smaller than this area, a transfer of several (smaller) blocks should be done at the same time. This also means that a block should be split if it is larger than the remaining part of the intermediate storage area, and one part transferred to the intermediate storage area with the remaining part transferred in the next block. Moreover, if a block is several times larger than the intermediate storage area, it may have to be split more than once. All of this splitting and concatenation is done in the host part of the OS-friendly bootloader in ways that are well known to computer scientists. From the point of view of data communications engineers, the host part of the OS-friendly bootloader is thus a kind of "transport layer".

[0029] The artisan will understand the benefit of this splitting and concatenation of information into transfer blocks. Some kind of communication mechanism is required to perform the actual transfers of information between memories, and whatever the mechanism used, fewer large transfers are typically preferable to more small transfers. A kept-full intermediate storage area can make the most efficient use of the available bandwidth by advantageously minimizing overhead on the communications channel. Each message requires some amount of administration and administrative information, and so fewer messages means less overhead.

[0030] A good example of the benefit of block splitting and concatenation effect is DMA as the communication mechanism. DMA typically requires some setup overhead (i.e., it takes some time to set up), but then DMA is very efficient once it has been started because transfers can be carried out in minimal CPU cycles. In order to gain the greatest benefit from the use of DMA, the largest DMA transfer permitted by the hardware should be done every time. Thus, it is currently believed to be advantageous to set the size of the intermediate storage area to the maximum DMA block size.

[0031] The host part of the OS-friendly bootloader should "know" when to leave its first stage (loading information by pushing it into memory) and to enter its second stage (loading information through one or more communication mechanisms). After all, the host cannot push information into memory that is invisible to it. Although the slave sends a message to the host part when it has reached the idle process, this may not be enough for the host part to tell the slave to start executing. This transition from pushing to bootloading will be seen as a change from the paradigm of passive loading (i.e., no code executing in the slave) to the paradigm of active loading (i.e., a partly alive, executing slave).

[0032] One way for the host part to know when to change stages is to tag the code and data to be loaded with information on what memory it shall be loaded to. For example, information intended for the invisible memory could include a tag or tags that indicate the information is to be loaded to the invisible memory. The absence of such a tag could indicate that the information is to be loaded to the visible memory, although it will be appreciated that a tag explicitly indicating that the information is to be loaded to the visible memory could also be used. This enables the host to do two passes over the information and load only the information required in each pass. In the first pass, things that go into the internal memory would be found and loaded, and in the second pass, things that go into the external memory would be found and loaded.

[0033] Another way, which currently appears to be simpler, is to arrange the slave-private memory such that all of it resides above (or below) a predetermined address. The information to be transferred is then sorted accordingly, with all sections of code and data to be loaded to the slave-private memory put at the end (or the beginning) of the sorted image. Then, all the host part of the OS-friendly bootloader has to do is to enter its second stage when an address larger (or smaller) than the predetermined (boundary) address is encountered.

[0034] In order to save memory or increase code integrity and platform security on the host side, information to be loaded to the slave can also be pre-processed in several different ways. For example, the information may be compressed according to a suitable algorithm, thereby reducing the size of the memory needed for it on the host side. For another example, the information may be encrypted, thereby strengthening platform security, as a potential hacker will not be able to disassemble the information easily. It is currently believed that encryption is valuable if the information to be loaded to the slave is stored in the internal file system of the host, where the information is available (at least in theory) to anyone.

[0035] From this description, it will be understood that OS mechanisms are available to the slave part of the OS-friendly bootloader that is executed by the slave processor and that the slave can reuse existing OS-dependent code required for communication. Moreover, the OS-friendly bootloader uses loading resources (e.g., DMA) efficiently, with the host part automatically deciding when to switch from a first stage, or push mode, to a second stage, or bootloader mode.

[0036] It is expected that this invention can be implemented in a wide variety of environments, including for example mobile communication devices. Newer ones of such devices can employ the OS-friendly bootloader described here to boot their DSPs, which may be provided to handle multimedia tasks, in cooperation with their main-processor software systems.

[0037] The OS-friendly bootloader described here takes the operating system into account and actually executes on an operating system. The host is fully running when the slave is booted or re-rebooted. This bootloader does not require the host processor to be in a certain state in order to start up the slave processor. Indeed, the startup of the slave processor can be carried out any time during the execution of the host processor software. The OS-friendly bootloader does not need a special executable file that is run in the slave processor while information is being loaded to it from the host processor and the host-inaccessible RAM. One executable is linked to all of the slave processor's memories. The slave is booted before all code is loaded, but code that is linked to host-inaccessible memory is not run until it is loaded with the help of code that is linked to the slave processor's host-accessible memory.

[0038] It will therefore be understood that the OS-friendly bootloader described here also makes it possible to change software executing in the slave processor and to start slave execution of an application software before it is completely loaded. One or more application processes can be chosen for "pushing" with the bootloader into the slave processor's host-accessible memory, and those processes will start executing at the same point in time as the slave processor's host-inaccessible memory begins to be loaded.

[0039] This capability can be important in many devices and many use cases. In a mobile telephone, for example, such use cases include making a call, receiving a call, compressing/decompressing speech, playing music files, etc. With the OS-friendly bootloader described here, one can load and execute new software in the slave processor virtually anytime the host processor is running.

[0040] It will be appreciated that procedures described above are carried out repetitively as necessary. To facilitate understanding, many aspects of the invention are described in terms of sequences of actions that can be performed by, for example, elements of a programmable computer system. It will be recognized that various actions could be performed by specialized circuits (e.g., discrete logic gates interconnected to perform a specialized function or application-specific integrated circuits), by program instructions executed by one or more processors, or by a combination of both.

[0041] Moreover, the invention described here can additionally be considered to be embodied entirely within any form of computer-readable storage medium having stored therein an appropriate set of instructions for use by or in connection with an instruction-execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch instructions from a medium and execute the instructions. As used here, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction-execution system, apparatus, or device. The computer-readable medium can be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a non-exhaustive list) of the computer-readable medium include an electrical connection having one or more wires, a portable computer diskette, a RAM, a ROM, an erasable programmable read-only memory (EPROM or Flash memory), and an optical fiber.

[0042] Thus, the invention may be embodied in many different forms, not all of which are described above, and all such forms are contemplated to be within the scope of the invention. For each of the various aspects of the invention, any such form may be referred to as "logic configured to" perform a described action, or alternatively as "logic that" performs a described action.

[0043] It is emphasized that the terms "comprises" and "comprising", when used in this application, specify the presence of stated features, integers, steps, or components and do not preclude the presence or addition of one or more other features, integers, steps, components, or groups thereof.

[0044] The particular embodiments described above are merely illustrative and should not be considered restrictive in any way. The scope of the invention is determined by the following claims, and all variations and equivalents that fall within the range of the claims are intended to be embraced therein.


Claims

1. A method of loading information into a slave processor (104) in a multi-processor system (100) that includes a master processor (102) and the slave processor, the information including a bootloader, comprising the steps of:

a) resetting the slave processor (104) and holding the slave processor (104) in a reset state;

b) pushing a first part of the information into a first memory (108) that is accessible by the master processor (102) and the slave processor (104), the first part of the information including the bootloader;

c) booting the slave processor (104);

d) starting an operating system in the slave processor (104), including blocking scheduling of processes having program code located in a second memory (110) that is accessible by the slave processor (104) and inaccessible by the master processor (102);

e) reserving an intermediate storage area in the first memory (108);

f) sending to the master processor (102) information about a location and size of the intermediate storage area reserved;

g) based on the sent information, loading the intermediate storage area with a second part of the information to be loaded into the second memory (110);

h) sending a first message to the slave processor (104) that indicates the intermediate storage area has been loaded and whether loading is finished or more information is to be loaded;

i) copying information in the intermediate storage area to the second memory (110);

j) sending a second message to the master processor (102) that indicates that information in the intermediate storage area has been copied; and

k) releasing the blocking of scheduling of processes having program code located in the second memory (110).


 
2. The method of claim 1, further comprising the step of, if there is more information to be loaded, repeating steps g-j until no more information is to be loaded.
 
3. The method of claim 1, wherein step d) includes creating interrupt handlers and creating data structures of processes that run in both the master processor (102) and the slave processor (104).
 
4. The method of claim 1, wherein the first part of the information pushed into the first memory (108) further includes the operating system and at least a portion of at least one application.
 
5. The method of claim 1, wherein step d) includes blocking scheduling of all processes except an idle process.
 
6. The method of claim 1, wherein step g) includes preceding the second part of the information to be loaded into the second memory (110) with at least one tag that indicates an address in the second memory (110) and a length of the information to be loaded.
 
7. The method of claim 1, wherein step g) includes splitting the second part of the information to be loaded into the second memory (110) into blocks and loading the intermediate storage area with a first block.
 
8. The method of claim 7, further comprising the step of repeating steps g-j for each block in succession.
 
9. The method of claim 1, wherein the first part of the information pushed into the first memory (108) includes at least one tag that indicates whether the information is to be loaded to the second memory (110).
 
10. The method of claim 1, wherein the second part of the information to be loaded to the second memory (110) is at least one of compressed and encrypted.
 
11. A multi-processor system (100), comprising:

a host processor (102);

at least one client processor (104);

a first memory (108) accessible by the host processor and the client processor, wherein the first memory includes an intermediate storage area;

a second memory (110) accessible by the client processor and not accessible by the host processor; and

a bootloader that includes:

a host part that is loadable into the first memory, that has a first stage that resets and holds the client processor (104) in a reset state and pushes information into the first memory (108), and that has a second stage that is initiated by the client part, that loads the intermediate storage area with information to be loaded to the second memory (110), and that sends to the client part a first message indicating the intermediate storage area is loaded; and

a client part that is loadable into the first memory (108), that starts an operating system including initially blocking scheduling of all processes having program code located in the second memory (110), that copies information loaded into the intermediate storage area to the second memory (110), that sends to the host part a second message indicating information has been copied, and that releases blocking scheduling of all processes having program code located in the second memory.


 
12. The system of claim 11, wherein the information pushed into the first memory (108) by the first stage includes the client part of the bootloader and the operating system, and the second stage enables the host and client processors (102, 104) to exchange messages.
 
13. The system of claim 12, wherein the information pushed into the first memory (108) by the first stage includes at least a portion of at least one application.
 
14. The system of claim 11, wherein the client part initially blocks scheduling of all processes except the idle process.
 
15. The system of claim 11, wherein the idle process sends to the host processor (102) information about an address and a length of the intermediate storage area.
 
16. The system of claim 11, wherein information to be loaded into the second memory (110) includes at least one tag that indicates an address in the second memory (110) and a length of the information to be loaded.
 
17. The system of claim 11, wherein the intermediate storage area is organized as blocks of information, and each block includes a header that indicates a length of the block and an address for the block in the second memory (110).
 
18. The system of claim 11, wherein information pushed into the first memory (108) includes at least one tag that indicates whether the information is to be loaded to the second memory (110).
 
19. The system of claim 11, wherein information to be loaded to the second memory (110) is at least one of compressed and encrypted.
 
20. A computer-readable medium containing a computer program for loading information into a slave processor (104) in a multi-processor system (100) that includes a master processor (102) and the slave processor (104), wherein the information includes a bootloader and the computer program performs the steps of:

a) resetting the slave processor (104) and holding the slave processor (104) in a reset state;

b) pushing a first part of the information into a first memory (108) that is accessible by the master processor (102) and the slave processor (104), the first part of the information including the bootloader;

c) booting the slave processor (104);

d) starting an operating system in the slave processor (104), including blocking scheduling of processes having program code located in a second memory (110) that is accessible by the slave processor (104) and inaccessible by the master processor (102);

e) reserving an intermediate storage area in the first memory (108);

f) sending to the master processor (102) information about a location and size of the intermediate storage area reserved;

g) based on the sent information, loading the intermediate storage area with a second part of the information to be loaded into the second memory (110);

h) sending a first message to the slave processor (104) that indicates the intermediate storage area has been loaded and whether loading is finished or more information is to be loaded;

i) copying information in the intermediate storage area to the second memory (110);

j) sending a second message to the master processor (102) that indicates that information in the intermediate storage area has been copied; and

k) releasing the blocking of scheduling of processes having program code located in the second memory (110).


 
21. The computer readable medium of claim 20, wherein the computer program further performs the step of, if there is more information to be loaded, repeating steps g-j until no more information is to be loaded.
 
22. The computer readable medium of claim 20, wherein step g) includes preceding the second part of the information to be loaded into the second memory (110) with at least one tag that indicates an address in the second memory (110) and a length of the information to be loaded.
 
23. The computer readable medium of claim 20, wherein step g) includes splitting the second part of the information to be loaded into the second memory (110) into blocks and loading the intermediate storage area with a first block.
 


Ansprüche

1. Verfahren zum Laden von Informationen in einen Slave-Prozessor (104) in einem Mehrprozessorsystem (100), das einen Master-Prozessor (102) und den Slave-Prozessor umfasst, wobei die Informationen einen Bootloader umfassen, umfassend die folgenden Schritte:

a) Rücksetzen des Slave-Prozessors (104) und Halten des Slave-Prozessors (104) in einem rückgesetzten Zustand;

b) Pushen eines ersten Teils der Informationen in einen ersten Speicher (108), auf den durch den Master-Prozessor (102) und den Slave-Prozessor (104) zugegriffen werden kann, wobei der erste Teil der Informationen den Bootloader umfasst;

c) Booten des Slave-Prozessors (104);

d) Starten eines Betriebssystems im Slave-Prozessor (104), umfassend ein Sperren des Disponierens von Prozessen mit Programmcode, der sich in einem zweiten Speicher (110) befindet, auf den durch den Slave-Prozessor (104) zugegriffen werden kann und auf den durch den Master-Prozessor (102) nicht zugegriffen werden kann;

e) Reservieren eines Zwischenspeicherbereichs im ersten Speicher (108);

f) Senden von Informationen über einen Speicherort und eine Größe des reservierten Zwischenspeicherbereichs an den Master-Prozessor (102);

g) Laden basierend auf den gesendeten Informationen des Zwischenspeicherbereichs mit einem zweiten Teil der Informationen, der in den zweiten Speicher (110) geladen werden soll;

h) Senden einer ersten Nachricht an den Slave-Prozessor (104), die angibt, dass der Zwischenspeicherbereich geladen wurde und ob das Laden abgeschlossen ist oder mehr Informationen geladen werden sollen;

i) Kopieren von Informationen im Zwischenspeicherbereich in den zweiten Speicher (110) ;

j) Senden einer zweiten Nachricht an den Master-Prozessor (102), die angibt, dass Informationen im Zwischenspeicherbereich kopiert wurden; und

k) Aufheben der Sperrung des Disponierens von Prozessen mit Programmcode, der sich im zweiten Speicher (110) befindet.


 
2. Verfahren nach Anspruch 1, ferner umfassend, wenn mehr Informationen geladen werden sollen, den Schritt des Wiederholens der Schritte g bis j, bis keine Informationen mehr geladen werden sollen.
 
3. Verfahren nach Anspruch 1, wobei Schritt d) ein Erzeugen von Interrupthandlern und Erzeugen von Datenstrukturen von Prozessen umfasst, die sowohl im Master-Prozessor (102) als auch im Slave-Prozessor (104) ausgeführt werden.
 
4. Verfahren nach Anspruch 1, wobei der erste Teil der Informationen, der in den ersten Speicher (108) gepusht wird, ferner das Betriebssystem und mindestens einen Teil mindestens einer Anwendung umfasst.
 
5. Verfahren nach Anspruch 1, wobei Schritt d) ein Sperren des Disponierens aller Prozesse mit Ausnahme eines Leerlaufprozesses umfasst.
 
6. Verfahren nach Anspruch 1, wobei Schritt g) ein Voranstellen mindestens eines Tags, der eine Adresse im zweiten Speicher (110) und eine Länge der zu ladenden Informationen angibt, vor den zweiten Teil der Informationen umfasst, der in den zweiten Speicher (110) geladen werden soll.
 
7. Verfahren nach Anspruch 1, wobei Schritt g) ein Teilen des zweiten Teils der Informationen, der in den zweiten Speicher (110) geladen werden soll, in Blöcke und Laden des Zwischenspeicherbereichs mit einem ersten Block umfasst.
 
8. Verfahren nach Anspruch 7, ferner umfassend den Schritt des Wiederholens der Schritt g bis j für jeden Block in Folge.
 
9. Verfahren nach Anspruch 1, wobei der erste Teil der Informationen, der in den ersten Speicher (108) gepusht wird, mindestens einen Tag umfasst, der angibt, ob die Informationen in den zweiten Speicher (110) geladen werden sollen.
 
10. Verfahren nach Anspruch 1, wobei der zweite Teil der Informationen, der in den zweiten Speicher (110) geladen werden soll, mindestens eines von komprimiert und verschlüsselt ist.
 
11. Mehrprozessorsystem (100), umfassend:

einen Hostprozessor (102);

mindestens einen Clientprozessor (104);

einen ersten Speicher (108), auf den durch den Hostprozessor und den Clientprozessor zugegriffen werden kann, wobei der erste Speicher einen Zwischenspeicherbereich umfasst;

einen zweiten Speicher (110), auf den durch den Clientprozessor zugegriffen werden kann und auf den durch den Hostprozessor nicht zugegriffen werden kann; und

einen Bootlader, der umfasst:

einen Host-Teil, der in den ersten Speicher geladen werden kann und der eine erste Stufe aufweist, die den Clientprozessor (104) zurücksetzt und in einem rückgesetzten Zustand hält und Informationen in den ersten Speicher (108) pusht, und der eine zweite Stufe aufweist, die vom Client-Teil initiiert wird und die den Zwischenspeicherbereich mit Informationen lädt, die in den zweiten Speicher (110) geladen werden sollen, und die eine erste Nachricht, die angibt, dass der Zwischenspeicherbereich geladen ist, an den Client-Teil sendet; und

einen Client-Teil, der in den ersten Speicher (108) geladen werden kann und der ein Betriebssystem startet, umfassend ein anfängliches Sperren des Disponierens aller Prozesse mit Programmcode, der sich im zweiten Speicher (110) befindet, der Informationen, die in den Zwischenspeicherbereich geladen sind, in den zweiten Speicher (110) kopiert, der eine zweite Nachricht, die angibt, dass Informationen kopiert wurden, an den Host-Teil sendet, und der die Sperrung des Disponierens aller Prozesse mit Programmcode, der sich im zweiten Speicher befindet, aufhebt.


 
12. System nach Anspruch 11, wobei die Informationen, die durch die erste Stufe in den ersten Speicher (108) gepusht werden, den Client-Teil des Bootloaders und das Betriebssystem umfassen, und die zweite Stufe die Host- und Clientprozessoren (102, 104) zum Austauschen von Nachrichten befähigt.
 
13. System nach Anspruch 12, wobei die Informationen, die durch die erste Stufe in den ersten Speicher (108) gepusht werden, mindestens einen Teil mindestens einer Anwendung umfassen.
 
14. System nach Anspruch 11, wobei der Client-Teil anfänglich ein Disponieren aller Prozesse mit Ausnahme des Leerlaufprozesses sperrt.
 
15. System nach Anspruch 11, wobei der Leerlaufprozess Informationen über eine Adresse und eine Länge des Zwischenspeicherbereichs an den Hostprozessor (102) sendet.
 
16. System nach Anspruch 11, wobei Informationen, die in den zweiten Speicher (110) geladen werden sollen, mindestens einen Tag umfassen, der eine Adresse im zweiten Speicher (110) und eine Länge der zu ladenden Informationen angibt.
 
17. System nach Anspruch 11, wobei der Zwischenspeicherbereich als Blöcke von Informationen organisiert ist, und jeder Block einen Header, der eine Länge des Blocks angibt, und eine Adresse für den Block im zweiten Speicher (110) umfasst.
 
18. System nach Anspruch 11, wobei Informationen, die in den ersten Speicher (108) gepusht werden, mindestens einen Tag umfassen, der angibt, ob die Informationen in den zweiten Speicher (110) geladen werden sollen.
 
19. System nach Anspruch 11, wobei Informationen, die in den zweiten Speicher (110) geladen werden sollen, mindestens eines von komprimiert und verschlüsselt sind.
 
20. Computerlesbares Medium, das ein Computerprogramm zum Laden von Informationen in einen Slave-Prozessor (104) in einem Mehrprozessorsystem (100) enthält, das einen Master-Prozessor (102) und den Slave-Prozessor (104) umfasst, wobei die Informationen einen Bootloader umfassen, und das Computerprogramm die folgenden Schritte ausführt:

a) Rücksetzen des Slave-Prozessors (104) und Halten des Slave-Prozessors (104) in einem rückgesetzten Zustand;

b) Pushen eines ersten Teils der Informationen in einen ersten Speicher (108), auf den durch den Master-Prozessor (102) und den Slave-Prozessor (104) zugegriffen werden kann, wobei der erste Teil der Informationen den Bootloader umfasst;

c) Booten des Slave-Prozessors (104);

d) Starten eines Betriebssystems im Slave-Prozessor (104), umfassend ein Sperren des Disponierens von Prozessen mit Programmcode, der sich in einem zweiten Speicher (110) befindet, auf den durch den Slave-Prozessor (104) zugegriffen werden kann und auf den durch den Master-Prozessor (102) nicht zugegriffen werden kann;

e) Reservieren eines Zwischenspeicherbereichs im ersten Speicher (108);

f) Senden von Informationen über einen Speicherort und eine Größe des reservierten Zwischenspeicherbereichs an den Master-Prozessor (102);

g) Laden basierend auf den gesendeten Informationen des Zwischenspeicherbereichs mit einem zweiten Teil der Informationen, der in den zweiten Speicher (110) geladen werden soll;

h) Senden einer ersten Nachricht an den Slave-Prozessor (104), die angibt, dass der Zwischenspeicherbereich geladen wurde und ob das Laden abgeschlossen ist oder mehr Informationen geladen werden sollen;

i) Kopieren von Informationen im Zwischenspeicherbereich in den zweiten Speicher (110) ;

j) Senden einer zweiten Nachricht an den Master-Prozessor (102), die angibt, dass Informationen im Zwischenspeicherbereich kopiert wurden; und

k) Aufheben der Sperrung des Disponierens von Prozessen mit Programmcode, der sich im zweiten Speicher (110) befindet.


 
21. Computerlesbares Medium nach Anspruch 20, wobei das Computerprogramm, wenn mehr Informationen geladen werden sollen, den Schritt des Wiederholens der Schritte g bis j ausführt, bis keine Informationen mehr geladen werden sollen.
 
22. Computerlesbares Medium nach Anspruch 20, wobei Schritt g) ein Voranstellen mindestens eines Tags, der eine Adresse im zweiten Speicher (110) und eine Länge der zu ladenden Informationen angibt, vor den zweiten Teil der Informationen umfasst, der in den zweiten Speicher (110) geladen werden soll.
 
23. Computerlesbares Medium nach Anspruch 20, wobei Schritt g) ein Teilen des zweiten Teils der Informationen, der in den zweiten Speicher (110) geladen werden soll, in Blöcke und Laden des Zwischenspeicherbereichs mit einem ersten Block umfasst.
 


Revendications

1. Procédé de chargement d'informations dans un processeur esclave (104) dans un système multiprocesseur (100) comprenant un processeur maître (102) et le processeur esclave, les informations comprenant un chargeur d'amorçage, comprenant les étapes de :

a) la réinitialisation du processeur esclave (104) et le maintien du processeur esclave (104) dans un état réinitialisé ;

b) la poussée d'une première partie des informations dans une première mémoire (108) qui est accessible par le processeur maître (102) et le processeur esclave (104), la première partie des informations comprenant le chargeur d'amorçage ;

c) l'amorçage du processeur esclave (104) ;

d) le démarrage d'un système d'exploitation dans le processeur esclave (104), comprenant le blocage de la programmation de processus ayant un code de programme situé dans une deuxième mémoire (110) qui est accessible par le processeur esclave (104) et inaccessible par le processeur maître (102) ;

e) la réservation d'une zone de mémorisation intermédiaire dans la première mémoire (108) ;

f) l'envoi, au processeur maître (102), d'informations relatives à un emplacement et une taille de la zone de mémorisation intermédiaire réservée ;

g) sur la base des informations envoyées, le chargement de la zone de mémorisation intermédiaire avec une deuxième partie des informations à charger dans la deuxième mémoire (110) ;

h) l'envoi d'un premier message au processeur esclave (104) indiquant que la zone de mémorisation intermédiaire a été chargée et si un chargement est terminé ou si plus d'informations doivent être chargées ;

i) la copie d'informations de la zone de mémorisation intermédiaire dans la deuxième mémoire (110) ;

j) l'envoi d'un deuxième message au processeur maître (102) indiquant que des informations dans la zone de mémorisation intermédiaire ont été copiées ; et

k) la suppression du blocage de la programmation de processus ayant un code de programme situé dans la deuxième mémoire (110).


 
2. Procédé selon la revendication 1, comprenant en outre l'étape de, s'il y a plus d'informations à charger, la répétition des étapes g-j jusqu'à ce qu'il ne reste plus d'informations à charger.
 
3. Procédé selon la revendication 1, dans lequel l'étape d) comprend la création de gestionnaires d'interruption et la création de structures de données de processus s'exécutant dans le processeur maître (102) et le processeur esclave (104).
 
4. Procédé selon la revendication 1, dans lequel la première partie des informations poussée dans la première mémoire (108) comprend en outre le système d'exploitation et au moins une portion d'au moins une application.
 
5. Procédé selon la revendication 1, dans lequel l'étape d) comprend le blocage de la programmation de tous les processus à l'exception d'un processus de veille.
 
6. Procédé selon la revendication 1, dans lequel l'étape g) comprend la précédence, avant la deuxième partie des informations à charger dans la deuxième mémoire (110), d'au moins une étiquette indiquant une adresse dans la deuxième mémoire (110) et une longueur des informations à charger.
 
7. Procédé selon la revendication 1, dans lequel l'étape g) comprend la division de la deuxième partie des informations à charger dans la deuxième mémoire (110) en blocs et le chargement de la zone de mémorisation intermédiaire avec un premier bloc.
 
8. Procédé selon la revendication 7, comprenant en outre l'étape de la répétition des étapes g-j pour chaque bloc en succession.
 
9. Procédé selon la revendication 1, dans lequel la première partie des informations poussée dans la première mémoire (108) comprend au moins une étiquette indiquant si les informations doivent être chargées dans la deuxième mémoire (110).
 
10. Procédé selon la revendication 1, dans lequel la deuxième partie des informations à charger dans la deuxième mémoire (110) est au moins l'une de compressée et de cryptée.
 
11. Système multiprocesseur (100) comprenant :

un processeur hôte (102) ;

au moins un processeur client (104) ;

une première mémoire (108) accessible par le processeur hôte et le processeur client, dans lequel la première mémoire comprend une zone de mémorisation intermédiaire ;

une deuxième mémoire (110) accessible par le processeur client et inaccessible par le processeur hôte ; et

un chargeur d'amorçage comprenant :

une partie hôte qui est chargeable dans la première mémoire, qui a un premier étage réinitialisant le processeur client (104) et le maintenant dans un état réinitialisé et poussant des informations dans la première mémoire (108), et qui a un deuxième étage initié par la partie client, chargeant la zone de mémorisation intermédiaire avec des informations à charger dans la deuxième mémoire (110) et envoyant, à la partie client, un premier message indiquant que la zone de mémorisation intermédiaire est chargée ; et

une partie client qui est chargeable dans la première mémoire (108), effectuant le démarrage d'un système d'exploitation comprenant le blocage initial de la programmation de tous les processus ayant un code de programme situé dans la deuxième mémoire (110), la copie d'informations chargées dans la zone de mémorisation intermédiaire dans la deuxième mémoire (110), l'envoi, à la partie hôte, d'un deuxième message indiquant que des informations ont été copiées, et la suppression du blocage de la programmation de tous les processus ayant un code de programme situé dans la deuxième mémoire.


 
12. Système selon la revendication 11, dans lequel les informations poussées dans la première mémoire (108) par le premier étage comprennent la partie client du chargeur d'amorçage et le système d'exploitation, et le deuxième étage permet aux processeurs hôte et client (102, 104) d'échanger des messages.
 
13. Système selon la revendication 12, dans lequel les informations poussées dans la première mémoire (108) par le premier étage comprennent au moins une portion d'au moins une application.
 
14. Système selon la revendication 11, dans lequel la partie client effectue le blocage initial de la programmation de tous les processus à l'exception du processus de veille.
 
15. Système selon la revendication 11, dans lequel le processus de veille envoie, au processeur hôte (102), des informations relatives à une adresse et une longueur de la zone de mémorisation intermédiaire.
 
16. Système selon la revendication 11, dans lequel les informations à charger dans la deuxième mémoire (110) comprennent au moins une étiquette indiquant une adresse dans la deuxième mémoire (110) et une longueur des informations à charger.
 
17. Système selon la revendication 11, dans lequel la zone de mémorisation intermédiaire est organisée en blocs d'informations, et chaque bloc comprend un en-tête indiquant une longueur du bloc et une adresse du bloc dans la deuxième mémoire (110).
 
18. Système selon la revendication 11, dans lequel des informations poussées dans la première mémoire (108) comprennent au moins une étiquette indiquant si les informations doivent être chargées dans la deuxième mémoire (110).
 
19. Système selon la revendication 11, dans lequel les informations à charger dans la deuxième mémoire (110) sont au moins l'une de compressées et de cryptées.
 
20. Support lisible par ordinateur contenant un programme informatique pour charger des informations dans un processeur esclave (104) dans un système multiprocesseur (100) comprenant un processeur maître (102) et le processeur esclave (104), dans lequel les informations comprennent un chargeur d'amorçage et le programme informatique effectue les étapes de :

a) la réinitialisation du processeur esclave (104) et le maintien du processeur esclave (104) dans un état réinitialisé ;

b) la poussée d'une première partie des informations dans une première mémoire (108) qui est accessible par le processeur maître (102) et le processeur esclave (104), la première partie des informations comprenant le chargeur d'amorçage ;

c) l'amorçage du processeur esclave (104) ;

d) le démarrage d'un système d'exploitation dans le processeur esclave (104), comprenant le blocage de la programmation de processus ayant un code de programme situé dans une deuxième mémoire (110) qui est accessible par le processeur esclave (104) et inaccessible par le processeur maître (102) ;

e) la réservation d'une zone de mémorisation intermédiaire dans la première mémoire (108) ;

f) l'envoi, au processeur maître (102), d'informations relatives à un emplacement et une taille de la zone de mémorisation intermédiaire réservée ;

g) sur la base des informations envoyées, le chargement de la zone de mémorisation intermédiaire avec une deuxième partie des informations à charger dans la deuxième mémoire (110) ;

h) l'envoi d'un premier message au processeur esclave (104) indiquant que la zone de mémorisation intermédiaire a été chargée et si un chargement est terminé ou si plus d'informations doivent être chargées ;

i) la copie d'informations de la zone de mémorisation intermédiaire dans la deuxième mémoire (110) ;

j) l'envoi d'un deuxième message au processeur maître (102) indiquant que des informations dans la zone de mémorisation intermédiaire ont été copiées ; et

k) la suppression du blocage de la programmation de processus ayant un code de programme situé dans la deuxième mémoire (110).


 
21. Support lisible par ordinateur selon la revendication 20, dans lequel le programme informatique effectue en outre l'étape de, s'il y a plus d'informations à charger, la répétition des étapes g-j jusqu'à ce qu'il ne reste plus d'informations à charger.
 
22. Support lisible par ordinateur selon la revendication 20, dans lequel l'étape g) comprend la précédence, avant la deuxième partie des informations à charger dans la deuxième mémoire (110), d'au moins une étiquette indiquant une adresse dans la deuxième mémoire (110) et une longueur des informations à charger.
 
23. Support lisible par ordinateur selon la revendication 20, dans lequel l'étape g) comprend la division de la deuxième partie des informations à charger dans la deuxième mémoire (110) en blocs et le chargement de la zone de mémorisation intermédiaire avec un premier bloc.
 




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REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description