(19)
(11)EP 2 030 032 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
23.05.2012 Bulletin 2012/21

(21)Application number: 07784466.0

(22)Date of filing:  18.06.2007
(51)Int. Cl.: 
G01R 31/3185  (2006.01)
(86)International application number:
PCT/US2007/071450
(87)International publication number:
WO 2007/149808 (27.12.2007 Gazette  2007/52)

(54)

LOGIC DEVICE AND METHOD SUPPORTING SCAN TEST

LOGIKANORDNUNG UND VERFAHREN ZUR UNTERSTÜTZUNG EINER SCAN-PRÜFUNG

DISPOSITIF LOGIQUE ET PROCÉDÉ SUPPORTANT UN TEST SÉRIE


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

(30)Priority: 22.06.2006 US 473219

(43)Date of publication of application:
04.03.2009 Bulletin 2009/10

(60)Divisional application:
11174427.2 / 2388607

(73)Proprietor: QUALCOMM Incorporated
San Diego, CA 92121 (US)

(72)Inventors:
  • SAINT-LAURENT, Martin
    Austin, Texas 78759 (US)
  • BASSETT, Paul
    San Diego California 92121-1714 (US)
  • PATEL, Prayag
    San Diego, California 92130 (US)

(74)Representative: Dunlop, Hugh Christopher et al
R.G.C. Jenkins & Co. 26 Caxton Street
London SW1H 0RJ
London SW1H 0RJ (GB)


(56)References cited: : 
US-A- 5 130 645
US-B1- 6 446 229
US-A1- 2002 087 930
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND


    I. Field



    [0001] The present disclosure generally relates to systems and methods of scan testing.

    II. Description of Related Art



    [0002] Generally, an integrated circuit may include multiple digital logic circuits. One type of digital logic circuit is a flip-flop, which is a circuit that can be switched between two states. Flip-flop circuits are a common type of sequential circuit element used to build digital systems. Accordingly, flip-flop circuits may have an impact on bath power and performance for such systems.

    [0003] Modern integrated circuits usually incorporate a variety of design-for-test (DFT) structures to enhance their inherent testability. Typically, the DFT structures are based on a scan design, where scan test data is provided to a test pin or where a plurality of externally accessible scan chains are embedded into the integrated circuit. When the scan chain is embedded, the scan chain may include one or more scan cells coupled in series, with each scan cell including a flip-flop or a latch. Typically, scan test design is used in conjunction with cult simulation and combinational ATPG (automatic test pattern generation) to generate manufacturing and diagnostic test pasterns for production test and prototype debug processes. Patent application US 2002/0087930 A1 (K. Kanba) describes a scan flip-flop circuit with a first and a second master latch and a slave latch.

    [0004] To provide DFT functionality, a circuit may have a test input, which can be accessed during a testing mode and which may be tied to a logic level during normal non-test operation. Test logic, such as a multiplexer, may be introduced to select between modes and to provide a data pattern to a logic circuit to be tested by passing the data pattern through the chain. The resulting output of the logic circuit provides an indication of faults present in the logic circuit.

    [0005] To test a logic circuit, the test logic provides test data to an input of the logic circuit Unfortunately, to provide the data to the input, the test logic, such as a multiplexer, is typically placed within the data path of the logic circuit and may unnecessarily consume power during normal non-test operation. Moreover, such test logic may introduce delays in the data path of the logic circuit, and the delays tend to reduce the performance of the logic circuit.

    [0006] Other sequential technologies, including pulsed latches, have been used to reduce delay. While pulsed latches may reduce the delay in the data path of the logic circuit, pulsed latches tend to consume more power and are typically less robust than flip-flops.

    [0007] Accordingly, it would be advantageous to provide a logic circuit with an improved test logic that reduces power loss and delays while maintaining DFT compatability.

    SUMMARY



    [0008] In a particular embodiment, a logic device is provided that includes a data input, a scan test input, a clock demultiplexer, and a master latch. The clock demultiplexer is responsive to a clock input to selectively provide a first clock output and a second clock output. The master latch is coupled to the data input and to the scan test input and includes an output. The master latch is responsive to the first clock output of the clock demultiplexer and the second clock output of the clock demultiplexer to selectively couple the data input or the scan test input to the output.

    [0009] In another particular illustrative embodiment, a method of operation of a digital logic device is provided that includes receiving a mode selection input to select between a test mode and an operating mode and selectively generating a first clock or a second clock based on the mode selection input. The method further includes routing a data input to a first state node of a storage element in response to the first clock, where the storage element includes a second state node that is inverted with respect to the first state node. Additionally, the method includes selectively isolating a scan test input from the second state node of the data latch element based on the mode selection input.

    [0010] In still another particular illustrative embodiment, a logic device includes a clock demultiplexer, a master latch, a slave latch, and a logic gate. The clock demultiplexer is coupled to a clock input and is responsive to a mode selection input to selectively generate a first clock or a second clock. The master latch is coupled to a data input and a scan test input and includes an output. The master latch is responsive to the first clock to couple the data input to the output and is responsive to the second clock to couple the scan test input to the output. The slave latch is coupled to the output of the master latch and is responsive to the clock input to selectively couple the output of the master latch to a data output. The logic gate is coupled to the data output and is responsive to the mode selection input to selectively couple the data output to a scan test output.

    [0011] One particular advantage provided by embodiments of the particular logic device is that the test logic is removed from the data path of the logic device, reducing delays in the data path. In one particular embodiment, the delays may be reduced by up to 25 percent.

    [0012] Another advantage is provided in that the logic device may consume less power than a conventional logic device with design for testability (DFT) features in the critical data path. Since the test logic is removed from the data path, the scan test logic may be gated in a power-off state during non-test operation. In one particular embodiment, the logic device may consume approximately 27 percent less power than a conventional logic device.

    [0013] Still another advantage is that the test logic and the logic device are approximately the same physical size and may occupy approximately the same amount of area on a circuit substrate as conventional devices with DFT features.

    [0014] Other aspects, advantages, and features of the present disclosure will become apparent after review of the entire application, including the following sections: Brief Description of the Drawings, Detailed Description, and the Claims.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0015] The aspects and the attendant advantages of the embodiments described herein will become more readily apparent by reference to the following detailed description when taken in conjunction with the accompanying drawings wherein:

    [0016] FIG. 1 is a block diagram illustrating a particular embodiment of a device with design for testability (DFT) compatible test logic;

    [0017] FIG. 2 is a schematic diagram illustrating a particular embodiment of a digital logic circuit with design for testability (DFT) features separated from an operational data path;

    [0018] FIG. 3 is a flow diagram of a particular embodiment of a method of operation of a digital logic device;

    [0019] FIG. 4 is a general diagram of a portable communication device incorporating a digital signal processor in which the logic device test features and method of FIGS. 1-3 may be used; and

    [0020] FIG. 5 is a general diagram of an exemplary cellular telephone incorporating a digital signal processor in which the digital logic device test features and method of FIGS. 1-3 may be used.

    DETAILED DESCRIPTION



    [0021] FIG. 1 is a block diagram of a logic device 100 with design for testability (DFT) compatible test logic. The logic device 100 includes an integrated circuit 102 that includes a master latch 104, a slave latch 106, and a clock demultiplexer 108. The integrated circuit 102 includes a clock input 110, a data input 112, a scan test input 114, and a mode selection input 116. The clock demultiplexer 108 receives the clock input 110 and a mode selection input 116. The clock demultiplexer 108 is responsive to the clock input 108 to selectively provide a first clock output 118 and a second clock output 120. The master latch 104 is coupled to the data input 112 and to the scan test input 114. The master latch 104 also includes an output 122. The master latch 104 is responsive to the first clock output 118 of the clock demultiplexer 108 and the second clock output 120 of the clock demultiplexer 108 to selectively couple the data input 112 or the scan test input 114 to the output 122. In one particular embodiment, the mode selection input 116 is coupled to the clock demultiplexer 108 to selectively activate the first clock input 118 or the second clock input 120 based on the clock input 110.

    [0022] The slave latch 106 is coupled to the output 122 of the master latch 104 to couple the output 122 of the master latch 104 to the data output 124. A logic gate 126 is coupled to the data output 124 and is responsive to an input, such as the mode selection input 116, to selectively couple the data output 124 to a scan test output 128 or to prevent a scan test output 128 from toggling. In a particular embodiment, the mode selection input 116 includes a test scan mode or an operating mode, and the output 122 of the master latch 104 is coupled through the slave latch 106 to the scan test output 128 when the mode selection input 116 indicates the test scan mode and is coupled through the slave latch 106 to the data output 124 when the mode selection input 116 indicates the operating mode.

    [0023] In a particular embodiment, the master latch 104 includes a data storage element that is selectively coupled to the data input 112 and to the scan test input 114. The data storage element may include a pair of cross-coupled inverters. In one particular embodiment, the master latch 104 may include a memory element and test scan circuitry to receive the scan test input 114 and to selectively couple the scan test input 114 to the memory element. In another particular embodiment, the master latch 104 includes a memory element and a transmission gate to receive the data input 112 and to selectively couple the data input 112 to the memory element. In still another embodiment, the master latch 104 includes a memory element including a pair of cross-coupled inverters and a write circuit, such as a transmission gate.

    [0024] In operation, the clock demultiplexer 108 receives the clock input 110 and generates the first clock output 118 or the second clock output 120 according, to the mode selection input 116. In one particular embodiment, when the first mode selection is received via the mode selection input 116, the clock demultiplexer 108 produces the first clock output 118, triggering the master latch 104 to provide data from the data input 112 to the output 122. The slave latch 106 provides data on the output 122 to the output 124 responsive to the clock input 110. In another particular embodiment, when the second mode selection is received via the mode selection input, the clock demultiplexer 108 produces the second clock output 120, triggering the master latch 104 to provide scan test data from the scan test input 114 to the output 122. The slave latch 106 provides data on the output 122 to the output 124 responsive to the clock input 110. The logic gate 126 provides the scan test data from the output 124 to the scan test output 128 responsive to the mode selection input 116. In one particular embodiment, when the second mode selection is received via the mode selection input 116, the scan test output 128 is related to the scan test input 114.

    [0025] In one particular embodiment, a time delay from the data input 112 to the data output 124 during a first mode of operation is less than a time delay from the scan test input 114 to the scan test output 128 during a second mode of operation.

    [0026] In one particular embodiment, the master latch 104 includes scan test circuitry that is gated in a power off state when the logic device 100 is in a non-test mode of operation. The scan test circuitry does not introduce a delay to a data path responsive to the data input 112.

    [0027] FIG. 2 is a schematic diagram illustrating a particular illustrative embodiment of a logic circuit 200 with design for testability (DFT) features separated from an operational data path. The logic circuit 200 includes clock demultiplexing logic 202, a master latch 204, a slave latch 206, and scan test output logic 284. The clock demultiplexing logic 202 includes a shift input 208, a clock input 210, and NOR gates 212 and 240. The NOR gate 212 inverts the shift input 208. The NOR gates 212 and 240 operate to demultiplex the clock input 210 responsive to the shift input 208: When the shift input 208 is at a logic low level, the NOR 212 provides a zero output, while the NOR gate 240 proves a clock signal that is inverted relative to the clock input 210. Thus, the NOR gates 212 and 240 provide clock demultiplexing logic 202 that converts a clock input 210 into a first clock signal at output 242 and a second clock signal at node 220.

    [0028] The inverter 216 inverts the logic level at node 220 and provides an inverted output to node 224. The tri-state inverter 218 includes an input coupled to a scan test input 209, an input coupled to node 220, and an inverted input coupled to the node 224. The shift input 208 controls the tri-state inverter 218 to selectively couple the scan test input 209 to a second state node 228 of the master latch 204. When the shift input 208 is at a logic low, the tri-state inverter 218 is deactivated, thereby isolating the second state node 228 from the scan test input 209. When the shift input 208 is at a logic high level, then the NOR gate 212 receives the shift input 208 as a logic low signal, since the shift input 208 of the NOR gate 212 is inverted, and the output of the NOR gate 212 at node 220 is an inverted version of the clock input 210.

    [0029] The NOR gate 240 includes the shift input 208 and the clock input 210. When the shift input 208 is at a logic low, the NOR gate 240 outputs an inverted version of the clock input 210 at output 242. The output 242 is coupled to an inverter 244, which is coupled to a node 246.

    [0030] The master latch 204 includes a data input 250, a scan test input 209, a tri-state inverter 230, a tri-state inverter 236, inverters 252 and 256, and a transmission gate 254. The scan test input 209 is coupled to the tri-state inverter 218 and to node 228. The tri-state inverter 230 includes a scan test clock input 232 coupled to the node 224, an inverted input 234 to receive an activation signal (i0), an input 237 coupled to a first state node 238, and an output coupled to the second state node 228. The tri-state inverter 236 includes an input 235 that is coupled to the second state node 228, a clock input 239 that is coupled to the node 246 to receive an activation signal (i1), and an output coupled to the first state node 238. It should be understood that the arrangement of the tri-state inverters 230 and 236 may be referred to as a storage element or as a cross-coupled inverter, which can be controlled by the logic level of the shift input 208. The master latch 204 also includes the inverter 252 to receive the data input 250 and to provide an inverted version of the data input 250 to the transmission gate 254. The transmission gate 254 may be a write circuit that is controlled by the clock input 210, such as a tristate inverter. The transmission gate 254 includes an input to receive the inverted version of the data input 250, inputs 251 and 257 to provide inverted versions of the clock input to the transmission gate 254, and an output coupled to the first state node 238 via node 258. In general, the storage element of the tri-state inverters 230 and 236 and the transmission gate 254 form a latch means or latch element. It should be apparent to someone skilled in the art that the number of logic gates between the clock and transmission gate 254 can be varied to change the timing characteristics of the circuit. The number of logic gates on the clock path of tristate inverter 226 can also be varied for the same reason.

    [0031] The slave latch 206 is coupled to the first state node 238 via node 258 and via an inverter 260. The slave latch 206 includes an input 262 that is coupled to an output of the inverter 260. The slave latch 206 also includes a transmission gate 264, inverters 266, 274, and 280, and a tri-state inverter 282. The inverter 266 includes a clock input 210 and provides an output to a node 270. The transmission gate 264 includes an input coupled to the output 262 of the inverter 260, an input 268 coupled to the clock input 210, and an input 267 coupled to the node 270. The transmission gate 264 includes an output coupled to node 272 and to a data output 276 via inverter 274. The inverter 280 includes an input coupled to the node 272 and an output coupled to the node 281. The inverter 282 includes an input coupled to the node 281, a control input coupled to the node 270, and an output coupled to the node 272. The slave latch 206 latches the data from the node 258 to the output 276 of the slave latch 206 on each clock cycle.

    [0032] The NAND gate 284 includes an input coupled to the shift input 208, an input coupled to the node 281, and a scan test output 286. When the shift input 208 is at a logic low level, the output of the NAND gate 284 is held at a logic high level. When the shift input 208 is at a logic low level, the NAND gate 284 provides an inverted version of the scan test input 209 to the scan test output 286. Thus, when the scan test mode of operation is selected, such as by placing a logic high signal on the shift input 208, the data from the output 276 is gated onto the scan test output 286 by the NAND gate 284. The same gating function can also be implemented using a different type of logic gate, such as a NOR gate.

    [0033] In one particular embodiment, when in a functional or operating mode, the tri-state inverter 218 that is coupled to the scan test input 209 is disabled when the shift input 208 receives a shift value of zero (or a logic low value, such as a level that is below a threshold voltage level, for example). The output of the NOR gate 240 is inverted by inverter 244 and inverted again at the control inputs 251 and 257 of the transmission gate 254, which is enabled to pass data from the data input 250 to the first state node 258. During an operating mode, the scan circuitry may be gated off to conserve power. The data input 250 is coupled to the data output 276 via the transmission gates 254 and 264 and via inverters 252, 258 and 274 to provide a data output signal on the data output 276 that is related to the data input signal at the data input 250. The scan test logic is not part of this data path.

    [0034] In a test mode, the shift value is "1" (a logic high, such as a level that is above a threshold voltage level, for example) at the shift input 208, the tri-state inverter 218 is enabled and the scan test input 209 is connected to the second state node 228 via the tri-state inverter 218. Concurrently, the transmission gate 254 is disabled to disconnect the data input 250 from the first state node 258. The scan circuitry 204 becomes the master latch that is coupled to the first state node 258, which provides the input to the slave latch 206. In the test mode, the scan test input 209 is coupled to the scan output 286 via the tri-state inverter 218, the node 228, the cross-coupled inverters 230 and 236, the first state node 258, the inverter 260, the transmission gate 264, the inverter 280, the tri-state inverter 282, the node 281, and the NAND gate 284.

    [0035] The circuit 200 performs like a multiplexer followed by a flip-flop. However, the scan test circuitry is removed from the data path logic. Instead, the multiplexing is performed using the clock input 210 and the shift input 208 in the clock demultiplexing logic 202 to produce two clocks to the master latch 204 to selectively couple either the scan test input 209 or the data input 250 to the slave latch 206. Additionally, the scan circuitry does not slow down the data flow through the data path logic.

    [0036] In general, a microprocessor that is designed for mobile applications may include flip-flops, which may account for approximately 29% of the total dynamic power consumption of the microprocessor. A flip-flop circuit that incorporates the scan test logic described in FIGS. 1 and 2, for example, may be approximately 25% faster and may require 27% less power than conventional flip-flops, while occupying the same physical area on the chip. The flip-flop, such as the inverters 280 and 282 in the slave latch 206 and the inverters 234 and 236 of the master latch 204 has its scan logic removed from the data path during normal operation. Additionally, since flip-flops are widely utilized in digital systems, the circuit 200 maintains design for testability (DFT) compatible test logic while removing the DFT scan circuitry from the data path logic to reduce delays relative to conventional scan test logic disposed within the data path. It should be understood that the term "data path logic" as used herein refers to the data path utilized during operating mode, as opposed to the scan test data path utilized during a test mode of operation.

    [0037] FIG. 3 is an illustrative block diagram of a particular embodiment of a method of operation of a logic device. A mode selection signal is received (block 300). If the mode selection signal is not related to a test mode (block 302), a first clock output is generated from a clock input (block 304). A data input is routed to a first state node of a storage element, where the storage element includes a second state node that is inverted with respect to the first state node (block 306). In the operating mode, a scan test input is isolated from the second state node (block 308).

    [0038] If the mode selection signal is related to a test mode (block 302), a second clock output is generated from a clock input (block 310). A scan test input is routed to a second state node of the storage element (block 312). In the scan test mode, the data input is isolated from the first state node (block 314). The output may be generated according to the routed input (block 316) (i.e. the data output in the normal operating mode or the scan test output during the scan test mode).

    [0039] In one particular embodiment, a control input is received to select the test mode of operation. In one embodiment, the test mode of operation is a scan test mode. In one particular embodiment, the scan test input is routed by enabling a tri-state inverter or a transmission gate to couple the scan test input to the second state node, where the tri-state inverter or transmission gate may include a data input coupled to the scan test input, a control input coupled to a control terminal, and an output coupled to the second state node. In one embodiment, the data input may be isolated from the first state node by disabling a second transmission gate or tri-state element. The second transmission gate or tri-state element may include a data input terminal coupled to the data input, a first control input and a second control input coupled to the control terminal, and an output coupled to the first state node, where the control terminal is inverted with respect to the first control input and the second control input.

    [0040] In another particular embodiment, the data input is routed to the first state node by enabling a transmission gate to couple the data input to the first state node. In yet another particular embodiment, the scan test input may be isolated by disabling an inverter, where the inverter includes a data input coupled to the scan test input, includes a control input coupled to a control terminal, and includes an output coupled to the second state node.

    [0041] In one particular embodiment, the scan test input is routed by enabling an inverter (such as the tri-state inverter 218 in FIG. 2) to couple the scan test input to the second state node. The inverter may couple the scan test input to the second state node during a test mode of operation and may isolate the second state node from the scan test input during an operating (non-test) mode. A transmission gate may couple the data input to the first state node during an operating mode and may isolate the data input from the first state node during a test mode.

    [0042] In another particular embodiment, the data input is routed to the first state node by enabling a transmission gate (such as the transmission gate 254) to couple the data input to the first state node. The transmission gate may include a data input terminal coupled to the data input, a first control input and a second control input coupled to the control terminal, and an output coupled to the first state node (such as input 253, control inputs 251 and 257, and the output coupled to the first state node 258 in FIG. 2). It should be apparent to anyone skilled in the art that input inverter 252 of Fig. 2 could be replaced by another logic gate, or completely removed. It should also be apparent that tristate inverter 234 or tristate inverter 236 can be replaced by another tristate logic gate to implement an asynchronous set or reset function for the master latch. Similarly, an asynchronous set or reset function can be implemented in the slave latch by replacing inverter 280 or tristate inverter 282 by another logic gate, such as a NAND or NORpwd, or tristate logic gate, respectively.

    [0043] In another particular embodiment, the scan test input may be isolated by disabling an inverter (such as the tri-state inverter 218 in FIG. 2). The inverter may include a data input coupled to the scan test input, a control input coupled to a control terminal, and an output coupled to the second state node.

    [0044] FIG. 4 illustrates an exemplary, non-limiting embodiment of a portable communication device that is generally designated 400. As illustrated in FIG. 4, the portable communication device includes an on-chip system 422 that includes a digital signal processor 410. In a particular embodiment, the digital signal processor 410 may include scan circuitry 411 (or scan test circuitry) as described with respect to FIGS. 1-3. FIG. 4 also shows a display controller 426 that is coupled to the digital signal processor 410 and to a display 428. Moreover, an input device 430 is coupled to the digital signal processor 410. As shown, a memory 432 is coupled to the digital signal processor 410. Additionally, a coder/decoder (CODEC) 434 can be coupled to the digital signal processor 410. A speaker 436 and a microphone 438 can be coupled to the CODEC 434.

    [0045] FIG. 4 also indicates that a wireless controller 440 can be coupled to the digital signal processor 410 and a wireless antenna 442. In a particular embodiment, a power supply 444 is coupled to the on-chip system 422. Moreover, in a particular embodiment, as illustrated in FIG. 4, the display 428, the input device 430, the speaker 436. the microphone 438, the wireless antenna 442, and the power supply 444 are external to the on-chip system 422. However, each is coupled to a component of the on-chip system 422.

    [0046] It should be understood that while the scan circuitry 411 is shown only within the digital signal processor 410, the scan circuitry 411 may be provided in other components, including the display controller 426, the wireless controller 440, the CODEC 434, or any other component that includes a flip-flop for which design for testability (DFT) compatibility is desired. It should be understood that at least one scan test pin and at least one mode selection pin may be provided in each such component to receive scan data and to select between an operating mode and a test mode.

    [0047] Referring to FIG. 5, an exemplary, non-limiting embodiment of a cellular telephone is shown and is generally designated 500. As shown, the cellular telephone 500 includes an on-chip system 522 that includes a digital baseband processor 524 and an analog baseband processor 526 that are coupled together. The digital baseband processor 524 may include scan circuitry 511, as described with respect to FIGS. 1-3. The analog baseband processor 526 may also include scan circuitry 527, as described with respect to FIGS. 1-3. As illustrated in FIG. 5, a display controller 528 and a touchscreen controller 530 are coupled to the digital baseband processor 524. In turn, a touchscreen display 532 external to the on-chip system 522 is coupled to the display controller 528 and the touchscreen controller 530.

    [0048] FIG. 5 further indicates that a video encoder 534, e.g., a phase alternating line (PAL) encoder, a sequential couleur a memoire (SECAM) encoder, or a national television system(s) committee (NTSC) encoder, is coupled to the digital baseband processor 524. Further, a video amplifier 536 is coupled to the video encoder 534 and the touchscreen display 532. Also, a video port 538 is coupled to the video amplifier 536. As depicted in FIG. 5, a universal serial bus (USB) controller 540 is coupled to the digital baseband processor 524. Also, a USB port 542 is coupled to the USB controller 540. A memory 544 and a subscriber identity module (SIM) card 546 can also be coupled to the digital baseband processor 524. Further, as shown in FIG. 5, a digital camera 548 can be coupled to the digital baseband processor 524. In an exemplary embodiment, the digital camera 548 is a charge-coupled device (CCD) camera or a complementary metal-oxide semiconductor (CMOS) camera.

    [0049] As further illustrated in FIG. 5, a stereo audio CODEC 550 can be coupled to the analog baseband processor 526. Moreover, an audio amplifier 552 can coupled to the stereo audio CODEC 550. In an exemplary embodiment, a first stereo speaker 554 and a second stereo speaker 556 are coupled to the audio amplifier 552. FIG. 5 shows that a microphone amplifier 558 can be also coupled to the stereo audio CODEC 550. Additionally, a microphone 560 can be coupled to the microphone amplifier 558. In a particular embodiment, a frequency modulation (FM) radio tuner 562 can be coupled to the stereo audio CODEC 550. Also, an FM antenna 564 is coupled to the FM radio tuner 562. Further, stereo headphones 566 can be coupled to the stereo audio CODEC 550.

    [0050] FIG. 5 further indicates that a radio frequency (RF) transceiver 568 can be coupled to the analog baseband processor 526. An RF switch 570 can be coupled to the RF transceiver 568 and to an RF antenna 572. As shown in FIG. 5, a keypad 574 can be coupled to the analog baseband processor 526. Also, a mono headset with a microphone 576 can be coupled to the analog baseband processor 526. Further, a vibrator device 578 can be coupled to the analog baseband processor 526. FIG. 5 also shows that a power supply 580 can be coupled to the on-chip system 522. In a particular embodiment, the power supply 580 is a direct current (DC) power supply that provides power to the various components of the cellular telephone 500 that require power. Further, in a particular embodiment, the power supply is a rechargeable DC battery or a DC power supply that is derived from an alternating current (AC) to DC transformer that is connected to an AC power source.

    [0051] In a particular embodiment, as depicted in FIG. 5, the touchscreen display 532, the video port 538, the USB port 542, the camera 548, the first stereo speaker 554, the second stereo speaker 556, the microphone 560, the FM antenna 564, the stereo headphones 566, the RF switch 570, the RF antenna 572, the keypad 574, the mono headset 576, the vibrator device 578, and the power supply 580 are external to the on-chip system 522.

    [0052] It should be understood that while the scan circuitry 511 and 527 is shown only within the digital signal processor 524 and within the analog baseband processor 526, scan circuitry, such as that described with respect to FIGS. 1-3, may be provided in other components, including the display controller 528, the touchscreen controller 530, the PAL/SECAM/NTSC encoder 534, or any other component that includes a flip-flop for which design for testability (DFT) compatibility is desired. It should be understood that at least one scan test pin and at least one mode selection pin may be provided in each such component to receive scan data and to select between an operating mode and a test mode.

    [0053] Those of skill would further appreciate that the various illustrative logical blocks, configurations, modules, circuits, and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, configurations, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

    [0054] The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, PROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a computing device or a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a computing device or user terminal.

    [0055] The previous description of the disclosed embodiment is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features as defined by the following claims.


    Claims

    1. A logic device comprising:

    a data input (112);

    a scan test input (114);

    a clock demultiplexer (108) responsive to a clock input (110) to selectively provide a first clock output (118) and a second clock output (120);

    a master latch (104) coupled to the data input (112) and to the scan test input (114), the master latch including an output (122), the master latch responsive to the first clock output (118) of the clock demultiplexer (108) and the second clock output (120) of the clock demultiplexer (108) to selectively couple the data input (112) or the scan test input (114) to the output (122); and

    a slave latch (106) coupled to the output (122) of the master latch to couple the output of the master latch to a data output (124) responsive to the clock input (110).


     
    2. The logic device of claim 1, further comprising:

    a logic gate (128) coupled to the data output (124) and responsive to an input to couple the data output (124) to a scan test output (128).


     
    3. The logic device of claim 2, wherein the input comprises a mode selection input (116).
     
    4. The logic device of claim 1, wherein the master latch comprises:

    a data storage element coupled to the data input (122) and to the scan test input (114).


     
    5. The logic device of claim 4, wherein the data storage element comprises:

    a pair of inverters or tri-state inverters that are arranged in a cross-coupled configuration, the pair of inverters including a first node and a second node, wherein the second node is inverted with respect to the first node; and

    a transmission gate or tri-state element coupled to the first node and responsive to the first clock input (118) to couple the data input (112) to the first node.


     
    6. The logic device of claim 4, wherein the master latch further comprises:

    a scan test circuit (411) coupled to the scan test input (114) and responsive to the second clock input (120) to connect the scan test input (114) to the data storage element.


     
    7. The logic device of claim 1 or 3, further comprising:

    a mode selection input (116) coupled to the clock demultiplexer (108) to selectively activate the first clock input (118) or the second clock input (120).


     
    8. The logic device of claim 7 wherein the mode selection input includes one of a test scan mode or an operating mode, and wherein the output (122) of the master latch is coupled to the scan test output (128) when the mode selection input is the test scan mode and is coupled to the data output (124) when the mode selection input is the operating mode.
     
    9. The logic device of claim 7 wherein the master latch comprises:

    a memory element (432); and

    test scan circuitry (411) to receive the scan test input and responsive to the mode selection input (116) to couple the scan test input (114) to the memory element.


     
    10. The logic device of claim 7, wherein the master latch comprises:

    a memory element (432); and

    a transmission gate to receive the data input and responsive to the mode selection input (116) to couple, the data input (112) to the memory element.


     
    11. A method of operation of a digital logic device, the method comprising:

    receiving (300) a mode selection input to select between a test mode and an operating mode;

    selectively generating a first clock (304) or a second clock (310) based on the mode selection input and a clock input;

    routing (306) a data input (250) to a first state node (238) of a storage element (230; 236) in response to the first clock (232; 239), the storage element having a second state node (228) that is inverted with respect to the first state node;

    selectively isolating (308) a scan test input (209) from the second state node (228) of the data latch element based on the mode selection input; and

    when in the test mode, routing the scan test input (209) via the second state node (228) to a logic gate (284), the logic gate responsive to the clock input.


     
    12. The method of claim 11, further comprising:

    in the test mode of operation, isolating (314) the data input from the first state node in response to the second clock.


     
    13. The logic device of claim 1, further comprising:

    a transmission gate (254) to receive the data input (112; 250), the transmission gate responsive to the first clock output (118; 210) to couple the data input to a first state node (238);
    scan test circuitry (411) to receive the scan test input (114, 209), the scan test circuitry responsive to the second clock output (120, 251) to couple the scan test input to a second state node (228); and
    a logic gate (126, 284) to receive the scan test input from the second state node, the logic gate responsive to the clock input (110).


     
    14. The logic device of claim 1. wherein the clock demultiplexer (108, 202) is further responsive to a mode selection signal (116, 208), and comprises a first NOR gate (212) and a second NOR gate (240), and wherein when the mode selection signal (116, 208) is at a logic low level, the first NOR gate (212) is operable to provide a logical zero output (22) and the second NOR gate (240) is operable to provide a clock signal (242) that is inverted relative to the clock input (110, 210).
     
    15. The logic device of claim 1 or claim 14, wherein when the data input (112, 250) is coupled to the master latch output (122) the scan test input is electrically isolated from the master latch output.
     
    16. The logic device of any of claims 1, 14 or 15, wherein the data input (112, 250) is coupled to a first input (237) of a pair of cross-coupled inverters (230, 236) and wherein the scan test input (209) is coupled to a second input (228) of the pair of cross-coupled inverters (230, 236).
     


    Ansprüche

    1. Eine Logikvorrichtung, die Folgendes aufweist:

    einen Dateneingang (112);

    einen Scan-Test-Eingang (114);

    einen Takt-Demultiplexer (108), der auf eine Takteingabe (110) anspricht, um selektiv eine erste Taktausgabe (118) und eine zweite Taktausgabe (120) vorzusehen;

    einen Master-Latch bzw. ein Master-Verriegelungselement (104), der an den Dateneingang (112) und an den Scan-Test-Eingang (114) gekoppelt ist,

    wobei der Master-Latch einen Ausgang (122) aufweist, wobei der Master-Latch auf die erste Taktausgabe (118) des Takt-Demultiplexers (108) und die zweite Taktausgabe (120) des Takt-Demultiplexers (108) anspricht, um selektiv den Dateneingang (112) oder den Scan-Test-Eingang (114) an den Ausgang (122) zu koppeln; und

    einen Slave-Latch bzw. ein Slave-Verriegelungselement (106), der an den Ausgang (122) vom Master-Latch gekoppelt ist, um den Ausgang des Master-Latches mit einem Datenausgang (124) ansprechend auf die Takteingabe (110) zu koppeln.


     
    2. Logikvorrichtung nach Anspruch 1, die weiter Folgendes aufweist:

    ein Logic Gate bzw. Logikgatter (128), das an den Datenausgang (124) gekoppelt ist und auf eine Eingabe anspricht, um den Datenausgang (124) mit einem Scan-Test-Ausgang (128) zu koppeln.


     
    3. Logikvorrichtung nach Anspruch 2, wobei die Eingabe eine Modusauswahleingabe (116) aufweist.
     
    4. Logikvorrichtung nach Anspruch 1, wobei der Master-Latch Folgendes aufweist:

    ein Datenspeicherelement, das an den Dateneingang (122) gekoppelt ist und

    an den Scan-Test-Eingang (114).


     
    5. Logikvorrichtung nach Anspruch 4, wobei das Datenspeicherelement Folgendes aufweist:

    ein Paar von Invertierern oder Invertierern mit drei Zuständen, die in einer kreuzgekoppelten Konfiguration angeordnet sind, wobei das Paar von Invertierern einen ersten Node bzw. Knoten und einen zweiten Node beinhaltet, wobei der zweite Node in Bezug auf den ersten Node invertiert ist; und

    ein Transmission Gate bzw. Sendegatter oder ein Element mit drei Zuständen, das an den ersten Node gekoppelt ist und auf die erste Takteingabe (118) anspricht, um den Dateneingang (112) an den ersten Node zu koppeln.


     
    6. Logikvorrichtung nach Anspruch 4, wobei der Master-Latch weiter Folgendes aufweist:

    einen Scan-Test-Schaltkreis (411), der an den Scan-Test-Eingang (114) gekoppelt ist und auf die zweite Takteingabe (120) anspricht, um den Scan-Test-Eingang (114) mit dem Datenspeicherelement zu verbinden.


     
    7. Logikvorrichtung nach Anspruch 1 oder 3, die weiter Folgendes aufweist:

    eine Modusauswahleingang (116), der an den Takt-Demultiplexer (108) gekoppelt ist, um selektiv die erste Takteingabe (118) oder die zweiten Takteingabe (120) zu aktivieren.


     
    8. Logikvorrichtung nach Anspruch 7, wobei die Modusauswahleingabe einen Test-Scan-Modus oder einen Betriebsmodus beinhaltet, und wobei der Ausgang (122) des Master-Latches mit dem Test-Scan-Ausgang (128) gekoppelt ist, wenn die Modusauswahleingabe der Test-Scan-Modus ist und mit dem Datenausgang (124) gekoppelt ist, wenn die Modusauswahleingabe der Betriebsmodus ist.
     
    9. Logikvorrichtung nach Anspruch 7, wobei der Master-Latch Folgendes aufweist:

    ein Speicherelement (432); und

    eine Test-Scan-Schaltung (411), um die Scan-Test-Eingabe zu empfangen und ansprechend auf die Modusauswahleingabe (116) den Scan-Test-Eingang (114) mit dem Speicherelement zu koppeln.


     
    10. Logikvorrichtung nach Anspruch 7, wobei der Master-Latch Folgendes aufweist:

    ein Speicherelement (432); und

    ein Sendegatter, um die Dateneingabe zu empfangen und ansprechend auf die Modusauswahleingabe (116) den Dateneingang (112) mit dem Speicherelement zu koppeln.


     
    11. Ein Verfahren zum Betrieb einer digitalen Logikvorrichtung, wobei das Verfahren Folgendes aufweist:

    Empfangen (300) einer Modusauswahleingabe, um zwischen einem TestModus und einem Betriebsmodus auszuwählen;

    selektives Generieren eines ersten Taktes (304) oder eine zweiten Taktes (310) basierend auf der Modusauswahleingabe und einer Takteingabe;

    Routing bzw. Weiterleiten (306) einer Dateneingabe (250) an einen ersten Zustandsnode (238) eines Speicherelements (230; 236) ansprechend auf einen ersten Takt (232; 239), wobei das Speicherelement einen zweiten Zustandsnode (228) hat, der in Bezug auf den ersten Zustandsnode invertiert ist;

    selektives Isolieren (308) eines Scan-Test-Eingangs (209) von dem zweiten Zustandsnode (228) des Daten-Latch-Elementes basierend auf der Modusauswahleingabe; und

    wenn im Testmodus, Weiterleiten der Scan-Test-Eingabe (209) über den zweiten Zustandsnode (228) an ein Logikgatter (284), wobei das Logikgatter auf die Takteingabe anspricht.


     
    12. Verfahren nach Anspruch 11, das weiter Folgendes aufweist:

    im Testbetriebsmodus, Isolieren (314) des Dateneingangs von dem ersten Zustandsnode ansprechend auf den zweiten Takt.


     
    13. Logikvorrichtung nach Anspruch 1, die weiter Folgendes aufweist:

    ein Sendegatter (254) um die Dateneingabe (112; 250) zu empfangen, wobei das Sendegatter auf die erste Takteingabe (118, 210) anspricht, um den Dateneingang mit dem ersten Zustandsnode (238) zu koppeln;

    eine Scan-Test-Schaltung (411), um die Scan-Test-Eingabe (114, 209) zu empfangen, wobei die Scan-Test-Schaltung auf die zweite Takteingabe (120, 251) anspricht, um die Scan-Test-Eingabe mit einem zweiten Zustandsnode (228) zu koppeln; und

    ein Logikgatter (126, 284), um die Scan-Test-Eingabe von dem zweiten Zustandsnode zu empfangen, wobei das Logikgatter auf die Takteingabe (110) anspricht.


     
    14. Logikvorrichtung nach Anspruch 1, wobei der Takt-Demultiplexer (108, 202) weiter auf ein Modusauswahlsignal (116, 208) anspricht, und ein erstes NOR-Gatter (212) und ein zweites NOR-Gatter (240) aufweist, und wobei, wenn das Modusauswahlsignal (116, 208) auf einem logischen Tiefpegel ist, das erste NOR-Gatter (212) betreibbar ist, um eine logische Null-Ausgabe (22) vorzusehen und das zweite NOR-Gatter (240) betreibbar ist, um ein Taktsignal (242) vorzusehen, das relativ zur Takteingabe (110, 210) invertiert ist.
     
    15. Logikvorrichtung nach Anspruch 1 oder Anspruch 14, wobei, wenn der Dateneingang (112, 250) an den Master-Latch-Ausgang (122) gekoppelt ist, der Scan-Test-Eingang vom Master-Latch-Ausgang elektrisch isoliert ist.
     
    16. Logikvorrichtung nach einem der Ansprüche 1, 14 oder 15, wobei der Dateneingang (112, 250) an den ersten Eingang (237) eines Paares von
    kreuzgekoppelten Invertierern (230, 236) gekoppelt ist und wobei der Scan-Test-Eingang (209) an einen zweiten Eingang (228) des Paares von kreuzgekoppelten Invertierern (230, 236) gekoppelt ist.
     


    Revendications

    1. Dispositif logique comprenant :

    une entrée de données (112) ;

    une entrée de test série (114) ;

    un démultiplexeur d'horloge (108) sensible à une entrée d'horloge (110) pour fournir sélectivement une première sortie d'horloge (118) et une seconde sortie d'horloge (120) ;

    un verrou maître (104) couplé à l'entrée de données (112) et à l'entrée de test série (114), le verrou maître comprenant une sortie (122), le verrou maître étant sensible à la première sortie d'horloge (118) du démultiplexeur d'horloge (108) et à la seconde sortie d'horloge (120) du démultiplexeur d'horloge (108) pour coupler sélectivement l'entrée de données (112) ou l'entrée de test série (114) à la sortie (122) ; et

    un verrou esclave (106) couplé à la sortie (122) du verrou maître pour coupler la sortie du verrou maître à une sortie de données (124) en réponse à l'entrée d'horloge (110).


     
    2. Dispositif logique selon la revendication 1, comprenant en outre :

    une porte logique (126) couplée à la sortie de données (124) et sensible à une entrée pour coupler la sortie de données (124) à une sortie de test série (128).


     
    3. Dispositif logique selon la revendication 2, dans lequel l'entrée comprend une entrée de sélection de mode (116).
     
    4. Dispositif logique selon la revendication 1, dans lequel le verrou maître comprend :

    un élément de stockage de données couplé à l'entrée de données (112) et à l'entrée de test série (114).


     
    5. Dispositif logique selon la revendication 4, dans lequel l'élément de stockage de données comprend :

    une paire d'inverseurs ou d'inverseurs à trois états qui sont agencés dans une configuration de rétrocouplage, la paire d'inverseurs comprenant un premier noeud et un second noeud, le second noeud étant inversé par rapport au premier noeud ; et

    une porte de transfert ou un élément à trois états couplé au premier noeud et sensible à la première sortie d'horloge (118) pour coupler l'entrée de données (112) au premier noeud.


     
    6. Dispositif logique selon la revendication 4, dans lequel le verrou maître comprend en outre :

    un circuit de test série (411) couplé à l'entrée de test série (114) et sensible à la seconde sortie d'horloge (120) pour connecter l'entrée de test série (114) à l'élément de stockage de données.


     
    7. Dispositif logique selon la revendication 1 ou 3, comprenant en outre :

    une entrée de sélection de mode (116) couplée au démultiplexeur d'horloge (108) pour activer sélectivement la première sortie d'horloge (118) ou la seconde sortie d'horloge (120).


     
    8. Dispositif logique selon la revendication 7, dans lequel l'entrée de sélection de mode comprend un mode parmi un mode de test série et un mode fonctionnel, et dans lequel la sortie (122) du verrou maître est couplée à la sortie de test série (128) quand l'entrée de sélection de mode est le mode de test série et est couplée à la sortie de données (124) quand l'entrée de sélection de mode est le mode fonctionnel.
     
    9. Dispositif logique selon la revendication 7, dans lequel le verrou maître comprend :

    un élément de mémoire (432) ; et

    un circuit de test série (411) pour recevoir l'entrée de test série et sensible à l'entrée de sélection de mode (116) pour coupler l'entrée de test série (114) à l'élément de mémoire.


     
    10. Dispositif logique selon la revendication 7, dans lequel le verrou maître comprend :

    un élément de mémoire (432) ; et

    une porte de transfert pour recevoir l'entrée de données et sensible à l'entrée de sélection de mode (116) pour coupler l'entrée de données (112) à l'élément de mémoire.


     
    11. Procédé de fonctionnement d'un dispositif logique numérique, le procédé consistant à :

    recevoir (300) une entrée de sélection de mode pour effectuer une sélection entre un mode de test et un mode fonctionnel ;

    générer sélectivement une première horloge (304) ou une seconde horloge (310) sur la base de l'entrée de sélection de mode et d'une entrée d'horloge ;

    router (306) une entrée de données (250) vers un premier noeud d'état (238) d'un élément de stockage (230 ; 236) en réponse à la première horloge (232 ; 239), l'élément de stockage comprenant un second noeud d'état (228) qui est inversé par rapport au premier noeud d'état ;

    isoler sélectivement (308) une entrée de test série (209) du second noeud d'état (228) de l'élément de verrouillage de données sur la base de l'entrée de sélection de mode ; et

    dans le mode de test, router l'entrée de test série (209) par l'intermédiaire du second noeud d'état (228) vers une porte logique (284), la porte logique étant sensible à l'entrée d'horloge.


     
    12. Procédé selon la revendication 11, consistant en outre à :

    dans le mode de fonctionnement de test, isoler (314) l'entrée de données du premier noeud d'état en réponse à la seconde horloge.


     
    13. Dispositif logique selon la revendication 1, comprenant en outre :

    une porte de transfert (254) pour recevoir l'entrée de données (112, 250), la porte de transfert étant sensible à la première sortie d'horloge (118, 210) pour coupler l'entrée de données à un premier noeud d'état (238) ;

    un circuit de test série (411) pour recevoir l'entrée de test série (114, 209), le circuit de test série étant sensible à la seconde sortie d'horloge (120, 251) pour coupler l'entrée de test série à un second noeud d'état (228) ; et

    une porte logique (126, 284) pour recevoir l'entrée de test série provenant du second noeud d'état, la porte logique étant sensible à l'entrée d'horloge (110).


     
    14. Dispositif logique selon la revendication 1, dans lequel le démultiplexeur d'horloge (108, 202) est en outre sensible à un signal de sélection de mode (116, 208) et comprend une première porte NI (212) et une seconde porte NI (240), et dans lequel quand le signal de sélection de mode (116, 208) est à un niveau logique bas, la première porte NI (212) sert à délivrer une sortie au zéro logique (22) et la seconde porte NI (240) sert à délivrer un signal d'horloge (242) qui est inversé par rapport à l'entrée d'horloge (110, 210).
     
    15. Dispositif logique selon la revendication 1 ou la revendication 14, dans lequel quand l'entrée de données (112, 250) est couplée à la sortie (122) du verrou maître, l'entrée de test série est électriquement isolée de la sortie du verrou maître.
     
    16. Dispositif logique selon l'une quelconque des revendications 1, 14 et 15, dans lequel l'entrée de données (112, 250) est couplée à une première entrée (237) d'une paire d'inverseurs rétrocouplés (230, 236) et dans lequel l'entrée de test série (209) est couplée à une seconde entrée (228) de la paire d'inverseurs rétrocouplés (230, 236).
     




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    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description