(19)
(11)EP 2 097 925 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.11.2020 Bulletin 2020/45

(21)Application number: 07867901.6

(22)Date of filing:  20.12.2007
(51)International Patent Classification (IPC): 
H01L 25/065(2006.01)
H01L 23/485(2006.01)
H01L 23/48(2006.01)
(86)International application number:
PCT/US2007/026095
(87)International publication number:
WO 2008/085391 (17.07.2008 Gazette  2008/29)

(54)

STACKED PACKAGES

STAPELVERKAPSELUNGEN

BOÎTIERS EMPILÉS


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC MT NL PL PT RO SE SI SK TR

(30)Priority: 28.12.2006 US 648172

(43)Date of publication of application:
09.09.2009 Bulletin 2009/37

(73)Proprietor: Tessera, Inc.
San Jose, CA 95134 (US)

(72)Inventor:
  • HABA, Belgacem
    San Jose, CA 95134 (US)

(74)Representative: Clark, Jane Anne 
Mathys & Squire LLP The Shard 32 London Bridge Street
London SE1 9SG
London SE1 9SG (GB)


(56)References cited: : 
US-A1- 2004 155 326
US-B1- 6 177 721
US-A1- 2004 221 451
US-B1- 6 344 683
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    BACKGROUND OF THE INVENTION



    [0001] The present invention generally relates to stacked microelectronic packages and more particularly relates to stacked microelectronic packages fabricated at the wafer level and to methods of making such packages.

    [0002] Semiconductor chips are flat bodies with contacts disposed on the front surface that are connected to the internal electrical circuitry of the chip itself. Semiconductor chips are typically packaged with substrates to form microelectronic packages having terminals that are electrically connected to the chip contacts. The package may then be connected to test equipment to determine whether the packaged device conforms to a desired performance standard. Once tested, the package may be connected to a larger circuit, e.g., a circuit in an electronic product such as a computer or a cell phone.

    [0003] The substrate materials used for packaging semiconductor chips are selected for their compatibility with the processes used to form the packages. For example, during solder or other bonding operations, intense heat may be applied to the substrate. Accordingly, metal lead frames have been used as substrates. Laminate substrates have also been used to package microelectronic devices. Such substrates may include two to four alternating layers of fiberglass and epoxy, wherein successive fiberglass layers may be laid in traversing, e.g., orthogonal, directions. Optionally, heat resistive compounds such as bismaleimide triazine (BT) may be added to such laminate substrates.

    [0004] Tapes have been used as substrates to provide thinner microelectronic packages. Such tapes are typically provided in the form of sheets or rolls of sheets. For example, single and double sided sheets of copper-on-polyimide are commonly used. Polyimide based films offer good thermal and chemical stability and a low dielectric constant, while copper having high tensile strength, ductility, and flexure has been advantageously used in both flexible circuit and chip scale packaging applications. However, such tapes are relatively expensive, particularly as compared to lead frames and laminate substrates.

    [0005] Microelectronic packages also include wafer level packages, which provide a package for a semiconductor component that is fabricated while the die are still in a wafer form. The wafer is subject to a number of additional process steps to form the package structure and the wafer is then diced to free the individual die, with no additional fabrication steps being necessary. Wafer level processing provides an advantage in that the cost of the packaging processes are divided among the various die on the wafer, resulting in a very low price differential between the die and the component. Furthermore, the package footprint can be substantially similar to the die size, resulting in very efficient utilization of area on a printed circuit board (PCB) to which the die will eventually be attached. As a result of these features, die packaged in this manner are commonly referred to as wafer level chip scale package (WLCSP).

    [0006] In order to save space certain conventional designs have stacked multiple microelectronic chips within a package. This allows the package to occupy a surface area on a substrate that is less than the total surface area of the chips in the stack.

    [0007] In spite of the above advances, there remains a need for improved wafer-scale packages and especially stacked wafer-scale packages that are reliable and that are economical to manufacture.

    [0008] US2004/0221451 describes an example in which two substrates each having active devices formed on a respective active side are joined together at the substrate level. Each substrate includes a substrate base layer on which is formed an active device layer. The active areas include a plurality of die that include the active circuits electrically connected to bond pads. Individual die are separated from each other by saw streets. The backsides of the top and bottom substrates are bought into contact with adhesive and the saw streets are vertically aligned. A plurality of through vias or apertures are formed in the saw streets through both the top substrate and the bottom substrate.

    [0009] A plurality of conductive lines are formed from the top die bond pads to the edge of the die and through a respective via to bottom die bond pads. The vertically aligned dice joined by the adhesive are thus electrically connected together through a conductive line. The individual joined die assembly can now be singulated or diced and as shown in Figure 19 of US2004/0221451 the conductive line remains in part of the via after cutting the adjacent die assemblies apart during singulation or dicing.

    [0010] Further stacked microelectronic packages are disclosed in US6344683B1 and US6177721B1.

    SUMMARY OF THE INVENTION



    [0011] The present invention is set out in the apended claims. In particular, the invention provides a stacked stacked unit in accordance with claim 1 and a method of forming a stacked unit in accordance with claim 6. Preferred embodiments are defined in the dependent claims.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0012] In the following figures:

    Figures 1-4 illustrate an embodiment of the method of invention.

    Figure 3 illustrates an embodiment of the stacked unit of the invention.

    Figures 5-9 are not in accordance with the invention.

    FIG. 1A is a top view of a subassembly;

    FIG. 1B is a cross-sectional view of the subassembly of FIG. 1A;

    FIG. 2 is a cross-sectional view of a plurality of subassemblies attached to one another to form a stacked assembly;

    FIG. 3 is a cross-sectional view of the stacked assembly of FIG. 2 after the stacked assembly has been diced into individual units;

    FIG. 4 is a cross-sectional view of individual units of FIG. 3 stacked upon each other.

    FIG. 5A is a top view of a subassembly;

    FIG. 5B is a cross-sectional view of the subassembly of FIG. 5A;

    FIG. 6 is a cross-sectional view of the subassembly of FIG. 5B at a later stage of assembly;

    FIG. 7 is a cross-sectional view of a plurality of subassemblies of FIG. 6 attached to one another to form a stacked assembly;

    FIG. 8 is a cross-sectional view of the stacked assembly of FIG. 7 after the stacked assembly has been diced into individual units; and

    FIG. 9 is a cross-sectional view of individual units of FIG. 8 stacked upon each other.


    DETAILED DESCRIPTION



    [0013] Reference is now made to FIGS. 1A and 1B, which illustrate a top view and a cross-sectional view, respectively of a wafer or first subassembly 10. As shown in the figures, a portion of a first wafer or subassembly 10 includes a plurality of microelectronic elements 12, each positioned side by side and adjacent to one another. The first subassembly preferably includes numerous rows of microelectronic elements 12 aligned along an X-axis and a Y-axis in various columns and rows. The microelectronic elements 12 are formed integral with one another using conventional semiconductor process techniques. The present invention is also applicable to reconstituted wafers.

    [0014] Each microelectronic element 12 includes a front face 14 and an oppositely-facing rear face 16. The microelectronic elements 12 also include first edges 18, second edges 20, third edges 19 and fourth edges 21, all of which extend from the front faces 14 to the rear faces 16 of the microelectronic elements 12. As shown in FIGS. 1A and 1B, a first edge 18 of one microelectronic element 12 is attached to a second edge 20 of a second and adjacent microelectronic element 12. Thus, the microelectronic elements 12 positioned within the middle of the first subassembly 10 are bordered by an adjacent microelectronic element 12 at all four edges, as shown in FIG. 1A. The microelectronic elements 12 positioned at a first end 11, a second end 13, a third end 15 or a fourth end 17 of the wafer have at least one edge unencumbered by an additional microelectronic element.

    [0015] Although the edges are depicted in the drawings for clarity of illustration, in practice the edges may not be visible. Rather, at this stage the edges or strips where adjacent microelectronic elements 12 contact one another are saw lanes or strips where the wafer can be cut without damaging the individual microelectronic elements. For instance, as shown in FIG. 1B, second edge 20' of microelectronic element 12' abuts first edge 18" of microelectronic element 12" and forms a saw lane 23. Similarly, throughout the wafer 10, saw lanes 23 are located at positions where microelectronic elements 12 abut one another. The first wafer/subassembly 10 may include any number of microelectronic elements including as little as one or as many as is desirable.

    [0016] Each of the microelectronic elements 12 in subassembly 10 also include a plurality of contacts 22 exposed at their respective front faces 16. Further, the contacts 22 are attached to traces 24 that extend from the contacts 22 to an edge of the microelectronic element. For instance, microelectronic 12' includes contact 22' and trace 24', which extends from contact 22' to first edge 18' of the microelectronic element 12'. Similarly, microelectronic element 12" includes contact 22" and trace 24", which extends from contact 22" to second edge 20" of microelectronic element 12". In one embodiment, traces 24' and 24" actually are a unitary structure extending between contacts 22' and 22'' of adjacent microelectronic elements 12', 12''. Thus, traces 24' and 24'' meet at the attachment point of microelectronic elements 12' and 12", or at saw lane 23'. However, it is not required that the traces actually contact one another but rather that these traces 24 simply extend toward a respective end of the microelectronic elements 12 and into the width of the saw lanes.

    [0017] As shown in FIG. 2, to create a stacked assembly 30, the first subassembly 10 is positioned under a second wafer/subassembly 10A. The second subassembly 10A is similarly constructed to the first subassembly 10, and thus like elements will be given similar character references unless otherwise specified.

    [0018] As shown in FIG. 2, the second assembly 10A is inverted such that contacts 22A exposed at front faces 14A of microelectronic elements 12A face in an opposite direction as opposed to contacts 22 of subassembly 10. Thus, as shown in FIG. 2, the rear faces 16A of subassembly 10A face towards the rear faces 16 of subassembly 10. When positioning the respective subassemblies 10, 10A, the microelectronic elements 12 are aligned with the microelectronic elements 12A. The respective first, second, third, and fourth edges of each of the microelectronic elements 12,12A are aligned along respective longitudinal axes. And the respective saw lanes 23, 23A of each of the subassemblies 10, 10A are also aligned. The stacked assembly 30 consists of a plurality of microelectronic elements 12, 12A, oriented and aligned in various rows and columns.

    [0019] To attach the two subassemblies 10, 10a, an adhesive layer 32 is positioned between the rear faces 16, 16A and adhered thereto. The adhesive layer 32 is preferably comprised of an adhesive, epoxy or the like, and once cured, maintains a connection between the two subassemblies 10, 10A, such that the subassemblies are attached to one another and form stacked assembly 30. The two subassemblies 10, 10A may be attached using other methods that do not involve the use of an adhesive such as directly attaching the rear faces 16 of the subassembly 10 to the rear faces 16A of the second subassembly 10A. For example, solder bonding, eutectic bonding, diffusion bonding or other known bonding procedures can be used.

    [0020] Next, the stacked assembly 30 is diced to form individual stacked units 34 using a mechanical cutting instrument not shown in the figures. Examples of such a mechanical cutting instrument can be found in U.S. Patent Nos. 6,646,289 and 6,972,480. The stacked assembly 30 is diced at locations that correspond to saw lanes 23, 23A of the individual subassemblies 10, 10A and various edges of the microelectronic elements 12, 12A. Since the ends of the traces 24, 24A that are remote from the contacts 22, 22A are positioned within the saw lanes 23, 23A, the dicing of the stacked assembly 30 causes these ends to become exposed.

    [0021] Each individual stacked unit 34 includes a microelectronic element 12A disposed above a microelectronic element 12 and attached thereto by adhesive layer 32. The respective front faces 14, 14A of the microelectronic elements 12, 12A face in opposite directions as do the contacts 22, 22A of respective microelectronic elements. In addition, the individual stacked units 34 include a first side wall 36 and a second side wall 38 that extend between the front faces 14, 14A of the microelectronic elements 12 and 12A. Adjacent to both side walls 36, 38 are the ends of the traces 24, 24A that are exposed after the dicing process.

    [0022] Bridging elements such as trace bridges 40 are then formed on the side walls 36 and 38. A trace bridge 40 extends from a trace 40 across either side wall 36 or side wall 38 to a trace 24A, and thereby electrically interconnects the two traces disposed on opposite faces of individual stacked units 34. The traces bridges extend about the edges of the microelectronic elements as well as the edges of the adhesive layer 32 that is exposed as a result of the dicing process. As a result of the trace bridge 40, a contact 22 is in electrical communication with a contact 22A. Prior to the trace bridges 40 being formed, a dielectric layer 41 may be disposed onto the exposed edges of the microelectronic elements and adhesive layer so as to electrically isolate the trace bridges from the bodies of the microelectronic elements if desired.

    [0023] With reference still to FIG. 3, a mass of conductive material 42 may be deposited onto contacts 22 so as to enable the individual stacked units 34 to be electrically connected to a substrate such as a circuit panel and the like. The mass of conductive material 42 may be a ball of solder or similar material.

    [0024] Individual stacked units 34 and 34' may be stacked one upon another with contacts of individual stacked unit 34 being electrically connected to contacts of individual stacked unit 34' as shown in FIG. 4. For example, to electrically connect the individual stacked units 34, 34', the contacts 50 exposed at a lower surface 52 of stacked unit 34 is aligned with the contacts 50' exposed at the top surface 54' of stacked unit 34' The contacts 50 and 50' may then be electrically connected using a mass of conductive material 56 such as solder or attached to one another using other methods known to those in the art.

    [0025] A subassembly 110 including a plurality of microelectronic elements 112 may be provided as shown in FIGS. 5A and 5B. Subassembly 110 is similarly constructed as subassembly 10 and includes many of the same features. For this reason, like elements will be given similar character references unless otherwise specified. The microelectronic elements 112 of subassembly 110 include a front face 114 and an oppositely-facing rear face 116.

    [0026] Additionally, each microelectronic element 112 includes a first edge 118, a second edge 120, a third edge 119 and a fourth edge 121 extending between the front face 114 and rear face 116. The locations were one edge of a first microelectronic element abuts an edge of a second microelectronic element forms saw lanes 123. As mentioned with regard to subassembly 10, the saw lanes may be cut there through without damaging the individual microelectronic elements 112 of the subassembly 110. And although demarcation lines are shown in FIGS. 5A to 5B for clarity of illustration, in practice a clear separation between adjacent microelectronic elements 112 may not be recognizable. Each microelectronic element 112 also includes a plurality of contacts 122 exposed at their respective front face 114. Although the subassembly 110 is illustrated having four rows and three columns of microelectronic elements, the number of microelectronic elements may be as little as one and as many as is desirable.

    [0027] Next, with reference to FIG. 6, the subassembly 110 is subjected to a mechanical cutting process that bores vias 130 through each of the microelectronic elements 112. The vias extend from a rear face 116 to a front face 114 of each of the microelectronic elements. And each of the vias 130 is preferably aligned with a contact 122 exposed on the front face 114 of each of the microelectronic elements 112 such that the contacts 122 are not only exposed at the front faces 114 but also at the rear faces 116.

    [0028] After the vias 130 are formed, they are filled with a conductive material 131 such as a metal. The conductive material 131 may for instance be formed from copper or a copper/gold alloy.

    [0029] As shown in FIG. 7, a stacked assembly 132 may be assembled by attaching the first subassembly 110 to a second subassembly 110'. The second subassembly 110' is similarly constructed as subassembly 110 and like features are described using similar character references unless otherwise specified. To form stacked assembly 132, the second subassembly 110' is inverted such that the rear faces 116' of the microelectronic elements 112' of the second subassembly face toward the rear faces 116 of microelectronic elements 112. When aligning the two subassemblies, the saw lanes 123 of subassembly 110 are aligned with the saw lanes 123' of second subassembly 110' and the vias 130, 130' of each of the subassemblies are also aligned. By aligning the vias 130 to the vias 130', the contacts 122 of the microelectronic elements 112 are aligned with the contacts 122' of the second subassembly and the conductive material 131, 131' of each of the vias 130, 130' are brought proximate to one another.

    [0030] To attach the second subassembly 110' to the subassembly 110, a second conductive material 137 may be utilized. For example, masses of the second conductive material 137, such as solder, are disposed in and around the vias 130 proximate the rear faces 116 of the microelectronic elements 112 and in contact with the conductive material 131 contained within the vias. The subassembly 110 is then brought proximate with the second subassembly 110' such that the second conductive material 137 is proximate vias 130' and in contact with the conductive material 131' of the second subassembly. As shown in FIG. 7, this configuration causes the contacts 122 to be electrically connected to contacts 122' through the various conductive materials disposed within the vias 130, 130' and thus the conductive material 131, 131' act as electrical bridges between contacts 122, 122'. A back fill such as encapsulant material 134 or an adhesive may be positioned between the two subassemblies 110, 110' to provide additional rigidity to the stacked assembly 132.

    [0031] In an alternate example, although not shown in the figures, the conductive material 131 of subassembly 110 may be directly adhered to the conductive material 131' of the second subassembly 110'. For instance, if the conductive material 130, 130' is copper, the copper in each via 130, 130' is reflowed and allowed to contact the copper in an aligned via. Once solidified, the copper in adjacent vias 130, 130', forms, not only an attachment area between the subassemblies but also an electrical connection between contacts 122, 122'.

    [0032] The stacked assembly 132 is now ready to be diced into individual stacked units 140. For this, a similar mechanical instrument (not shown in the figures) described previously is brought proximate the saw lanes 123, 123' of each of the subassemblies 110, 110'. The mechanical tool is passed through the stacked assembly 132 at positions that correspond to the saw lanes 123, 123' thereby dissecting the stacked assembly into individual stacked units 140. Of course, if the stacked assembly 132 was created with subassemblies that only included single microelectronic elements a dissection step is not required. A mass of solder 142 or other conductive material may be disposed on exposed contacts 122 or 122' so as to enable the individual stacked units 140 to be attached to a substrate such as a circuit panel.

    [0033] The stacked assembly 132 may also be attached to a circuit panel without having to dice the assembly into individual units if desired.

    [0034] According to one example, individual stacked units 140 and 140' may be stacked one upon another with the contacts of individual stacked unit 140 being electrically connected to contacts of individual stacked unit 140'. For example, to electrically connect the individual stacked units 140, 140', the contacts 150 exposed at a lower surface 152 of stacked unit 140 are aligned with the contacts 150' exposed at the top surface 154' of stacked unit 140' The contacts 150 and 150' may then be electrically connected using a mass of conductive material 156 such as solder or attached to one another using other methods known to those in the art. The entire assembly 160 may be attached to a substrate such as circuit panel 170 illustrated in FIG. 9, which includes conductive pads 172.

    [0035] Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the scope of the present invention as defined by the appended claims.


    Claims

    1. A stacked unit comprising:

    a first microelectronic element (12) having a first rear surface (16);

    a second microelectronic element (12a) having a second rear surface (16a), the second microelectronic element attached to the first microelectronic element so as to form an individual stacked unit (34);

    wherein in said individual stack unit (34) the second microelectronic element overlies the first microelectronic element such that the first rear surface (16) of the first microelectronic element (12) faces toward the second rear surface (16a) of the second microelectronic element (12a); and

    at least one bridging element (40), wherein the first microelectronic element and second microelectronic element each have a front surface (14, 14a) and a plurality of contacts (22) exposed thereat, said contacts (22) also being exposed contacts of the individual stacked unit for connection to a substrate or a further stacked unit, wherein the at least one bridging element (40) extends between the plurality of contacts (22) of the first microelectronic element and the plurality of contacts (22) of the second microelectronic element so as to electrically connect the two,

    wherein the first and second microelectronic elements (12, 12a) each include a first exposed edge and a second exposed edge extending from the front surface (14, 14a) to the rear surface (16, 16a) of the microelectronic element, wherein the first exposed edge of the first microelectronic element is aligned with the first exposed edge of the second microelectronic element, thereby forming a first sidewall (36) of said individual stacked unit (34),

    wherein the second exposed edge of the first microelectronic element is aligned with the second exposed edge of the second microelectronic element, thereby forming a second sidewall of said individual stacked unit, and wherein the first and second microelectronic elements each include a third and a fourth exposed edge extending from the front surface to the rear surface of the microelectronic element, wherein the third exposed edge of the first microelectronic element is aligned with the third exposed edge of the second microelectronic element, thereby forming a third sidewall of said individual stacked unit, and wherein the fourth exposed edge of the first microelectronic element is aligned with the fourth exposed edge of the second microelectronic element, thereby forming a fourth sidewall of said individual stacked unit;

    wherein the at least one bridging element (40) is formed on the first sidewall (36).


     
    2. The stacked unit of claim 1, further comprising a plurality of traces (24) exposed on the respective front surfaces (14, 14a) of the first microelectronic element (12) and second microelectronic element (12a), at least some of the plurality of traces (24) extending from at least some of the plurality of contacts (22) on the first microelectronic element to the at least one bridging element (40) and at least some of the plurality of traces (24) extending from at least some of the plurality of contacts (22) of the second microelectronic element to the at least one bridging element (40).
     
    3. The stacked unit of claim 2, further comprising an adhesive (32) that attaches the first microelectronic element to the second microelectronic element (12a).
     
    4. The stacked unit of claim 1, further comprising a third microelectronic element having a front face and a rear face and a fourth microelectronic element having a rear face, wherein the third and fourth microelectronic elements are attached such that the rear face of the third microelectronic element faces toward the rear face of the fourth microelectronic element, the third microelectronic element also being attached to the first second microelectronic element such that the front face of the third microelectronic element faces toward the front surface of the second microelectronic element.
     
    5. The stacked unit of claim 1, wherein a mass of conductive material (42) is deposited onto the contacts (22) so as to enable electrical connection to a substrate.
     
    6. A method of forming a stacked unit, comprising the steps of:

    forming a microelectronic assembly (30) by stacking a first subassembly (10) including a plurality of microelectronic elements (12) onto a second subassembly (10a) including a plurality of microelectronic elements (12a), wherein the rear faces of the first subassembly and second subassembly confront one another and wherein the first subassembly and second subassembly each include saw lanes (23) separating the respective microelectronic elements in the respective subassemblies, the saw lanes being aligned during the step of forming the microelectronic assembly, wherein the first subassembly includes a plurality of contacts (22) exposed at a front face of the first subassembly and the second subassembly includes a plurality of contacts (22) exposed at a front face of the second subassembly;
    dicing through the saw lanes of the first and second subassemblies so as to form individual stacked units (34) consisting of a first microelectronic element (12) stacked on a second microelectronic element (12a), wherein at least some of the plurality of microelectronic elements of the first subassembly and the second subassembly have traces that extend from the respective contacts (22) of the first and second subassemblies to the saw lanes of the respective first and second subassemblies such that after the dicing step ends of the traces (24a) are exposed,

    after the dicing step, forming electrically conductive bridging elements (40) electrically connecting the traces (24a) extending from the plurality of contacts (22) exposed at the front face of the first microelectronic element of the individual stacked unit (34) to the traces (24a) extending from the plurality of contacts (22) exposed at a front face of the second microelectronic element of the individual stacked unit (34), wherein each microelectronic element has first to fourth exposed edges exposed during the step of dicing through the saw lanes, said exposed edges extending from the front surface to the rear surface of the microelectronic element, and said bridging elements (40) are disposed on the exposed edges of both the first and the second microelectronic elements,
    wherein said contacts (22) exposed at the front face of the respective first and second microelectronic element of the individual stacked unit (34) are exposed contacts of the individual stacked unit (34) for connection to a substrate or a further stacked unit.


     
    7. A method of assembling a stacked package comprising the steps of forming a first stacked unit and a second stacked unit according to claim 6, further comprising electrically connecting at least some of the contacts (22) of the first stacked unit to at least some of the contacts (22) of the second stacked unit.
     


    Ansprüche

    1. Gestapelte Einheit aufweisend:

    ein erstes mikroelektronisches Element (12) mit einer ersten hinteren Oberfläche (16);

    ein zweites mikroelektronisches Element (12a) mit einer zweiten hinteren Oberfläche (16a), wobei das zweite mikroelektronische Element an dem ersten mikroelektronischen Element befestigt ist, um so eine individuelle gestapelte Einheit (34) zu bilden;

    wobei in der individuell gestapelten Einheit (34) das zweite mikroelektronische Element über dem ersten mikroelektronischen Element liegt, so dass die erste hintere Oberfläche (16) des ersten mikroelektronischen Elements (12) der zweiten hinteren Oberfläche (16a) des zweiten mikroelektronischen Elements (12a) zugewandt ist; und

    mindestens ein Überbrückungselement (40), wobei das erste mikroelektronische Element und das zweite mikroelektronische Element jeweils eine vordere Oberfläche (14, 14a) und eine Vielzahl von Kontakten (22) aufweisen, die an dieser freiliegen, wobei die Kontakte (22) auch freiliegende Kontakte der individuell gestapelten Einheit zur Verbindung mit einem Substrat oder einer weiteren gestapelten Einheit sind, wobei sich das mindestens eine Überbrückungselement (40) zwischen der Vielzahl von Kontakten (22) des ersten mikroelektronischen Elements und der Vielzahl von Kontakten (22) des zweiten mikroelektronischen Elements erstreckt, um die beiden elektrisch zu verbinden,

    wobei das erste und das zweite mikroelektronische Element (12, 12a) jeweils eine erste freiliegende Kante und eine zweite freiliegende Kante aufweisen, die sich von der vorderen Oberfläche (14, 14a) zu der hinteren Oberfläche (16, 16a) des mikroelektronischen Elements erstrecken, wobei die erste freiliegende Kante des ersten mikroelektronischen Elements mit der ersten freiliegenden Kante des zweiten mikroelektronischen Elements ausgerichtet ist, wodurch eine erste Seitenwand (36) der individuell gestapelten Einheit (34) gebildet wird,

    wobei die zweite freiliegende Kante des ersten mikroelektronischen Elements mit der zweiten freiliegenden Kante des zweiten mikroelektronischen Elements ausgerichtet ist, wodurch eine zweite Seitenwand der individuell gestapelten Einheit gebildet wird, und wobei das erste und das zweite mikroelektronische Element jeweils eine dritte und eine vierte freiliegende Kante aufweisen, die sich von der Vorderfläche zur Rückfläche des mikroelektronischen Elements erstrecken, wobei die dritte freiliegende Kante des ersten mikroelektronischen Elements mit der dritten freiliegenden Kante des zweiten mikroelektronischen Elements ausgerichtet ist, wodurch eine dritte Seitenwand der individuell gestapelten Einheit gebildet wird, und wobei die vierte freiliegende Kante des ersten mikroelektronischen Elements mit der vierten freiliegenden Kante des zweiten mikroelektronischen Elements ausgerichtet ist, wodurch eine vierte Seitenwand der individuell gestapelten Einheit gebildet wird;

    wobei das mindestens eine Brückenelement (40) an der ersten Seitenwand (36) ausgebildet ist.


     
    2. Gestapelte Einheit nach Anspruch 1, ferner aufweisend eine Vielzahl von Leiterbahnen (24), die auf den jeweiligen vorderen Oberflächen (14, 14a) des ersten mikroelektronischen Elements (12) und des zweiten mikroelektronischen Elements (12a) freiliegen, wobei sich mindestens einige der Mehrzahl von Leiterbahnen (24) von mindestens einigen der Mehrzahl von Kontakten (22) auf dem ersten mikroelektronischen Element zu dem mindestens einen Brückenelement (40) erstrecken, und sich mindestens einige der Mehrzahl von Leiterbahnen (24) von mindestens einigen der Mehrzahl von Kontakten (22) des zweiten mikroelektronischen Elements zu dem mindestens einen Brückenelement (40) erstrecken.
     
    3. Gestapelte Einheit nach Anspruch 2, ferner mit einem Klebstoff (32), der das erste mikroelektronische Element an dem zweiten mikroelektronischen Element (12a) befestigt.
     
    4. Gestapelte Einheit nach Anspruch 1, weiterhin aufweisend ein drittes mikroelektronisches Element mit einer Vorderseite und einer Rückseite und ein viertes mikroelektronisches Element mit einer Rückseite, wobei das dritte und das vierte mikroelektronische Element so befestigt sind, dass die Rückseite des dritten mikroelektronischen Elements zur Rückseite des vierten mikroelektronischen Elements weist, wobei das dritte mikroelektronische Element auch an dem ersten zweiten mikroelektronischen Element so befestigt ist, dass die Vorderseite des dritten mikroelektronischen Elements zur vorderen Oberfläche des zweiten mikroelektronischen Elements weist.
     
    5. Gestapelte Einheit nach Anspruch 1, wobei eine Masse aus leitfähigem Material (42) auf den Kontakten (22) aufgebracht ist, um eine elektrische Verbindung mit einem Substrat zu ermöglichen.
     
    6. Verfahren zum Bilden einer gestapelten Einheit, aufweisend die folgenden Schritte:

    Bilden einer mikroelektronischen Baugruppe (30) durch Stapeln einer ersten Unterbaugruppe (10), die eine Vielzahl von mikroelektronischen Elementen (12) enthält, auf einer zweiten Unterbaugruppe (10a), die eine Vielzahl von mikroelektronischen Elementen (12a) enthält, wobei die Rückseiten der ersten Unterbaugruppe und der zweiten Unterbaugruppe einander gegenüberliegen und wobei die erste Unterbaugruppe und die zweite Unterbaugruppe jeweils Sägespuren (23) enthalten, die die jeweiligen mikroelektronischen Elemente in den jeweiligen Unterbaugruppen trennen, wobei die Sägespuren während des Schritts des Bildens der mikroelektronischen Baugruppe ausgerichtet werden, wobei die erste Unterbaugruppe eine Vielzahl von Kontakten (22) aufweist, die an einer Vorderseite der ersten Unterbaugruppe freiliegen, und die zweite Unterbaugruppe eine Vielzahl von Kontakten (22) aufweist, die an einer Vorderseite der zweiten Unterbaugruppe freiliegen;

    Zerteilen der ersten und zweiten Unterbaugruppe durch die Sägespuren, um so individuell gestapelte Einheiten (34) zu bilden, die aus einem ersten mikroelektronischen Element (12) bestehen, das auf ein zweites mikroelektronisches Element (12a) gestapelt ist, wobei zumindest einige der Vielzahl von mikroelektronischen Elementen der ersten Unterbaugruppe und der zweiten Unterbaugruppe Leiterbahnen aufweisen, die sich von den jeweiligen Kontakten (22) der ersten und zweiten Unterbaugruppe zu den Sägespuren der jeweiligen ersten und zweiten Unterbaugruppe erstrecken, so dass nach dem Zerteilungsschritt Enden der Leiterb ahnen (24a) freigelegt sind,

    nach dem Zerteilungsschritt, Bilden elektrisch leitender Brückenelemente (40), die die Leiterbahnen (24a), die sich von der Vielzahl von Kontakten (22), die an der Vorderseite des ersten mikroelektronischen Elements der individuell gestapelten Einheit (34) freiliegen, zu den Leiterbahnen (24a), die sich von der Vielzahl von Kontakten (22), die an einer Vorderseite des zweiten mikroelektronischen Elements der individuell gestapelten Einheit (34) freiliegen, erstrecken, elektrisch verbinden, wobei jedes mikroelektronische Element erste bis vierte freiliegende Kanten aufweist, die während des Zerteilungsschrittes durch die Sägespuren freigelegt werden, wobei sich die freiliegenden Kanten von der vorderen Oberfläche zur hinteren Oberfläche des mikroelektronischen Elements erstrecken, und wobei die Brückenelemente (40) an den freiliegenden Kanten sowohl des ersten als auch des zweiten mikroelektronischen Elements angeordnet sind,

    wobei die Kontakte (22), die an der Vorderseite des jeweiligen ersten und zweiten mikroelektronischen Elements der individuell gestapelten Einheit (34) freiliegen, freiliegende Kontakte der individuell gestapelten Einheit (34) zur Verbindung mit einem Substrat einer weiteren gestapelten Einheit sind.


     
    7. Verfahren zumZusammensetzen eines gestapelten Pakets, aufweisend die Schritte zum Bilden einer ersten gestapelten Einheit und einer zweiten gestapelten Einheit nach An spruch 6, ferner aufweisend ein elektrisches Verbinden mindestens einiger der Kontakte (22) der ersten gestapelten Einheit mit mindestens einigen der Kontakte (22) der zweiten gestapelten Einheit.
     


    Revendications

    1. Unité empilée comprenant :

    un premier élément microélectronique (12) présentant une première surface arrière (16) ;

    un deuxième élément microélectronique (12a) présentant une seconde surface arrière (16a), le deuxième élément microélectronique étant fixé au premier élément microélectronique de manière à former une unité empilée individuelle (34) ;

    dans laquelle dans ladite unité empilée individuelle (34) le deuxième élément microélectronique recouvre le premier élément microélectronique de telle sorte que la première surface arrière (16) du premier élément microélectronique (12) soit tournée vers la seconde surface arrière (16a) du deuxième élément microélectronique (12a) ; et

    au moins un élément de pontage (40), les premier élément microélectronique et deuxième élément microélectronique présentant chacun une surface avant (14, 14a) et une pluralité de contacts (22) exposée au niveau de celle-ci, lesdits contacts (22) étant également des contacts exposés de l'unité empilée individuelle en vue d'une connexion à un substrat ou à une autre unité empilée, l'au moins un élément de pontage (40) s'étendant entre la pluralité de contacts (22) du premier élément microélectronique et la pluralité de contacts (22) du deuxième élément microélectronique de manière à connecter électriquement les deux,

    dans laquelle les premier et deuxième éléments microélectroniques (12, 12a) comportent chacun un premier bord exposé et un deuxième bord exposé s'étendant depuis la surface avant (14, 14a) jusqu'à la surface arrière (16, 16a) de l'élément microélectronique, le premier bord exposé du premier élément microélectronique étant aligné avec le premier bord exposé du deuxième élément microélectronique, formant ainsi une première paroi latérale (36) de ladite unité empilée individuelle (34),

    dans laquelle le deuxième bord exposé du premier élément microélectronique est aligné avec le deuxième bord exposé du deuxième élément microélectronique, formant ainsi une deuxième paroi latérale de ladite unité empilée individuelle, et dans laquelle les premier et deuxième éléments microélectroniques comportent chacun un troisième et un quatrième bord exposé s'étendant depuis la surface avant jusqu'à la surface arrière de l'élément microélectronique, le troisième bord exposé du premier élément microélectronique étant aligné avec le troisième bord exposé du deuxième élément microélectronique, formant ainsi une troisième paroi latérale de ladite unité empilée individuelle, et le quatrième bord exposé du premier élément microélectronique étant aligné avec le quatrième bord exposé du deuxième élément microélectronique, formant ainsi une quatrième paroi latérale de ladite unité empilée individuelle ;

    dans laquelle l'au moins un élément de pontage 40) est formé sur la première paroi latérale (36).


     
    2. Unité empilée selon la revendication 1, comprenant en outre une pluralité de tracés (24) exposée sur les surfaces avant respectives (14, 14a) du premier élément microélectronique (12) et du deuxième élément microélectronique (12a), au moins certains de la pluralité de tracés (24) s'étendant depuis au moins certains de la pluralité de contacts (22) sur le premier élément microélectronique jusqu'à l'au moins un élément de pontage (40) et au moins certains de la pluralité de tracés (24) s'étendant depuis au moins certains de la pluralité de contacts (22) du deuxième élément microélectronique jusqu'à l'au moins un élément de pontage (40).
     
    3. Unité empilée selon la revendication 2, comprenant en outre un adhésif (32) qui fixe le premier élément microélectronique au deuxième élément microélectronique (12a).
     
    4. Unité empilée selon la revendication 1, comprenant en outre un troisième élément microélectronique présentant une face avant et une face arrière et un quatrième élément microélectronique présentant une face arrière, les troisième et quatrième éléments microélectroniques étant fixés de telle sorte que la face arrière du troisième élément microélectronique soit tournée vers la face arrière du quatrième élément microélectronique, le troisième élément microélectronique étant également fixé au premier deuxième élément microélectronique de telle sorte que la face avant du troisième élément microélectronique soit tournée vers la face avant du deuxième élément microélectronique.
     
    5. Unité empilée selon la revendication 1, dans laquelle une masse de matériau conducteur (42) est déposée sur les contacts (22) de manière à permettre une connexion électrique à un substrat.
     
    6. Procédé de formation d'une unité empilée, comprenant les étapes suivantes :

    la formation d'un ensemble microélectronique (30) en empilant un premier sous-ensemble (10) comportant une pluralité d'éléments microélectroniques (12) sur un second sous-ensemble (10a) comportant une pluralité d'éléments microélectroniques (12a), dans lequel les faces arrières du premier sous-ensemble et du second sous-ensemble sont tournées l'une vers l'autre et dans lequel le premier sous-ensemble et le second sous-ensemble comportent chacun des voies de sciage (23) qui séparent les éléments microélectroniques respectifs dans les sous-ensembles respectifs, les voies de sciage étant alignées durant l'étape de formation de l'ensemble microélectronique, le premier sous-ensemble comportant une pluralité de contacts (22) exposés au niveau d'une face avant du premier sous-ensemble et le second sous-ensemble comportant une pluralité de contacts (22) exposés au niveau d'une face avant du second sous-ensemble ;

    le découpage en dés à travers les voies de sciage des premier et second sous-ensembles de manière à former des unités empilées individuelles (34) consistant en un premier élément microélectronique (12) empilé sur un deuxième élément microélectronique (12a), dans lequel au moins certains de la pluralité d'éléments microélectroniques du premier sous-ensemble et du second sous-ensemble présentent des tracés qui s'étendent depuis des contacts respectifs (22) des premier et second sous-ensembles jusqu'aux voies de sciage des premier et second sous-ensembles respectifs de telle sorte qu'au terme de l'étape de découpage en dés des extrémités des tracés (24a) soient exposées,

    après l'étape de découpage en dés, la formation d'éléments de pontage électriquement conducteurs (40) qui connectent électriquement les tracés (24a) s'étendant depuis la pluralité de contacts (22) exposés au niveau de la face avant du premier élément microélectronique de l'unité individuelle (34) jusqu'aux tracés (24a) s'étendant depuis la pluralité de contacts (22) exposés au niveau d'une face avant du deuxième élément microélectronique de l'unité empilée individuelle (34), chaque élément microélectronique présentant des premier à quatrième bords exposés qui sont exposés durant l'étape de découpage en dés à travers les voies de sciage, lesdits bords exposés s'étendant depuis la surface avant jusqu'à la surface arrière de l'élément microélectronique, et lesdits éléments de pontage (40) étant disposés sur les bords exposés des deux premier et deuxième éléments microélectroniques, lesdits contacts (22) exposés au niveau de la face avant des premier et deuxième éléments microélectroniques respectifs de l'unité empilée individuelle (34) étant des contacts exposés de l'unité empilée individuelle (34) en vue d'une connexion à un substrat ou à une autre unité empilée.


     
    7. Procédé d'assemblage d'un boîtier empilé comprenant les étapes de formation d'une première unité empilée et d'une seconde unité empilée selon la revendication 6, comprenant la connexion électrique d'au moins certains des contacts (22) de la première unité empilée à au moins certains des contacts (22) de la seconde unité empilée.
     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description