(19)
(11)EP 2 165 367 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.12.2019 Bulletin 2019/49

(21)Application number: 08779641.3

(22)Date of filing:  13.06.2008
(51)Int. Cl.: 
H01L 29/808  (2006.01)
H01L 29/812  (2006.01)
H01L 29/739  (2006.01)
H01L 29/423  (2006.01)
H01L 27/098  (2006.01)
H01L 29/06  (2006.01)
H01L 21/337  (2006.01)
H01L 29/872  (2006.01)
H01L 29/10  (2006.01)
H01L 27/07  (2006.01)
H01L 21/8232  (2006.01)
(86)International application number:
PCT/US2008/007408
(87)International publication number:
WO 2008/156674 (24.12.2008 Gazette  2008/52)

(54)

IMPROVED POWER SWITCHING TRANSISTORS

VERBESSERTE LEISTUNGSSCHALTTRANSISTOREN

TRANSISTORS À COMMUTATION DE PUISSANCE PERFECTIONNÉS


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

(30)Priority: 13.06.2007 US 808915

(43)Date of publication of application:
24.03.2010 Bulletin 2010/12

(73)Proprietor: Northrop Grumman Systems Corporation
Falls Church, VA 22042-4511 (US)

(72)Inventors:
  • McNUTT, Ty, R.
    Columbia, MD 21046 (US)
  • STEWART, Eric
    Silver Spring, MD 20901 (US)
  • CLARKE, Rowland, C.
    Sykesville, MD 21784 (US)
  • SINGH, Ranbir
    South Riding, VA 20152 (US)
  • VAN CAMPEN, Stephen
    Clarksville, MD 21029 (US)
  • SHERWIN, Marc, E.
    Catonsville, MD 21228 (US)

(74)Representative: Whitlock, Holly Elizabeth Ann 
Maucher Jenkins 26 Caxton Street
London SW1H 0RJ
London SW1H 0RJ (GB)


(56)References cited: : 
US-A- 4 262 296
US-A- 5 342 795
US-B1- 6 303 947
US-B2- 6 809 358
US-B2- 7 202 528
US-A- 5 262 668
US-A1- 2002 167 011
US-B1- 6 362 495
US-B2- 7 164 160
  
  • YANG GAO ET AL: "Trench Power JFET with Integrated Junction Barrier Schottky Diode", THE 2006 IEEE INDUSTRY APPLICATIONS CONFERENCE FORTY-FIRST IAS ANNUAL MEETING, CONFERENCE RECORD OF, IEEE, PISCATAWAY, NJ, US, 1 October 2006 (2006-10-01), pages 359-363, XP031026057, ISBN: 978-1-4244-0364-6
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

FIELD OF THE INVENTION



[0001] The invention relates generally to electronic devices, specifically to improved power switching transistors.

BACKGROUND OF THE INVENTION



[0002] Transistors have many applications. For example, transistors can be used as a switch or can be used to amplify an input current. As a switch, a transistor may be either fully "on" with maximum current flow, or fully "off' with minimal, ideally zero, current. As an amplifier, a transistor can amplify the small output current from a logic chip so that it can operate a larger device such as a relay or other high current device. Transistors are incorporated into most electrical circuits.

[0003] Designers strive to make continuous improvements to make transistors smaller and exhibit improved performance. US 2002/0167011 describes a variety of silicon carbide J-FET semiconductor devices including double gated structures in which the two J-FETs are both vertical J-FETs. The article, YANG GAO et al.; "Trench Power JFET with integrated junction barrier Schottky diode", The 2006 IEEE Industry applications conference 41st IAS annual meeting, conference record of, IEEE Piscataway NJ, US, October 2006, pages 359-363, describes a trench power JFET with integrated junction barrier Schottky diode.

SUMMARY OF THE INVENTION



[0004] A dual gated integrated device is proposed which comprises first vertical junction field-effect transistor (VJFET). The first VJFET comprises a first VJFET source, a pair of first upper gates disposed on each side of the first VJFET source, a first upper N channel disposed between the pair of first upper gates, a first N drift region disposed adjacent to the first upper N channel, a first pair of lower gates of the first VJFET in a lower N channel. The dual gated integrated device further comprises a second VJFET. The second VJFET comprises a second VJFET source, a pair of second upper gates disposed on each side of the second VJFET source, wherein a second upper N channel is disposed between the pair of second upper gates and a second pair of lower gates of the second VJFET in the lower N channel. The device further includes a Schottky contact, wherein the Schottky contact couples the first pair of lower gates of the first VJFET to the second pair of lower gates of the second VJFET, wherein the lower channel separates at least one gate of the first VJFET from at least one gate of the second VJFET, and wherein the Schottky contact forms a rectifying contact to the lower N channel, and forms ohmic, non-rectifying contacts to the first pair of lower gates of the first VJFET and the second pair of lower gates of the second VJFET; and a common source (818) connected to the first VJFET source (817) and the second VJFET source (810), and wherein the common source is insulated from the upper gates of the first VJFET and the upper gates of the second VJFET by an insulator, and is connected to the first and second pairs of lower gates.

BRIEF DESCRIPTION OF THE DRAWINGS



[0005] 

Figure 1 illustrates a vertical junction field-effect transistor (VJFET) that may be used as power switching transistor.

Figure 2 illustrates an integrated VJFET/JBSD device.

Figure 3 shows a power conditioning circuit using a conventional VJFET switch (3A), and a power conditioning circuit using an integrated VJFET/JBSD device (3B).

Figures 4 - 6 are graphs illustrating the integrated VJFET/JBSD device operation.

Figure 7 illustrates a method for fabricating integrated VJFET/JBSD device.

Figure 8 illustrates an integrated VJFET/JBSD device having a planar (non-recessed) gate structure.

Figure 9 illustrates an integrated VJFET/JBSD device having a buried-gate structure.

Figure 10 illustrates an integrated VJFET/JBSD device having a lateral JFET structure.

Figure 11 illustrates a VJFET with Schottky gates having a "dual-metal" Schottky configuration.

Figure 12 illustrates a dual-gated integrated VJFET/JBSD device, in accordance with an embodiment.

Figure 13 illustrates a Merged-PiN-Schottky (MPS) diode with an epitaxial N-resistive layer.

Figure 14 illustrates MPS diode with an implanted N-resistive layer.

Figure 15 shows graph depicting modeling results of an epitaxial MPS diode with an N- resistive layer to activate the PN junction.

Figure 16 illustrates a vertical channel trenched structure insulated gate bipolar device (IGBT) 1200 configured using Si.

Figure 17 illustrates a graph showing electron mobility using various layer configurations.

Figure 18 illustrates device epitaxial layers needed for a SiC epitaxial injection enhanced IGBT device having a vertical channel trenched structure.

Figure 19 shows various trench gate IGBT structures.

Figure 20 illustrates a non-punch through trench gate IGBT with a P implant.

Figure 21 illustrates a non-punch through trench gate IGBT with a P implant.


DETAILED DESCRIPTION



[0006] Figure 1 illustrates a recessed-gate vertical junction field-effect transistor (VJFET) 100 that may be used as power switching transistor. VJFETs may be used for wide-bandgap materials (such as silicon carbide (SiC)) that do not have a high-quality native oxide for MOS devices. The VJFET 100 includes a source 112 and a N+ source region 110. A channel 130 is disposed under the source as shown. The channel 130 separates a first gate 113 and an P+ implant 120, from a second gate 111 and P+ implant 115. The gates 111 and 113 are formed from metal that makes ohmic (non-rectifying) contact to the p+ semiconductor, and are electrically connected (not shown) such that they form two parts of the same gate electrode. The channel 130 and drift region 140 are disposed on a semiconductor N+ buffer/substrate, such as a silicon carbide. The substrate is coupled to a drain 160.

[0007] As shown by the arrow, current 190 flows from the drain 160 to the source 112, in between the two implanted P+ gate regions 115 and 120. A thick, lightly-doped "drift" region 140 separates the high-voltage drain 160 of the device 100 with the low-voltage gates 113, 111 and source 112. The spacing between the P+ gate regions 115 and 120, and the voltage applied to them, control the amount of current 190 that flows. If the P+ regions 115 and 120 are spaced far apart, the device 100 is "normally-on" and current 190 flows through the channel 130 at VGs (i.e., voltage gate to source) = 0 V. To turn the device 100 off, a negative VGs must be applied, causing the depletion regions from the reverse-biased p/n junctions to pinch-off the channel 130. Alternatively, if the P+ regions 115 and 120 are close together, the built-in depletion regions will pinch-off the channel 130 with no applied bias (VAS = 0 V). In this case, the device 100 is "normally-off," and a positive voltage must be applied to the gate to turn the device "on." Although only one source and two gates are shown in Figure 1, a power VJFET may contain hundreds (or thousands) of transistors repeating this structure, all connected in parallel to obtain high currents.

[0008] For power switching applications, a VJFET may be used in a cascode configuration, in which a low-voltage normally-off (Noff) device is connected in series with a high-voltage "normally-on" (Non) device. The cascode configuration can be implemented either with two discrete devices or monolithically on a single chip. The gate of the Non device is connected to the source of the Noff device. In the off-state, the Noff initially blocks the voltage. This reverse-biases the gate-source junction of the Non device, which at some low voltage (e.g., VAS = -20 V) turns off. The Non VJFET then blocks the bulk of the high voltage (e.g., 300V-10 kV). The cascode configuration has several advantages compared to a single device, including (i) faster switching speed, due to the reduced Miller capacitance; (ii) elimination of the need for a high-voltage Noff VJFETs, which can be very resistive; and (iii) an integral anti-parallel diode.

[0009] Figure 2 illustrates an integrated VJFET/JBSD (Junction Barrier Schottky Diode) power switch 200. Figure 2 includes two VJFETs 201 and 203, configured as shown. The first VJFET, VJFET 201 includes a source 218 and a N+ source region 217. A channel 230 is disposed under the source 217, as shown. The channel 230 separates a first gate 213 and an P+ implant 220, from a second gate 266 and P+ implant 265. The channel 230 is disposed on a substrate, such as a silicon carbide. The substrate includes a N- drift region 240 and a N+ buffer/substrate 250. The substrate is coupled to a drain 260. The second VJFET 203 includes a source 212 and a N+ source region 210. A channel 230 is disposed under the source as shown. The channel 230 separates a first gate 211 and an P+ implant 215, from a second gate 267 and P+ implant 268. The gate contacts 211, 213, 266, and 267 are all formed from metal that makes ohmic contact to the semiconductor. As can be seen, the channel 230, disposed on the substrate, is common to the first VJFET 201 and the second VJFET 203. The second VJFET 203 also shares a common N- drift region 240, N+ buffer/substrate 250, and drain 260 with the first VJFET 201.

[0010] The integrated VJFET/JBSD device 200 includes a pair of gates, such as gate 266 and gate 267, and a channel 230 disposed between the gates, that are contacted by the Schottky metal 280. The Schottky metal 280 makes a Schottky (rectifying) contact to the semiconductor channel 230 and ohmic (non-rectifying) contact to the gates 266 and 267, and forms the anode for the integral JBSD contained in the device. The JBSD 202 is formed on a substrate that includes the N-drift layer 240, N+ buffer/substrate 250 and drain 260.

[0011] The gates 213, 280 and 211 of the integrated VJFET/JBSD device 200 are tied together to form a single gate for the device. The source 212 and 218 are tied together to form a single source for the device 200.

[0012] The integrated VJFET/JBSD device 200, shown in Figure 2, functions as a "normally-on" VJFET with an integral JBSD.

[0013] As shown by the arrows, for example, in the "on" state (VAS = 0 V, VAS > 0 V) transistor current 290 and 292 flows from the drain 260 to the source 217 and 210, respectively, in between the two implanted P+ gate regions. If the device is switched to the "off' state (VAS is negative enough to pinch-off the channel 230), the VJFET transistor current 290 and 292 is turned off. If, while the device is in the "off' state, a positive bias is applied gate to drain (VGD > 0 V) that is greater than the turn-on voltage of the JBSD, diode current flows in the opposite direction, as shown by arrow 291. The thick, lightly-doped "drift" region 240 separates the high-voltage drain 260 of the device 200 from the source 210 and 217 (which are tied together). The spacing between the P+ gate regions 220 and 265, and 268 and 215, is made large enough to ensure that the device 200 is "normally-on" and that current 290, 292 flows through the channel 230 at VGs = 0 V. To turn the device 200 off, a negative VGs is applied, causing the depletion regions from the reverse-biased p/n junctions to pinch-off the channel 230, between gate regions 220 and 265, and 268 and 215. Although only one set of sources and gates is shown here, a integrated VJFET/JBSD device 200 may be configured to contain hundreds or thousands of repeating source/gate fingers to obtain high currents.

[0014] For power conditioning circuits, it is often desirable to connect a JBS diode in anti-parallel configuration with the power switch, as shown in Figure 3A. This is often done using separate discrete devices for the transistor and diode. If a conventional VJFET cascode switch is used as the power switch, three separate devices are needed: normally-off VJFET 32, normally-on VJFET 31, and JBS diode 30.

[0015] A normally-on integrated VJFET/JBSD device 200, when connected in cascode configuration with a standard normally-off VJFET transistor 37, has an "anti-parallel" JBS diode 35 automatically integrated with a normally-on VJFET 36 within the device, as shown in Figure 3B. As a result, two devices, such as a normally-on integrated VJFET/JBSD device 200 and a standard normally-off VJFET transistor 37, can be used in place of three, reducing the cost and complexity, while increasing the reliability of the power conditioning circuit.

[0016] In one example, the doping concentration may be around 5 x 1015/cm3 in the n-drift layer, while the n-channel layer may have a doping concentration of about 3 x 1016/cm3. The Schottky gate, ohmic contact and source regions may have a doping concentration of 1 x 1019/cm3, and the P+ implant regions may have a doping concentrations ranging from 1 x 1016/cm3 to 1 x 1019/cm3. This doping levels are given as an example. The doping levels for devices and device regions can be varied as desirable.

[0017] Figures 4 - 6 are graphs 400, 500, and 600, respectively, illustrating a simulated integrated VJFET/JBSD device operation using device modeling software. The graphs 400, 500 and 600 confirm that integrated VJFET/JBSD device functions as a normally-on VJFET with the advantages of an integral JBSD. Figure 4 shows that as the gate-drain voltage of the integrated VJFET/JBSD device is increased from approximately .5 volts to over 3 volts (X-axis), the gate current increases from zero to 2 X 105 A/pm (Y-axis). In this simulation, the gates (including the Schottky contacts) are biased in the forward direction and the source left floating. Based on the graph 400, it can seen that the Schottky gate-drain diode turns "on" as expected.

[0018] If the gates of the integrated VJFET/JBSD device are left at zero or less and the drain-source of the integrated VJFET/JBSD device biased positive, the device acts as a "normally-on" VJFET with a pinch-off voltage of VGs = - 25 V at voltage drain to source (VDs) = 800 V, as can be seen in graph 500, Figure 5. Graph 500, shows the drain voltage \fps (X-axis) and the drain current (Y-axis) as the VGs varies from -10 V to -25 V.

[0019] Figure 6 illustrates graph 600 that shows the "normally-on" forward characteristics integrated VJFET/JBSD device. Graph 600 shows the drain voltage (X-axis) and the drain current (Y-axis). As shown in graph 600, if VAS = 0, the device is turned "on" and as the drain voltage (VDs) increases from 0 to approximately 3.6 volts, the drain current increases from zero to 2 X 105 A/pm. As VAS is decreases from , for example, - 2V to - 6V, even though the drain voltage increases, the drain current decreases drastically, as shown in Figure 6. As the VGs reaches the "pinch off voltage, the drain current is almost zero and the integrated VJFET/JBSD device is turned off.

[0020] Figure 7 illustrates a method for fabricating an integrated VJFET/JBSD device, such as the device 200. Although the description below is provided for an N-type device, the process and techniques described herein may also be applied to a P-type device by replacing the N-type material with P-type material, P-type material with N-type material, and by reversing the electrode polarities. An underlying semiconductor substrate 710 containing silicon (Si), SiC, other material, or any combination thereof, may be used for the integrated VJFET/JBSD device. The substrate 710 may include a top layer, for source contacts, that may be doped with a higher carrier concentration. For example, for a N-type device, the top layer is a N+ source contact layer. However, for a P-type device, the top layer is a P+ source contact layer. As shown in Figure 7(a), masks 720 and 721 are patterned and source pillars 715, 716 are etched into the substrate 710. The N+ source contact layer 711 remains for the source pillars 715 and 716 but is removed for both the p+ regions and the Schottky region.

[0021] As shown in Figure 7(b), an additional mask 722 is patterned on the substrate 710. An ion-implantation is performed to create all P+ regions 731, 732, 733 and 734, as shown in Figure 7(c), for the N-type device. The spacing between the P+ regions P1, P2, and P3, can typically range from 0.5 to 10 micrometers. The ion-implantation may be a single implantation or may include multiple implantations. Alternate approaches to creating the P-type gate regions include diffusion and epitaxial regrowth. For a P-type device, an ion-implantation is performed to create N+ regions. A metallization and interconnect process is used to create the gate, source and drain contacts. Ohmic gate contacts 735, 736, 737, and 738 are formed on the P+ regions 731, 732, 733 and 734, as shown in Figure 7(d). Schottky gate regions 741, 744 and 743 are then formed to make Schottky contacts to the semiconductor channel and ohmic contacts to the p+ gates 735, 736, 737, and 738. These regions are connected together outside of the plane of the figure to form a single gate contact for the integrated VJFET/JBSD device. An insulator 780 is deposited over the gate contacts 741, 744 and 743. Source contact 760 are then formed for the integrated VJFET/JBSD device. The drain contact 770 is also formed for the device.

[0022] The integrated VJFET/JBSD device, as shown in Figure 7(d), includes a first VJFET 750, a JBS diode 751 and a second VJFET 770. The Schottky contact 744 for the JBS diode is formed by omitting the ohmic contact that exists on the P+ regions 732, 733 surrounding the Schottky contact 744.

[0023] Figure 8 illustrates an integrated VJFET/JBSD device having a planar (non-recessed) gate structure. As shown, the gates 81 and 82 are planar to the sources 87, 88 and offer the features of the integrated VJFET/JBSD devices (described above).

[0024] Figure 9 illustrates an integrated VJFET/JBSD device having a buried-gate structure (e.g., gates 91, 92, 93 and 94 are buried).

[0025] Figure 10 illustrates an integrated VJFET/JBSD device having a lateral JFET structure.

[0026] A VJFET with Schottky gates may be integrated with and a "dual-metal" Schottky diode as illustrated Figure 11. A high-barrier Schottky (HBS) metal is used as the gates 11, 12, 13 and 14 of the VJFET and the shielding regions of the diode, and a low-barrier Schottky (LBS) metal is used as the main contact 15 of the diode.

[0027] Figure 12 illustrates a dual-gated integrated VJFET/JBSD device 800, in accordance with an embodiment. The dual-gated integrated VJFET/JBSD device 800 is configured to include two sets of gates, an upper gate to control the "normally-off' position and a lower gate to control the "normally-on" position.

[0028] In the dual gated integrated VJFET/JBSD device, shown in Figure 12, the first VJFET, VJFET 801 includes a source 818 and a N+ source region 817. A first channel 830 is disposed under the source 817, as shown. The first N-channel 830 separates upper gates including first gate 813 and an P+ implant 820, from second gate 814 and P+ implant 821. VJFET 801 includes a first N-drift region 840. The first VJFET 801 also includes a first set of lower gates including first gate 871 and an P+ implant 870 and second gate 876 and P+ implant 875. The lower gates are separated by a second N-channel 835. The second n-channel 835 is disposed on a second N- drift region 841, which is disposed on a N+ buffer/substrate 850. The N+ buffer/substrate 850 is connected to a drain 860 of the dual-gated integrated VJFET/JBSD device 800.

[0029] As shown in Figure 12, the second VJFET 803 includes a source 818 common with the VJFET 801 and a N+ source region 810. The second N-channel 831, is disposed under the N+ source region 810, as shown. The second N-channel 830 separates upper gates including first gate 815 and an P+ implant 822, from second gate 816 and P+ implant 823. Second VJFET 803 has a N- drift region 843, as shown. The second VJFET 803 also includes a second set of lower gates including first gate 877 and an P+ implant 878 and second gate 874 and P+ implant 879. The lower gates are separated by the second N-channel 835. The second n-channel 835 is disposed on the second N-drift region 841, which is disposed on the N+ buffer/substrate 850. The N+ buffer/substrate 850 is coupled to the drain 860 of the dual-gated integrated VJFET/JBSD device 800.

[0030] In accordance with the invention, the dual-gated integrated VJFET/JBSD device 800 is configured to include two sets of gates, upper gates 813, 814, 815 and 816 to control the "normally-off' position and lower gates 871, 876, 877 and 874 to control the "normally-on" position. Due to the small spacing between the upper gates (i.e., gates 820 and 821, and 822 and 823), the built-in depletion regions will pinch-off the channels 830, 831 with no applied bias between gate and source (i.e., VAS = 0 V). In this case, the upper gates provide a device 800 which is "normally-off." A positive voltage VAS must be applied to the gate to reduce the built-in depletion region and turn the device 800 "on." The common source 818, which may be a interconnect metal, is used to connect the sources of the VJFETs 801, 803, as shown. The common source 818 is insulated from upper gates by an insulator 891, 892, 893 and 894.

[0031] The lower gates 871, 876, 877 and 874 provide a normally "on" device. The larger spacing between the P+ gate regions 870 and 875, and 878 and 879 permit a current to flow through the second N-channel 835, between the gate regions, at VAS = 0 V. The lower gates are connected to the sources through source contact 818. If the upper normally-off portion of the devices are in the "off' state and the drain-source voltage (VDS) is positive, a negative voltage will appear between the second n-channel 835 and the lower gates 871, 876, 877, and 874. This switches the lower normally-on portion of the devices off. If the upper "normally-off portion of the devices are in the "on" state", current will flow through both portions of the device and the combined switch is "on". The dual-gate device 800 advantageously connects a normally-off VJFET and normally-on VJFET in cascode configuration in a single device, thus reducing the cost and complexity of the circuit.

[0032] As shown in Figure 12, the Schottky contact 880 makes a Schottky (rectifying) contact to the lower semiconductor channel 835 and ohmic contacts to the lower gates 871, 876, 877 and 874. The JBS diode 802 is formed on a substrate that includes the second N- drift layer 841, N+ buffer/substrate 850 and drain 860. In this manner, three devices (normally-off VJFET, normally-on VJFET, and anti-parallel JBS diode) are combined into a single device, reducing the cost and complexity of the power conditioning circuits.

[0033] Although the integrated VJFET/JBSD devices, as shown in the figures and described herein, only show two source/gate sets, an integrated VJFET/JBSD device may be configured to include hundreds or thousands or repeating gate/source connections for a device with high currents.

[0034] In a high-power transistor containing many sets of sources and gates, the VJFET/JBSD can be integrated in two different ways. The first method is to interdigitate a JBS diode finger in between every VJFET finger. For high-voltage devices, this method of integration should not significantly reduce either device's performance. For high-voltage majority-carrier devices, the drift region is typically thick (10-100 pm) and lightly doped (1014-1015 cm-3) and dominates the "on" state resistance. As a result, a lower density of fingers for both the VJFET and JBS diode may be able to be accommodated without significantly increasing the resistance of either device. This allows the integration of two high performance devices in the same area as one. The second method is to form separate groups of VJFET fingers and JBS diode fingers, all within the same edge termination, but not interdigitated. This will require more area than the interdigitated approach to achieve the same performance, but may have advantages regarding interconnecting the fingers to bond pads.

[0035] In an alternate embodiment, the ohmic contacts to the P+ gates of the VJFET could be omitted from the structure. The Schottky contact would then be used to contact both the semiconductor channel of the JBS diode and the p+ gates of the VJFETs. This will not alter the pinch-off voltage of the normally on device appreciably. The gate-source pinch-off voltage is typically -20 V. Due to the Schottky junction at the P+ gate contact, an additional 1 V drop may be introduced, lowering it to -21 V. This should not have much effect on the cascode circuit.

[0036] Figure 13 illustrates an improved recovery surge current capable rectifier 900 with an N-resistive layer 930 and epitaxial P anode pillars 940-942. As shown, the improved recovery rectifier 900 may be fabricated on a N substrate 910, such as SiC. The improved recovery rectifier 900 includes a N- drift layer 920 and a N-resistive layer 930. The improved recovery rectifier 900 includes P anode pillars 940, 941 and 942 fabricated on the N- resistive layer 930. The P anode pillars 940, 941 and 942 include ohmic contacts 950, 951 and 952, respectively. The ohmic contacts allow low resistance access to the P anode pillars. The ohmic contacts may provide a linear and symmetric current-voltage (I-V) characteristic for the contact. The ohmic contacts may be sputtered or evaporated metal pads that are patterned using photolithography.

[0037] The P anode pillars 940, 941 and 942 are fabricated using an epitaxial process. As shown, Schottky contacts 961 and 962 are deposited on the N-resistive layer 930 between the P anode pillars 940, 941 and 942, as shown. The Schottky contacts 961 and 962 may provide a Schottky barrier (rectifying contact), where the junction conducts for one bias polarity, but not the other. The Schottky diode may provide non-linear and asymmetric I-V characteristics for the contact. The N-resistive layer 930 is added to the improved recovery rectifier 900 to cause the PN junction (junction at P anode and the N- resistive layer) of the device to turn "on" at lower voltages, thus reducing on-resistance of the device.

[0038] Figure 14 illustrates another example of an improved recovery surge current capable rectifier 1000 with an N-resistive layer 1030 and P anode implants 1040-1042. The P anode implants 1040-1042 are implanted in the N-resistive layer 1030. As shown, the improved recovery rectifier 1000 may be fabricated on a N substrate 1010, such as SiC. The rectifier 1000 includes a N-drift layer 1020 and a N- resistive layer 1030. The P anode regions 1040, 1041 and 1042, implanted in the N- resistive layer, that include ohmic contacts 1050, 1051 and 1052, respectively. The ohmic contacts allow low resistance access to the P anode implants. The ohmic contacts may provide a linear and symmetric current-voltage (I-V) characteristic for the contact.

[0039] The P anode regions 1040, 1041 and 1042 are implanted into the N-resistive layer 1030. As shown, Schottky contacts 1061 and 1062 are deposited on the N-resistive layer 1030 between the P anode implant regions 1040, 1041 and 1042. The Schottky contacts 1061 and 1062 may provide a Schottky barrier (rectifying contact), where the junction conducts for one bias polarity, but not the other. The Schottky diode may provide non-linear and asymmetric I-V characteristics for the contact. The N- resistive layer 1030 is added to the rectifier 1000 to cause the PN junction (junction at P anode and the N- resistive layer) of the device to turn "on" at lower voltages, thus reducing on-resistance of the device.

[0040] Figure 15 shows graph 1100 depicting numerical modeling results of an epitaxial rectifier (e.g., rectifier 900) with an N- resistive layer to activate the PN junction. The X-axis shows the rectifier's forward biased voltage (V) and the Y-axis shows rectifier's current (A/pm). In these simulations, the N- layer (e.g., 930) was fixed at approximately 4 pm thick (T), the P anode pillars (e.g., 940, 941, and 941) were fixed at approximately 10 pm in width (W1), and the Schottky contact (e.g., 961 and 962) was approximately 3 pm wide (W2). Graph 1100, shows three curves showing the various dopings of the N- resistive layer. The PN junction of rectifier turns on at lower voltages as the resistivity of the N- layer increases. Therefore, the PN junction turn-on can be tailored by adjusting the N-layer doping, depth, and P anode spacing for a given N- layer resistive layer doping. For example, curve 1110 shows a doping of 1 X 1014/cm3, curve 1120 shows a doping of 2 X 1014/cm3, and curve 1130 shows a doping of 3 X 1014/cm3. As can be seen by the graph 1100, at a doping of 1 X 1014/cm3, the PN junction will turn "on" at a voltage of approximately 4 volts (data point 1111). As the N-resistive layer doping levels are increased, the turn-on voltage for the PN junction also increases. Data points 1111, 1121 and 1131 represent the current through the ohmic contacts since the ohmic contacts require greater turn-on voltages. Thus, adjusting the various parameters and providing a N- resistive layer helps to increase the voltage drop across the pn junction, hence the pn junction turn-on voltage can be lowered to turn on at a specific forward voltage across the rectifier and reduce the on-resistance of the device. The doping of the N- resistive layer may range up to the doping of the N-drift layer. Applications requiring surge current, e.g., for system start-up conditions, require that the p-n junctions turn on to inject minority carriers, thus drastically lower the forward on-resistance at the desired forward voltage. The Schottky contact can act as a recombination source for minority carrier holes during reverse recovery, thus speeding up the turn off process. Tailoring the low-doped resistive layer 930 or 1030 allows for the surge current to occur only under stress conditions and not during normal operation.

[0041] In an example of the rectifier 900 and rectifier 1000, the thickness T of the N- resistive layer may range from 0.2 to 5 micron meters in thickness, the width (W1) of the P anode pillars may range from .5 to 12 micron meters, and/or the width (W2) of the Schottky contact may range from .5 to 8 micron meters in width.

[0042] Figure 16 illustrates a vertical channel trenched structure insulated gate bipolar device (IGBT) 1200 configured using Si. By using a trench gate structure and controlling the pitch of the cell, enhanced injection in the IGBT base may be produced. The enhanced injection reduces on-states losses without dramatic increases in switching losses in an IGBT. The vertical channel trenched structure insulated gate bipolar device (IGBT) 1200 includes a collector terminal (or anode) 1210, a P emitter region 1220, a N base 1230, a pair of vertical trenched gates 1240, 1241, a P base 1270, a N source 1260 and an emitter terminal (or cathode) 1250. The gates 1240 and 1241 may be coupled with each other. Optionally, one of the gates 1240 and 1241 may be coupled to the emitter terminal 1250.

[0043] In the vertical channel IGBT 1220, if a positive voltage is applied to the vertical gates 1240, 1241, with respect to the emitter terminal 1250, a inversion layer (N channel) 1271 is formed in the P-type region between the pair of vertical gates 1240, 1241. The applied voltage creates channels, adjacent to the vertical gates 1240, 1241, in which electrons flow downwards away from the cathode in the inversion layer and holes flow up through the P base. This results in a low resistance region for the electrons in the channels 1240 and a large potential drop is created in the region between the channels 1240 for the holes to travel. Also, the structure provides no "JFET" resistance as in traditional DMOS (Double Diffused Metal Oxide Semiconductor) structures.

[0044] A conventional planar IGBT is a bipolar device that utilizes conductivity modulation in the thick drift region. During reverse blocking, the layer thickness and doping must be low enough to allow the blocking voltage to be dropped across the drift region. The low carrier concentration and the thick base layer of an IGBT is modulated by minority carriers (holes), injected from the lower p+ emitter region. The injected hole density in the N base can be very high (orders of magnitude higher than the background N type dopant density) and will effectively lower the on-state resistance. In silicon IGBTs, the design of the MOS channel can greatly effect the charge concentration in the base of the IGBT during the on-state. It has been found that making the P-body implant in an N-channel IGBT wide and deep or developing deep trench gate structures create a raised potential across the MOS channel. The raised potential results in increased electron current from the channel and results in the piling up of current on the emitter terminal 1250 or cathode. The result is a decrease in the base resistance (due to an increase in the base charge concentration) of the IGBT, without much increase in switching losses. In silicon, the dopants are diffused to construct the channel region, since the dopant diffusion rate in Si is high. Also, the material quality in Si is such that a MOS channel is easily produced that yields a high inversion layer mobility.

[0045] Moreover, in silicon carbide, the P well region of an IGBT is implanted using ion implantation. The diffusion coefficients in SiC are very low, and hence the dopants, for all practical purposes, do not diffuse. Therefore, the depth of the P well in SiC is limited to 1 micron or less. This limits the effectiveness of the planar device injection enhancement structure of a conventional IGBT. Furthermore, since the dopants must be implanted to the maximum depth of -1 micron in the SiC IGBT structure to prevent latch-up, the channel region is highly damaged, dramatically reducing the inversion layer mobility.

[0046] As descried herein, an injection enhanced IGBT is provided using an epitaxial P layer to form the channel layer. The epitaxial P layer (16) provides a much higher inversion layer mobility as compared to an implanted channel region (17, 18), as shown in Figure 17. Furthermore, the tight channel width is used to create a higher potential drop across the channel due to crowding of the hole current. As stated above, the crowding of the hole current increases the minority carrier concentration in the base, and hence reduces the on-state voltage drop across the IGBT.

[0047] Figure 18 illustrates device epitaxial layers needed to develop a SiC epitaxial injection enhanced IGBT device having a vertical channel trenched structure. Due to the lack of a highly conductive P type substrate in SiC, the epitaxial layer can be grown on an N-type substrate 1300. The N substrate can be lapped away to make a backside (anode) contact to the P type emitter epitaxial layer 1310. The P type emitter epitaxial layer 1310 is deposited with an N- base epitaxial layer 1320, which is deposited with a P type collector or metal oxide semiconductor (MOS) channel epitaxial layer 1330. A N+ MOS source contact epitaxial layer 1340 is deposited on layer 1330, as shown. In addition, the epitaxial layers can be grown in reverse order with the P injecting layer on top, and the substrate lapped away. The wafer may be flipped over, and the MOS portion of the IGBT can then be developed on the C-face, as is known.

[0048] Figure 19 illustrates several IGBT technologies (e.g., non punch-through, punch-through, and field-stop IGBTs) implemented in SiC with epitaxial layers for injection enhancement. The non punch-through 1400, punch-through 1450, and field-stop IGBTs 1451, respectively, demonstrate trench gate injection enhanced IGBT structure using epitaxial P channel layer. Each IGBT technology has tradeoffs of on-state versus switching losses, yielding application specific devices. The present disclosure can be implemented to further reduce the on-state losses for each technology.

[0049] Figure 19 shows a non-punch through trench gate IGBT structure 1400. The non-punch through trench gate IGBT 1400 includes an anode 1401, a P type emitter epitaxial layer 1402, a N- base epitaxial layer 1403, a MOS channel epitaxial layer 1404, poly silicon gate 1405, gate oxide 1406, cathode 1407 and N source contacts 1408. The devices shown in Figure 19 may be created using SiC.

[0050] Figure 19 shows a punch-through trench gate IGBT structure 1450, which is similar to the non-punch through trench gate IGBT structure 1400 but includes a N buffer punch-through epitaxial layer 1409. The punch-through epitaxial layer 1409 provides a thinner more lowly doped drift layer in order to decrease the slope of the electric field profile under reverse bias. This enables a trade-off in lowering the on-state resistance and the switching speed.

[0051] Further illustrated in Figure 19 is a field-stop IGBT structure 1451 which is similar to the non-punch through trench gate IGBT structure 1400 but includes a N field stop epitaxial layer 1410. The N field stop epitaxial layer 1410 provides a decrease in the amount of charge in the P injecting layer. This decrease results in a decrease in injected charge in the IGBT drift layer during forward bias. Therefore, the switching losses in the IGBT are reduced by having the minimal amount of electron-hole plasma to distinguish at turn-off.

[0052] When a positive voltage is applied to the gate of the device, the IGBT structures 1400, 1450 and 1451 create vertical channels 1415 in the MOS region 1404 to generate increased potential or bias for holes to travel through the MOS region 1404. The P region 1404 may be between .1 to 3 micron meters (pm) in width (W). When a positive voltage is applied to the gate of the device 1400, 1450 or 1451, a inversion layer 1415 is formed in the P region 1404, in which electrons flow downwards away from the cathode 1407 and N source 1408. Holes then flow upwards towards the cathode 1407 in the region between channels 1415. The depletion regions of the vertical channels 1415 are pushed together, creating a large potential drop for the holes to travel. This large potential drop results in an increase in the hole concentration in the drift region, which reduces the on-state losses for the device structures 1400, 1450, and 1451.

[0053] Although Figures 18 and 19 and the above description apply to a N type IGBT, a similar configuration may be achieved for a P type IGBT by reversing the polarities of the dopants.

[0054] Figures 20 illustrates a non-punch through trench gate IGBT, as shown in Figure 19, with P implants 1505 to shield the gate oxide 1406. Figures 20 illustrates a non-punch through trench gate IGBT, as shown in Figure 19, with P implant 1605 to shield the gate oxide 1606. Figure 21 shows the shield oxide 1606 with and without the P implants. Under reverse bias stress, the gate oxide 1406 can see significant electric fields. In order to prevent the gate oxide from experiencing high electric fields, the P implants, such as implants 1505 and 1605 can be placed at high electric field points, thus reducing the electric fields in the oxide.

[0055] An embodiment of the present invention is specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the present invention are covered by the above teachings and within the purview of the appended claims without departing from the intended scope of the invention.


Claims

1. A dual gated integrated device, comprising:

a first vertical junction field-effect transistor, VJFET (801), wherein the first VJFET comprises:

a first VJFET source (817);

a pair of first upper gates (820, 821) disposed on each side of the first VJFET source;

a first upper N channel (830) disposed between the pair of first upper gates;

a first N- drift region (840) disposed adjacent to the first upper N channel; and

a first pair of lower gates (870, 875) of the first VJFET in a lower N channel (835);

a second VJFET (803), wherein the second VJFET comprises:

a second VJFET source (810);

a pair of second upper gates (822, 823) disposed on each side of the second VJFET source, wherein a second upper N channel (831) is disposed between the pair of second upper gates; and

a second pair of lower gates (878, 879) of the second VJFET in the lower N channel;

a Schottky contact (880, 876, 877), wherein the Schottky contact couples the first pair of lower gates of the first VJFET to the second pair of lower gates of the second VJFET wherein the lower N channel (835) separates at least one gate (876) of the first VJFET from at least one gate (877) of the second VJFET, wherein the Schottky contact forms a rectifying contact to the lower N channel (835), and forms ohmic, non-rectifying contacts to the first pair of lower gates (870, 875) of the first VJFET and the second pair of lower gates (878, 879) of the second VJFET; and

a common source (818) connected to the first VJFET source (817) and the second VJFET source (810), and wherein the common source is insulated from the first upper gates (820, 821) of the first VJFET and the second upper gates (822, 823) of the second VJFET by an insulator (891, 892, 893, 894), and the common source is connected to the first and second pairs of lower gates.


 
2. The dual gated integrated device of claim 1, wherein the first pair of lower gates (870, 875) of the first VJFET and the second pair of lower gates (878, 879) of the second VJFET provide a normally on device.
 
3. The dual gated integrated device of claim 1, wherein the first upper gates (820, 821) of the first VJFET and the second upper gates (822, 823) of the second VJFET provide a normally off device.
 
4. The dual gated integrated device of claim 1, wherein the Schottky contact is an anode of a JBS diode.
 
5. The dual gated integrated device of claim 1, wherein the Schottky contact is a metal contact.
 


Ansprüche

1. Integrierte Dual-Gate-Vorrichtung, umfassend:

einen ersten Vertikalsperrschicht-Feldeffekttransistor, VJFET (801), wobei der erste VJFET Folgendes umfasst:

eine erste VJFET-Source (817);

ein Paar erster oberer Gates (820, 821), die auf jeder Seite der ersten VJFET-Source angeordnet sind;

einen ersten oberen N-Kanal (830), der zwischen dem Paar erster oberer Gates angeordnet ist;

eine erste N--Drift-Region (840), die neben dem ersten oberen N-Kanal angeordnet ist; und

ein erstes Paar unterer Gates (870, 875) des ersten VJFET in einem unteren N-Kanal (835);

einen zweiten VJFET (803), wobei der zweite VJFET Folgendes umfasst:

eine zweite VJFET-Source (810);

ein Paar zweiter oberer Gates (822, 823), die auf jeder Seite der zweiten VJFET-Source angeordnet sind, wobei ein zweiter oberer N-Kanal (831) zwischen dem Paar zweiter oberer Gates angeordnet ist; und

ein zweites Paar unterer Gates (878, 879) des zweiten VJFET in dem unteren N-Kanal;

einen Schottky-Kontakt (880, 876, 877), wobei der Schottky-Kontakt das erste Paar unterer Gates des ersten VJFET mit dem zweiten Paar unterer Gates des zweiten VJFET koppelt, wobei der untere N-Kanal (835) mindestens ein Gate (876) des ersten VJFET von mindestens einem Gate (877) des zweiten VJFET trennt, wobei der Schottky-Kontakt einen Gleichrichterkontakt mit dem unteren N-Kanal (835) bildet und ohmsche Nicht-Gleichrichterkontakte mit dem ersten Paar unterer Gates (870, 875) des ersten VJFET und dem zweiten Paar unterer Gates (878, 879) des zweiten VJFET bildet; und

eine gemeinsame Source (818), die mit der ersten VJFET-Source (817) und der zweiten VJFET-Source (810) verbunden ist, und wobei die gemeinsame Source von den ersten oberen Gates (820, 821) des ersten VJFET und den zweiten oberen Gates (822, 823) des zweiten VJFET durch einen Isolator (891, 892, 893, 894) isoliert ist und die gemeinsame Source mit dem ersten und zweiten Paar unterer Gates verbunden ist.


 
2. Integrierte Dual-Gate-Vorrichtung nach Anspruch 1, wobei das erste Paar unterer Gates (870, 875) des ersten VJFET und das zweite Paar unterer Gates (878, 879) des zweiten VJFET eine selbstleitende Vorrichtung bereitstellen.
 
3. Integrierte Dual-Gate-Vorrichtung nach Anspruch 1, wobei die ersten oberen Gates (820, 821) des ersten VJFET und die zweiten oberen Gates (822, 823) des zweiten VJFET eine selbstsperrende Vorrichtung bereitstellen.
 
4. Integrierte Dual-Gate-Vorrichtung nach Anspruch 1, wobei der Schottky-Kontakt eine Anode einer JBS-Diode ist.
 
5. Integrierte Dual-Gate-Vorrichtung nach Anspruch 1, wobei der Schottky-Kontakt ein Metallkontakt ist.
 


Revendications

1. Dispositif intégré à double grille, comprenant :

un premier transistor à effet de champ à jonction verticale, VJFET (801), le premier VJFET comprenant :

une source de premier VJFET (817) ;

une paire de premières grilles supérieures (820, 821) disposées de part et d'autre de la source de premier VJFET ;

un premier canal N supérieur (830) disposé entre la paire de premières grilles supérieures ;

une première région de gradient de champ N- (840) disposée adjacente au premier canal N supérieur ; et

une première paire de grilles inférieures (870, 875) du premier VJFET dans un canal N inférieur (835) ;

un second VJFET (803), le second VJFET comprenant :

une source de second VJFET (810) ;

une paire de secondes grilles supérieures (822, 823) disposées de part et d'autre de la source de second VJFET, un second canal N supérieur (831) étant disposé entre la paire de secondes grilles supérieures ; et

une seconde paire de grilles inférieures (878, 879) du second VJFET dans le canal N inférieur ;

un contact Schottky (880, 876, 877), le contact Schottky couplant la première paire de grilles inférieures du premier VJFET avec la seconde paire de grilles inférieures du second VJFET, le canal N inférieur (835) séparant au moins une grille (876) du premier VJFET d'au moins une grille (877) du second VJFET, le contact Schottky formant un contact de rectification vers le canal N inférieur (835), et formant des contacts ohmiques, sans rectification vers la première paire de grilles inférieures (870, 875) du premier VJFET et la seconde paire de grilles inférieures (878, 879) du second VJFET ; et

une source commune (818) reliée à la source de premier VJFET (817) et la source de second VJFET (810), la source commune étant isolée des premières grilles supérieures (820, 821) du premier VJFET et des secondes grilles supérieures (822, 823) du second VJFET par un isolant (891, 892, 893, 894), et la source commune étant reliée aux première et seconde paires de grilles inférieures.


 
2. Dispositif intégré à double grille selon la revendication 1, la première paire de grilles inférieures (870, 875) du premier VJFET et la seconde paire de grilles inférieures (878, 879) du second VJFET fournissant un dispositif normalement ouvert.
 
3. Dispositif intégré à double grille selon la revendication 1, les premières grilles supérieures (820, 821) du premier VJFET et les secondes grilles supérieures (822, 823) du second VJFET fournissant un dispositif normalement fermé.
 
4. Dispositif intégré à double grille selon la revendication 1, le contact Schottky étant une anode d'une diode JBS.
 
5. Dispositif intégré à double grille selon la revendication 1, le contact Schottky étant un contact métallique.
 




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REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description




Non-patent literature cited in the description