(19)
(11)EP 2 259 315 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
19.02.2014 Bulletin 2014/08

(21)Application number: 10005813.0

(22)Date of filing:  04.06.2010
(51)International Patent Classification (IPC): 
H01L 27/11(2006.01)
H01L 21/8244(2006.01)

(54)

Semiconductor device

Halbleiterbauelement

Dispositif semi-conducteur


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

(30)Priority: 05.06.2009 JP 2009135754

(43)Date of publication of application:
08.12.2010 Bulletin 2010/49

(73)Proprietor: Unisantis Electronics Singapore Pte. Ltd.
Singapore 179098 (SG)

(72)Inventors:
  • Masuoka, Fujio
    Tokyo-104-0033 (JP)
  • Nakamura, Hiroki
    Tokyo104-0033 (JP)

(74)Representative: Röthinger, Rainer 
Wuesthoff & Wuesthoff Patent- und Rechtsanwälte Schweigerstrasse 2
81541 München
81541 München (DE)


(56)References cited: : 
EP-B1- 0 334 927
JP-A- 2008 205 168
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The present invention relates to a semiconductor device.

    [0002] A degree of integration in a semiconductor device, particularly in an integrated circuit using a MOS transistor, has been increasing year by year. Along with the increase in the degree of integration, miniaturization of the MOS transistor used therein has progressed to a nano region. The progress in miniaturization of the MOS transistor, which constitutes an inverter circuit as a basic circuit for digital circuits, gives rise to a problem, such as difficulty in suppressing a leak current, which causes deterioration in reliability due to hot carrier effects and poses an impediment to sufficiently reducing a circuit occupancy area while meeting a requirement of ensuring a necessary current magnitude. With a view to solving this problem, there have been proposed a surrounding gate transistor (SGT) having a structure in which a source, a gate and a drain are arranged in a direction perpendicular to a substrate, wherein the gate is formed to surround an island-shaped semiconductor layer, and a CMOS inverter circuit using the SGT (see, for example, S. Watanabe, K. Tsuchida, D. Takashima, Y Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, "A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's," IEEE JSSC, Vol. 30, No. 9, 1995).

    [0003] An inverter is constructed using a pMOS transistor and an nMOS transistor. In an inverter circuit, a gate width of a pMOS transistor has to be set to be twice as large as that of an nMOS transistor, because a hole mobility is one-half of an electron mobility. Therefore, a conventional CMOS inverter circuit using an SGT (SGT CMOS inverter circuit) is composed of two pMOS SGTs and one nMOS SGT. In other words, the conventional SGT CMOS inverter circuit is composed of total three island-shaped semiconductors.

    [0004] An SRAM is composed of two inverters and two selection transistors. In cases where an SRAM is constructed using the conventional SGT CMOS inverter circuit, it is composed of four pMOS and four nMOS. In other words, the SRAM using the conventional SGT CMOS inverter circuit is composed of total eight island-shaped semiconductors.

    [0005] JP 2008205168 describes a SRAM comprising transistors in cylinder shape.

    [0006] It is therefore an object of the present invention to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0007] In order to achieve this object, according to a first aspect of the present invention, there is provided a semiconductor device according to claim 1.

    [0008] According to a second aspect of the present invention, there is provided a semiconductor device as defined in the first aspect of the present invention, which is further characterized in that the first gate dielectric film is surrounding a periphery of the first island-shaped semiconductor layer, the first gate electrode is surrounding a periphery of the first gate dielectric film, the third gate dielectric film is surrounding a periphery of the second island-shaped semiconductor layer, the second gate electrode is surrounding a periphery of the third gate dielectric film, the fifth gate dielectric film is surrounding a periphery of the third island-shaped semiconductor layer, the third gate electrode is surrounding a periphery of the fifth gate dielectric film, the sixth gate dielectric film is surrounding a periphery of the fourth island-shaped semiconductor layer, and the fourth gate electrode is surrounding a periphery of the sixth gate dielectric film.

    [0009] According to a third aspect of the present invention, there is provided a semiconductor device as defined in the second aspect of the present invention, which is further characterized by comprising a fifth first-conductive-type high-concentration semiconductor layer arranged underneath the second first-conductive-type high-concentration semiconductor layer, the second second-conductive-type high-concentration semiconductor layer and the eighth second-conductive-type high-concentration semiconductor layer; a sixth first-conductive-type high-concentration semiconductor layer arranged underneath the fourth first-conductive-type high-concentration semiconductor layer, the fourth second-conductive-type high-concentration semiconductor layer and the sixth second-conductive-type high-concentration semiconductor layer; a first semiconductor-metal compound layer formed on a part of respective sidewalls of the second second-conductive-type high-concentration semiconductor layer and the fifth first-conductive-type high-concentration semiconductor layer; a second semiconductor-metal compound layer formed on the eighth second-conductive-type high-concentration semiconductor layer and the fifth first-conductive-type high-concentration semiconductor layer; a third semiconductor-metal compound layer formed on a part of respective sidewalls of the fourth second-conductive-type high-concentration semiconductor layer and the sixth first-conductive-type high-concentration semiconductor layer; a fourth semiconductor-metal compound layer formed on the sixth second-conductive-type high-concentration semiconductor layer and the sixth first-conductive-type high-concentration semiconductor layer; a fifth semiconductor-metal compound layer formed on the first first-conductive-type high-concentration semiconductor layer; a sixth semiconductor-metal compound layer formed on the first second-conductive-type high-concentration semiconductor layer; a seventh semiconductor-metal compound layer formed on the third first-conductive-type high-concentration semiconductor layer; an eighth semiconductor-metal compound layer formed on the third second-conductive-type high-concentration semiconductor layer; a ninth semiconductor-metal compound layer formed on the fifth second-conductive-type high-concentration semiconductor layer; a tenth semiconductor-metal compound layer formed on the seventh second-conductive-type high-concentration semiconductor layer; a first contact connecting the first gate electrode and the fourth semiconductor-metal compound layer; and a second contact connecting the second gate electrode and the second semiconductor-metal compound layer.

    [0010] According to a fourth aspect of the present invention, there is provided a semiconductor device as defined in the second aspect of the present invention, further characterized in that the first first-conductive-type high-concentration semiconductor layer is a first p+-type semiconductor layer, the second first-conductive-type high-concentration semiconductor layer is a second p+-type semiconductor layer, the first second-conductive-type high-concentration semiconductor layer is a first n+-type semiconductor layer, the second second-conductive-type high-concentration semiconductor layer is a second n+-type semiconductor layer, the third first-conductive-type high-concentration semiconductor layer is a third p+-type semiconductor layer, the fourth first-conductive-type high-concentration semiconductor layer is a fourth p+-type semiconductor layer, the third second-conductive-type high-concentration semiconductor layer is a third n+-type semiconductor layer, the fourth second-conductive-type high-concentration semiconductor layer is a fourth n+-type semiconductor layer, the fifth second-conductive-type high-concentration semiconductor layer is a fifth n+-type semiconductor layer, the sixth second-conductive-type high-concentration semiconductor layer is a sixth n+-type semiconductor layer, the seventh second-conductive-type high-concentration semiconductor layer is a seventh n+-type semiconductor layer, and the eighth second-conductive-type high-concentration semiconductor layer is an eighth n+-type semiconductor layer

    [0011] According to a fifth aspect of the present invention, there is provided a semiconductor device as defined in the fourth aspect of the present invention, which is further characterized by comprising a fifth p+-type semiconductor layer arranged underneath the second p+-type semiconductor layer, the second n+-type semiconductor layer and the eighth n+-type semiconductor layer; a sixth p+-type semiconductor layer arranged underneath the fourth p+-type semiconductor layer, the fourth n+-type semiconductor layer and the sixth n+-type semiconductor layer; a first semiconductor-metal compound layer formed on a part of respective sidewalls of the second n+-type semiconductor layer and the fifth p+-type semiconductor layer; a second semiconductor-metal compound layer formed on the eighth n+-type semiconductor layer and the fifth p+-type semiconductor layer; a third semiconductor-metal compound layer formed on a part of respective sidewalls of the fourth n+-type semiconductor layer and the sixth p+-type semiconductor layer;
    a fourth semiconductor-metal compound layer formed on the sixth n+-type semiconductor layer and the sixth p+-type semiconductor layer; a fifth semiconductor-metal compound layer formed on the first p+-type semiconductor layer; a sixth semiconductor-metal compound layer formed on the first n+-type semiconductor layer; a seventh semiconductor-metal compound layer formed on the third p+-type semiconductor layer; an eighth semiconductor-metal compound layer formed on the third n+-type semiconductor layer; a ninth semiconductor-metal compound layer formed on the fifth n+-type semiconductor layer; a tenth semiconductor-metal compound layer formed on the seventh n+-type semiconductor layer; a first contact connecting the first gate electrode and the fourth semiconductor-metal compound layer; and a second contact connecting the second gate electrode and the second semiconductor-metal compound layer.

    [0012] Preferably, the semiconductor device of the present invention is configured to satisfy the following condition: Wp1 ≈ 2Wn1, wherein Wp1 is an outer peripheral length of the first island-shaped semiconductor layer, and Wn1 is a length of an arc of the first arc-shaped semiconductor layer in contact with a part of the periphery of the second gate dielectric film.

    [0013] Preferably, the semiconductor device of the present invention is configured to satisfy the following condition: Wp2 ≈ 2Wn2, wherein Wp2 is an outer peripheral length of the second island-shaped semiconductor layer, and Wn2 is a length of an arc of the second arc-shaped semiconductor layer in contact with a part of the periphery of the fourth gate dielectric film.

    [0014] Preferably, the semiconductor device of the present invention is configured to satisfy the following condition: Ln1 ≈ Lp1, wherein Ln1 is a channel length of the first arc-shaped semiconductor layer, and Lp1 is a channel length of the first island-shaped semiconductor layer.

    [0015] Preferably, the semiconductor device of the present invention is configured to satisfy the following condition: Ln2 ≈ Lp2, wherein Ln2 is a channel length of the second arc-shaped semiconductor layer, and Lp2 is a channel length of the second island-shaped semiconductor layer.

    [0016] Preferably, in the semiconductor device of the present invention, a first pMOS transistor, a first nMOS transistor, a second pMOS transistor and a second nMOS transistor are made up of a combination of the first island-shaped semiconductor layer, the first gate dielectric film surrounding the periphery of the first island-shaped semiconductor layer, the first gate electrode surrounding the periphery of the first gate dielectric film, the first p+-type semiconductor layer arranged on the top of the first island-shaped semiconductor layer, and the second p+-type semiconductor layer arranged underneath the first island-shaped semiconductor layer, a combination of the first gate electrode, the second gate dielectric film surrounding a part of the periphery of the first gate electrode, the first arc-shaped semiconductor layer in contact with a part of a periphery of the second gate dielectric film, a first n+-type semiconductor layer arranged on the top of the first arc-shaped semiconductor layer, and the second n+-type semiconductor layer arranged underneath the first arc-shaped semiconductor layer, a combination of the second island-shaped semiconductor layer, the third gate dielectric film surrounding the periphery of the second island-shaped semiconductor layer, the second gate electrode surrounding the periphery of the third gate dielectric film, the third p+-type semiconductor layer arranged on the top of the second island-shaped semiconductor layer, and the fourth p+-type semiconductor layer arranged underneath the second island-shaped semiconductor layer, and a combination of the second gate electrode, the fourth gate dielectric film surrounding a part of the periphery of the second gate electrode, the second arc-shaped semiconductor layer in contact with a part of the periphery of the fourth gate dielectric film, the third n+-type semiconductor layer arranged on the top of the second arc-shaped semiconductor layer, and the fourth n+-type semiconductor layer arranged underneath the second arc-shaped semiconductor layer, respectively, wherein: the first gate dielectric film is adapted to allow the first pMOS transistor to operate as an enhancement type; the second gate dielectric film is adapted to allow the first nMOS transistor to operate as an enhancement type; the first electrode is made of a material allowing the first pMOS transistor and the first nMOS transistor to operate as an enhancement type; the third gate dielectric film is adapted to allow the second nMOS transistor to operate as an enhancement type, and the first electrode is made of a material allowing the second pMOS transistor and the second nMOS transistor to operate as an enhancement type.

    [0017] Preferably, in the semiconductor device according to the fifth aspect of the present invention, each of the first to tenth semiconductor-metal compound layers is a silicon-metal compound layer.

    [0018] In the semiconductor device of the present invention, the first island-shaped semiconductor layer, the first arc-shaped semiconductor layer, the second island-shaped semiconductor layer, the second arc-shaped semiconductor layer, the third island-shaped semiconductor layer and the fourth island-shaped semiconductor layer may be a first island-shaped silicon layer, a first arc-shaped silicon layer, a second island-shaped silicon layer, a second arc-shaped silicon layer, a third island-shaped silicon layer and a fourth island-shaped silicon layer, respectively. Further, each of the n+-type semiconductor layers may be a p+-type silicon layer, and each of the p+-type semiconductor layers may be a p+-type silicon layer.

    [0019] Preferably, in the above semiconductor device, the first island-shaped silicon layer, the first arc-shaped silicon layer, the second island-shaped silicon layer, the second arc-shaped silicon layer, the third island-shaped silicon layer and the fourth island-shaped silicon layer are a first n-type or non-doped island-shaped silicon layer, a first p-type or non-doped arc-shaped silicon layer, a second n-type or non-doped island-shaped silicon layer, a second p-type or non-doped arc-shaped silicon layer, a third p-type or non-doped island-shaped silicon layer and a fourth p-type or non-doped island-shaped silicon layer, respectively.

    [0020] As above, the semiconductor device according to the first aspect of the present invention is according to claim 1.

    [0021] The semiconductor device according to the second aspect of the present invention is the semiconductor device as defined in the first aspect of the present invention, which is further characterized in that the first gate dielectric film is surrounding a periphery of the first island-shaped semiconductor layer, the first gate electrode is surrounding a periphery of the first gate dielectric film, the third gate dielectric film is surrounding a periphery of the second island-shaped semiconductor layer, the second gate electrode is surrounding a periphery of the third gate dielectric film, the fifth gate dielectric film is surrounding a periphery of the third island-shaped semiconductor layer, the third gate electrode is surrounding a periphery of the fifth gate dielectric film, the sixth gate dielectric film is surrounding a periphery of the fourth island-shaped semiconductor layer, and the fourth gate electrode is surrounding a periphery of the sixth gate dielectric film. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0022] The semiconductor device according to the third aspect of the present invention is the semiconductor device as defined in the second aspect of the present invention, which is further characterized by comprising a fifth first-conductive-type high-concentration semiconductor layer arranged underneath the second first-conductive-type high-concentration semiconductor layer, the second second-conductive-type high-concentration semiconductor layer and the eighth second-conductive-type high-concentration semiconductor layer; a sixth first-conductive-type high-concentration semiconductor layer arranged underneath the fourth first-conductive-type high-concentration semiconductor layer, the fourth second-conductive-type high-concentration semiconductor layer and the sixth second-conductive-type high-concentration semiconductor layer; a first semiconductor-metal compound layer formed on a part of respective sidewalls of the second second-conductive-type high-concentration semiconductor layer and the fifth first-conductive-type high-concentration semiconductor layer; a second semiconductor-metal compound layer formed on the eighth second-conductive-type high-concentration semiconductor layer and the fifth firstconductive-type high-concentration semiconductor layer; a third semiconductor-metal compound layer formed on a part of respective sidewalls of the fourth second-conductive-type high-concentration semiconductor layer and the sixth first-conductive-type high-concentration semiconductor layer; a fourth semiconductor-metal compound layer formed on the sixth second-conductive-type high-concentration semiconductor layer and the sixth first-conductive-type high-concentration semiconductor layer; a fifth semiconductor-metal compound layer formed on the first first-conductive-type high-concentration semiconductor layer; a sixth semiconductor-metal compound layer formed on the first second-conductive-type high-concentration semiconductor layer; a seventh semiconductor-metal compound layer formed on the third first-conductive-type high-concentration semiconductor layer; an eighth semiconductor-metal compound layer formed on the third second-conductive-type high-concentration semiconductor layer; a ninth semiconductor-metal compound layer formed on the fifth second-conductive-type high-concentration semiconductor layer; a tenth semiconductor-metal compound layer formed on the seventh second-conductive-type high-concentration semiconductor layer; a first contact connecting the first gate electrode and the fourth semiconductor-metal compound layer; and a second contact connecting the second gate electrode and the second semiconductor-metal compound layer. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0023] The semiconductor device according to the fourth aspect of the present invention is the semiconductor device as defined in the second aspect of the present invention, further characterized in that the first first-conductive-type high-concentration semiconductor layer is a first p+-type semiconductor layer, the second first-conductive-type high-concentration semiconductor layer is a second p+-type semiconductor layer, the first second-conductive-type high-concentration semiconductor layer is a first n+-type semiconductor layer, the second second-conductive-type high-concentration semiconductor layer is a second n+-type semiconductor layer, the third first-conductive-type high-concentration semiconductor layer is a third p+-type semiconductor layer, the fourth first-conductive-type high-concentration semiconductor layer is a fourth p+-type semiconductor layer, the third second-conductive-type high-concentration semiconductor layer is a third n+-type semiconductor layer, the fourth second-conductive-type high-concentration semiconductor layer is a fourth n+-type semiconductor layer, the fifth second-conductive-type high-concentration semiconductor layer is a fifth n+-type semiconductor layer, the sixth second-conductive-type high-concentration semiconductor layer is a sixth n+-type semiconductor layer, the seventh second-conductive-type high-concentration semiconductor layer is a seventh n+-type semiconductor layer, and the eighth second-conductive-type high-concentration semiconductor layer is an eighth n+-type semiconductor layer. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0024] The semiconductor device according to the fifth aspect of the present invention is the semiconductor device as defined In the fourth aspect of the present invention, which is further characterized by comprising a fifth p+-type semiconductor layer arranged underneath the second p+-type semiconductor layer, the second n+-type semiconductor layer and the eighth n+-type semiconductor layer; a sixth p+-type semiconductor layer arranged underneath the fourth p+-type semiconductor layer, the fourth n+-type semiconductor layer and the sixth n+-type semiconductor layer; a first semiconductor-metal compound layer formed on a part of respective sidewalls of the second n+-type semiconductor layer and the fifth p+-type semiconductor layer; a second semiconductor-metal compound layer formed on the eighth n+-type semiconductor layer and the fifth p+-type semiconductor layer; a third semiconductor-metal compound layer formed on a part of respective sidewalls of the fourth n+-type semiconductor layer and the sixth p+-type semiconductor layer; a fourth semiconductor-metal compound layer formed on the sixth n+-type semiconductor layer and the sixth p+-type semiconductor layer; a fifth semiconductor-metal compound layer formed on the first p+-type semiconductor layer; a sixth semiconductor-metal compound layer formed on the first n+-type semiconductor layer; a seventh semiconductor-metal compound layer formed on the third p+-type semiconductor layer; an eighth semiconductor-metal compound layer formed on the third n+-type semiconductor layer; a ninth semiconductor-metal compound layer formed on the fifth n+-type semiconductor layer;
    a tenth semiconductor-metal compound layer formed on the seventh n+-type semiconductor layer; a first contact connecting the first gate electrode and the fourth semiconductor-metal compound layer; and a second contact connecting the second gate electrode and the second semiconductor-metal compound layer. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0025] In a preferred embodiment of the present invention, the semiconductor device is configured to satisfy the following condition: Wp1 2Wn1, wherein Wp1 is an outer peripheral length of the first island-shaped semiconductor layer, and Wn1 is a length of an arc of the first arc-shaped semiconductor layer in contact with a part of the periphery of the second gate dielectric film. In this case, a gate length of a pMOS transistor can be set to be twice as large as that of an nMOS transistor. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0026] In a preferred embodiment of the present invention, the semiconductor device is configured to satisfy the following condition: Wp2 ≈2Wn2, wherein Wp2 is an outer peripheral length of the second island-shaped semiconductor layer, and Wn2 is a length of an arc of the second arc-shaped semiconductor layer in contact with a part of the periphery of the fourth gate dielectric film. In this case, a gate length of a pMOS transistor can be set to be twice as large as that of an nMOS transistor. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0027] In a preferred embodiment of the present invention, the semiconductor device is configured to satisfy the following condition: Ln1 ≈ Lp1, wherein Ln1 is a channel length of the first arc-shaped semiconductor layer, and Lp1 is a channel length of the first island-shaped semiconductor layer. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM

    [0028] In a preferred embodiment of the present invention, the semiconductor device is configured to satisfy the following condition: Ln2 =Lp2, wherein Ln2 is a channel length of the second arc-shaped semiconductor layer, and Lp2 is a channel length of the second island-shaped semiconductor layer. This makes it possible to provide a semiconductor device comprising a highly-integrated SGT-based SRAM.

    [0029] In a preferred embodiment of the present invention, a first pMOS transistor, a first nMOS transistor, a second pMOS transistor and a second nMOS transistor are made up of a combination of the first island-shaped semiconductor layer, the first gate dielectric film surrounding the periphery of the first island-shaped semiconductor layer, the first gate electrode surrounding the periphery of the first gate dielectric film, the first p+-type semiconductor layer arranged on the top of the first island-shaped semiconductor layer, and the second p+-type semiconductor layer arranged underneath the first island-shaped semiconductor layer, a combination of the first gate electrode, the second gate dielectric film surrounding a part of the periphery of the first gate electrode, the first arc-shaped semiconductor layer in contact with a part of a periphery of the second gate dielectric film, a first n+-type semiconductor layer arranged on the top of the first arc-shaped semiconductor layer, and the second n+-type semiconductor layer arranged underneath the first arc-shaped semiconductor layer, a combination of the second island-shaped semiconductor layer, the third gate dielectric film surrounding the periphery of the second island-shaped semiconductor layer, the second gate electrode surrounding the periphery of the third gate dielectric film, the third p+-type semiconductor layer arranged on the top of the second island-shaped semiconductor layer, and the fourth p+-type semiconductor layer arranged underneath the second island-shaped semiconductor layer, and a combination of the second gate electrode, the fourth gate dielectric film surrounding a part of the periphery of the second gate electrode, the second arc-shaped semiconductor layer in contact with a part of the periphery of the fourth gate dielectric film, the third n+-type semiconductor layer arranged on the top of the second arc-shaped semiconductor layer, and the fourth n+-type semiconductor layer arranged underneath the second arc-shaped semiconductor layer, respectively, wherein: the first gate dielectric film is adapted to allow the first pMOS transistor to operate as an enhancement type; the second gate dielectric film is adapted to allow the first nMOS transistor to operate as an enhancement type; the first electrode is made of a material allowing the first pMOS transistor and the first nMOS transistor to operate as an enhancement type; the third gate dielectric film is adapted to allow the second nMOS transistor to operate as an enhancement type, and the first electrode is made of a material allowing the second pMOS transistor and the second nMOS transistor to operate as an enhancement type. In this case, each of the pMOS and nMOS transistors can be formed as an enhancement type.

    [0030] In a preferred embodiment of the present invention, each of the first to tenth semiconductor-metal compound layers is a silicon-metal compound layer.

    FIG. 1 shows a semiconductor device according to one embodiment of the present invention, wherein (a), (b) and (c) are a schematic diagram of the semiconductor device in a plane view, a sectional view taken along the line X-X' in (a) and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 2 shows a step in one example of a production process for the semiconductor device according to the embodiment, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 3 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 4 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 5 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 6 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 7 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 8 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view, taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 9 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 10 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 11 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 12 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 13 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 14 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 15 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 16 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 17 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 18 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 19 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 20 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 21 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 22 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 23 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 24 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 25 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 26 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 27 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 28 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 29 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 30 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 31 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 32 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 33 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 34 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 35 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 36 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 37 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 38 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 39 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 40 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 41 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 42 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 43 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 44 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 45 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 46 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 47 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 48 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 49 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 50 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 51 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 52 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 53 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 54 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 55 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 56 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 57 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 58 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 59 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 60 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 61 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 62 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 63 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 64 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG 65 shows a step in the example of the production process, wherein (a), (b) and (c) are a top plan view, a sectional view taken along the line X-X' in (a), and a sectional view taken along the line Y-Y' in (a), respectively.

    FIG. 66 is a diagram showing a semiconductor device structure formed by arranging the semiconductor device according to the embodiment in a three-row by three-column array.

    FIG 67 is a diagram showing an inverter output terminal layer in the semiconductor device structure formed by arranging the semiconductor device according to the embodiment in a three-row by three-column array.

    FIG 68 is a diagram showing a transistor layer in the semiconductor device structure formed by arranging the semiconductor device according to the embodiment in a three-row by three-column array.

    FIG. 69 is a diagram showing a contact layer and a first level metal layer in the semiconductor device structure formed by arranging the semiconductor device according to the embodiment in a three-row by three-column array.

    FIG. 70 is a diagram showing a second level metal layer, and a first level via (a contact between the first level metal layer and the second level metal layer), in the semiconductor device structure formed by arranging the semiconductor device according to the embodiment in a three-row by three-column array.

    FIG. 71 is a diagram showing a third level metal layer, and a second level via (a contact between the second level metal layer and the third level metal layer), in the semiconductor device structure formed by arranging the semiconductor device according to the embodiment in a three-row by three-column array.

    FIG. 72 is a diagram showing a fourth level metal layer, and a third level via (a contact between the third level metal layer and the fourth level metal layer), in the semiconductor device structure formed by arranging the semiconductor device according to the embodiment in a three-row by three-column array.


    DETAILED DESCRIPTION



    [0031] FIG. 1 shows a semiconductor device according to one embodiment of the present invention, wherein (a), (b) and (c) are a schematic diagram of the semiconductor device in a plane view, a sectional view taken along the line X-X' in (a) and a sectional view taken along the line Y-Y' in (a), respectively. (a) is a top plan view in which some part is hatched for distinguishing regions. Some components are hatched in a plane view for distinguishing regions. Only two sectional views of the semiconductor device are shown for the easy of viewing.

    [0032] The semiconductor device according to this embodiment comprises: a first inverter 237 arranged at an intersection of the 1st row and the 1st column, wherein the first inverter 237 includes a first island-shaped silicon layer 137, a first gate dielectric film 187 surrounding a periphery of the first island-shaped silicon layer 137, a first gate electrode 178 surrounding a periphery of the first gate dielectric film 187, a second gate dielectric film 187 surrounding a part of a periphery of the first gate electrode 178, a first arc-shaped silicon layer 141 in contact with a part of a periphery of the second gate dielectric film, a first p+-type silicon layer 161 arranged on a top of the first island-shaped silicon layer 137, a second p+-type silicon layer 162 arranged underneath the first island-shaped silicon layer 137, a first n+-type silicon layer 154 arranged on a top of the first arc-shaped silicon layer 141, and a second n+-type silicon layer 156 arranged underneath the first arc-shaped silicon layer 141; a second inverter 240 arranged at an intersection of the 2nd row and the 2nd column, wherein the second inverter 240 includes a second island-shaped silicon layer, a third gate dielectric film surrounding a periphery of the second island-shaped silicon layer, a second gate electrode 181 surrounding a periphery of the third gate dielectric film, a fourth gate dielectric film surrounding a part of a periphery of the second gate electrode 181, a second arc-shaped silicon layer in contact with a part of a periphery of the fourth gate dielectric film, a third p+-type silicon layer arranged on a top of the second island-shaped silicon layer, a fourth p+-type silicon layer arranged underneath the second island-shaped silicon layer, a third n+-type silicon layer arranged on a top of the second arc-shaped silicon layer, and a fourth n+-type silicon layer arranged underneath the second arc-shaped silicon layer; a first selection transistor 239 arranged at an intersection of the 1st row and the 2nd column, wherein the first selection transistor 239 includes a third island-shaped silicon layer 138, a fifth gate dielectric film 188 surrounding a periphery of the third island-shaped silicon layer 138, a third gate electrode 179 surrounding a periphery of the fifth gate dielectric film 188, a fifth n+-type silicon layer 155 arranged on a top of the third island-shaped silicon layer 138, and a sixth n+-type silicon layer 157 arranged underneath the third island-shaped silicon layer 138; a second selection transistor 242 arranged at an intersection of the 2nd row and the 1st column, wherein the second selection transistor 242 includes a fourth island-shaped silicon layer 139, a sixth gate dielectric film 189 surrounding a periphery of the fourth island-shaped silicon layer 139, a fourth gate electrode 180 surrounding a periphery of the sixth gate dielectric film 189, a seventh n+-type silicon layer 158 arranged on a top of the fourth island-shaped silicon layer 139, and an eighth n+-type silicon layer 156 arranged underneath the fourth island-shaped silicon layer 139; a fifth p+-type silicon layer 143 arranged underneath the second p+-type silicon layer 162, the second n+-type silicon layer 156 and the eighth n+-type silicon layer 156; a sixth p+-type silicon layer 144 arranged underneath the fourth p+-type silicon layer, the fourth n+-type silicon layer and the sixth n+-type silicon layer 157; a first silicon-metal compound layer 204 formed on a part of respective sidewalls of the second n+-type silicon layer 156 and the fifth p+-type silicon layer 143; a second silicon-metal compound layer 201 formed on the eighth n+-type silicon layer 156 and the fifth p+-type silicon layer 143; a third silicon-metal compound layer 205 formed on a part of respective sidewalls of the fourth n+-type silicon layer and the sixth p+-type silicon layer 144; a fourth silicon-metal compound layer 198 formed on the sixth n+-type silicon layer 157 and the sixth p+-type silicon layer 144; a fifth silicon-metal compound layer 197 formed on the first p+-type silicon layer 161; a sixth silicon-metal compound layer 196 formed on the first n+-type silicon layer 154; a seventh silicon-metal compound layer formed on the third p+-type silicon layer; an eighth silicon-metal compound layer formed on the third n+-type silicon layer; a ninth silicon-metal compound layer 199 formed on the fifth n+-type silicon layer 155; a tenth silicon-metal compound layer 200 formed on the seventh n+-type silicon layer 158; a first contact 209 connecting the first gate electrode 178 and the fourth silicon-metal compound layer 198; and a second contact 210 connecting the second gate electrode 181 and the second silicon-metal compound layer 201.

    [0033] A contact 221 is formed on the fifth silicon-metal compound layer 197. A contact 220 is formed on the sixth silicon-metal compound layer 196. A contact 226 is formed on the seventh silicon-metal compound layer. A contact 227 is formed on the eighth silicon-metal compound layer. A contact 222 is formed on the ninth silicon-metal compound layer 199. A contact 225 is formed on the tenth silicon-metal compound layer 200. A contact 223 is formed on the third gate electrode 179. A contact 224 is formed on the fourth gate electrode 180.

    [0034] A first level metal 228 is formed on the contact 220. A first level metal 229 is formed on the contact 221. A first level metal 230 is formed on the contact 222. A first level metal 231 is formed on the contact 223. A first level metal 232 is formed on the contact 224. A first level metal 233 is formed on the contact 225. A first level metal 234 is formed on the contact 226. A first level metal 235 is formed on the contact 227. In the above manner, an SRAM memory cell is formed.

    [0035] The above semiconductor device is configured to satisfy the following condition: Wp1 ≈ 2Wn1, wherein Wp1 is an outer peripheral length of the first island-shaped silicon layer 137, and Wn1 is a length of an arc of the first arc-shaped silicon layer 141 in contact with a part of the periphery of the second gate dielectric film 187. Thus, a gate width of a pMOS transistor can be set to be twice as large as that of an nMOS transistor. In this case, it is preferable to satisfy the following condition: Ln1 ≈ Lp1, wherein Ln1 is a channel length of the first arc-shaped silicon layer 141, and Lp1 is a channel length of the first island-shaped silicon layer 137.

    [0036] The above semiconductor device is also configured to satisfy the following condition: Wp2 ≈2Wn2, wherein Wp2 is an outer peripheral length of the second island-shaped silicon layer, and Wn2 is a length of an arc of the second arc-shaped silicon layer in contact with a part of the periphery of the fourth gate dielectric film. Thus, a gate width of a pMOS transistor can be set to be twice as large as that of an nMOS transistor. In this case, it is preferable to satisfy the following condition: Ln2 ≈ Lp2, wherein Ln2 is a channel length of the second arc-shaped silicon layer, and Lp2 is a channel length of the second island-shaped silicon layer.

    [0037] With reference to FIG 2, one example of a production process for forming a structure of the semiconductor device according to this embodiment will be described below. In these figures, the same elements or components are defined by a common reference numeral or code. Each of FIG. 2 to FIG. 65 shows a step in the example of the production process, wherein the figure suffixed with (a), the figure suffixed with (b) and the figure suffixed with (c) are a top plan view, a sectional view taken along the line X-X' in the figure suffixed with (a), and a sectional view taken along the line Y-Y' in the figure suffixed with (a), respectively. (a) are top plan views in which some part is hatched for distinguishing regions.

    [0038] Referring to FIG. 2, boron (B) is implanted into a p-type or non-doped silicon layer 103 formed on an oxide layer 101 to form a p+-type silicon layer 102 therein.

    [0039] Referring to FIG. 3, a resist 104 for forming an n-type silicon layer is formed. In cases where after-mentioned silicon layers 105, 106 are formed as a non-doped type, this step is unnecessary.

    [0040] Referring to FIG. 4, two n-type silicon layers 105, 106 are formed by implantation of phosphorus (P). In cases where these silicon layers 105, 106 are formed as a non-doped type, this step is unnecessary.

    [0041] Referring to FIG. 5, the resist 104 is stripped away, and then a heat treatment is performed. In cases where the silicon layers 1.05, 106 are formed as a non-doped type, this step is unnecessary.

    [0042] Referring to FIG. 6, an oxide film 107 is deposited, and then a nitride film 108 is deposited.

    [0043] Referring to FIG. 7, four resists 109, 110, 111, 112 for forming four (first, second, third, and fourth) island-shaped silicon layers is formed.

    [0044] Referring to FIG. 8, the nitride film 108 and the oxide film 107 are etched to form four nitride films 113, 114, 115 (one of the nitride films is indicated by the reference numeral 116 in FIG. 9, etc.) and four oxide films 117, 118, 119 (one of the oxide films is not indicated by a reference numeral).

    [0045] Referring to FIG. 9, the resists 109, 110, 111, 112 are stripped away.

    [0046] Referring to FIG. 10, an oxide film 121 is deposited.

    [0047] Referring to FIG. 11, the oxide film 121 is etched to form four oxide film-based sidewalls 122, 123, 124, 125.

    [0048] Referring to FIG. 12, a nitride film 126 is deposited.

    [0049] Referring to FIG. 13, the nitride film 126 is etched to form four nitride film-based sidewalls 127, 128, 129, 130.

    [0050] Referring to FIG. 14, four resists 131, 132, 133, 134 are formed.

    [0051] Referring to FIG 15, the nitride film-based sidewalls 127, 128, 129, 130 are etched to form two nitride film-based hard masks 127 (one of the nitride film-based hard masks is indicated by the reference numeral 130 in FIG. 17, etc.) for forming first and second arc-shaped silicon layers.

    [0052] Referring to FIG 16, the oxide film-based sidewalls 122, 123, 124, 125 are etched.

    [0053] Referring to FIG 17, the resists 131, 132, 133, 134 are stripped away.

    [0054] Referring to FIG. 18, two resists 135, 136 for forming a diffusion-layer interconnection section is formed.

    [0055] Referring to FIG 19, the silicon layer 103 is etched to form a diffusion-layer interconnection section thereon.

    [0056] Referring to FIG. 20, the resists 135, 136 are stripped away.

    [0057] Referring to FIG 21, the oxide film-based sidewalls 122, 123, 124, 125 are etched away.

    [0058] Referring to FIG 22, the silicon layer 103 and silicon layers 105, 106 are etched to form a first island-shaped silicon layer 137, a third island-shaped silicon layer 138, a fourth island-shaped silicon layer 139, a second island-shaped silicon layer (indicated by the reference numeral 140 in FIG 23, etc), a first arc-shaped silicon layer 141, a second arc-shaped silicon layer (indicated by the reference numeral 142 in FIG. 23, etc), and fifth and sixth p+-type silicon layers 143, 144.

    [0059] Referring to FIG. 23, the nitride films 113, 114, 115, 116 and the oxide films 117, 118, 119 are stripped away.

    [0060] Referring to FIG. 24, a nitride film 145 is deposited.

    [0061] Referring to FIG. 25, the nitride film 145 is etched to form six nitride film-based sidewalls 146, 147, 148, 149, 150, 151 for protecting channel regions during ion implantation in a subsequent step.

    [0062] Referring to FIG. 26, two resists 152, 153 for forming an n+-type silicon layer are formed.

    [0063] Referring to FIG. 27, arsenic (As) is implanted to form a first n+-type silicon layer 154, a second n+-type silicon layer 156, a third n+-type silicon layer 159, a fourth n+-type silicon layer 157, a fifth n+-type silicon layer 155, a sixth n+-type silicon layer 157, a seventh n+-type silicon layer 158 and an eighth n+-type silicon layer 156.

    [0064] Referring to FIG 28, the resists 152, 153 are stripped away.

    [0065] Referring to FIG. 29, a resist 160 for forming a p+-type silicon layer is formed.

    [0066] Referring to FIG 30, boron (B) is implanted to form a first p+-type silicon layer 161, a second p+-type silicon layer 162, a third p+-type silicon layer 163 and a fourth p+-type silicon layer 164.

    [0067] Referring to FIG 31, the resist 160 is stripped away, and then a heat treatment is performed.

    [0068] Referring to FIG 32, an oxide film 165 is deposited, and then subjected to flattening and etching-back to expose the first n+-type silicon layer 154, the third n+-type silicon layer 159, the fifth n+-type silicon layer 155, the seventh n+-type silicon layer 158, the first p+-type silicon layer 161 and the third p+-type silicon layer 163.

    [0069] Referring to FIG. 33, a resist 166 for forming a gate section is formed.

    [0070] Referring to FIG. 34, a portion of the oxide film 165 corresponding to the gate section is etched.

    [0071] Referring to FIG. 35, the resist 166 is stripped away.

    [0072] Referring to FIG. 36, the nitride film-based sidewalls 148, 149, 150, 151 are etched away.

    [0073] Referring to FIG. 37, a high-K (high-dielectric constant) film 167 is deposited, and then a metal 168, such as titanium nitride (TiN); is deposited.

    [0074] Referring to FIG. 38, a nitride film 169 is deposited.

    [0075] Referring to FIG. 39, four resists 170, 171, 172, 173 for forming a gate pad is formed.

    [0076] Referring to FIG. 40, the nitride film 169 is etched to form four nitride film-based hard masks 174, 175 (two of the nitride film-based hard masks are indicated by the reference numerals 176, 177 in FIG. 41, etc.)

    [0077] Referring to FIG. 41, the resists 170, 171, 172, 173 are stripped away.

    [0078] Referring to FIG. 42, the metal 168 is etched to form first to fourth gate electrodes 178, 181, 179, 180.

    [0079] Referring to FIG. 43, a nitride film 182 is deposited.

    [0080] Referring to FIG. 44, the nitride film 182 is etched to form four nitride film-based sidewalls 183, 184, 185, 186.

    [0081] Referring to FIG. 45, the high-K film is etched to form first to six high-K films (gate dielectric films) 187, 187, 190, 190, 188, 189.

    [0082] Referring to FIG. 46, for resists 191, 192, 193, 194 for etching the oxide film 165 is formed.

    [0083] Referring to FIG. 47, the oxide film 165 is dry-etched.

    [0084] Referring to FIG. 48, the resists 191, 192, 193, 194 are stripped away.

    [0085] Referring to FIG. 49, the oxide film 165 is wet-etched.

    [0086] Referring to FIG. 50, a nitride film 195 is deposited.

    [0087] Referring to FIG. 51, the nitride film 195 is etched to form nitride film-based sidewalls 195.

    [0088] Referring to FIG. 52, the oxide film 165 is dry-etched.

    [0089] Referring to FIG 53, the oxide film 165 is wet-etched to expose the nitride film-based sidewalls 146, 147.

    [0090] Referring to FIG. 54, the nitride film-based sidewalls 195 are etched, and a part of the nitride film-based sidewalls 146, 147 is etched, to expose a part of respective sidewalls of the second n+-type silicon layer 156, the fifth p+-type silicon layer 143, and a part of respective sidewalls of the fourth n+-type silicon layer 157 and the sixth p+-type silicon layer 144.

    [0091] Referring to FIG. 55, a metal, such as nickel (Ni) or cobalt (Co), is deposited. Subsequently, a heat treatment is performed, and then an unreacted metal film is removed, to obtain a first silicon-metal compound layer 204 formed on a part of the sidewalls of the second n+-type silicon layer 156 and the fifth p+-type silicon layer 143, a second silicon-metal compound layer 201 formed on the eighth n+ silicon layer 156 and the fifth p+-type silicon layer 143, a third silicon-metal compound layer 205 formed on a part of the sidewalls of the fourth n+-type silicon layer 157 and the sixth p+-type silicon layer 144, a fourth silicon-metal compound layer 198 formed on the sixth n+-type silicon layer 157 and the sixth p+-type silicon layer 144; a fifth silicon-metal compound layer 197 formed on the first p+-type silicon layer 161, a sixth silicon-metal compound layer 196 formed on the first n+-type silicon layer 154, a seventh silicon-metal compound layer 202 formed on the third p+-type silicon layer 163, an eighth silicon-metal compound layer 203 formed on the third n+-type silicon layer 159, a ninth silicon-metal compound layer 199 formed on the fifth n+-type silicon layer 155, and a tenth silicon-metal compound layer 200 formed on the seventh n+-type silicon layer 158.

    [0092] Referring to FIG. 56, an interlayer film 206, such as an oxide film, is formed.

    [0093] Referring to FIG 57, a contact hole 207 is formed to expose a part of the first gate electrode 178 and the fourth silicon-metal compound layer 198, and a contact hole 208 is formed to expose a part of the second gate electrode 181 and the second silicon-metal compound layer 201.

    [0094] Referring to FIG. 58, a metal, such as tungsten (W), is deposited to form first and second contacts 209, 210.

    [0095] Referring to FIG. 59, an interlayer film 211 is formed.

    [0096] Referring to FIG. 60, a contact hole 212 is formed on the third gate electrode 179, and a contact hole 213 is formed on the fourth gate electrode 180.

    [0097] Referring to FIG. 61, a contact hole 214 is formed on the sixth silicon-metal compound layer 196, and a contact hole 215 is formed on the eighth silicon-metal compound layer 203.

    [0098] Referring to FIG. 62, four contact holes 216, 217, 218, 219 are formed on the fifth silicon-metal compound layer 197, the ninth silicon-metal compound layer 199, the tenth silicon-metal compound layer 200 and the seventh silicon-metal compound layer 202, respectively.

    [0099] Referring to FIG. 63, a metal, such as tungsten (W), is deposited to form eight contacts 220,221,222,223,224,225,226,227.

    [0100] Referring to FIG. 64, eight first level metals 228, 229, 230, 231, 232, 233, 234, 235 are formed on respective ones of the eight contacts.

    [0101] Referring to FIG. 65, an interlayer film 236 is formed. In the above manner, an SRAM memory cell is formed.

    [0102] With reference to FIG. 66 to 72, one example of a semiconductor device structure formed by arranging the semiconductor device according to the above embodiment in a three-row by three-column array. In these figures, the same elements or components are defined by a common reference numeral or code. FIG. 66 shows the semiconductor device structure formed by arranging the semiconductor device according to the above embodiment in a three-row by three-column array. FIG. 67 shows an inverter output terminal layer in the semiconductor device structure, and FIG. 68 shows a transistor layer in the semiconductor device structure. FIG. 69 shows a contact layer and a first level metal layer in the semiconductor device structure, and FIG. 70 shows a second level metal layer, and a first level via (a contact between the first level metal layer and the second level metal layer), in the semiconductor device structure. FIG. 71 shows a third level metal layer, and a second level via (a contact between the second level metal layer and the third level metal layer), in the semiconductor device structure, and FIG. 72 shows a fourth level metal layer, and a third level via (a contact between the third level metal layer and the fourth level metal layer), in the semiconductor device structure.

    [0103] An inverter 319 is arranged at an intersection of the 1st row and the 1st column. A selection transistor 337 is arranged at an intersection of the 1st row and the 2nd column. A selection transistor 340 is arranged at an intersection of the 2nd row and the 1st column. An inverter 322 is arranged at an intersection of the 2nd row and the 2nd column. The inverter 319 and the selection transistor 340 are connected to each other by an output terminal 301. The inverter 322 and the selection transistor 337 are connected to each other by an output terminal 302. An input terminal 355 of the inverter 319 is connected to the output terminal 302 via a contact 374. An input terminal 358 of the inverter 322 is connected to the output terminal 301 via a contact 373.

    [0104] An inverter 320 is arranged at an intersection of the 1st row and the 4th column. A selection transistor 338 is arranged at an intersection of the 1st row and the 3rd column. A selection transistor 341 is arranged at an intersection of the 2nd row and the 4th column. An inverter 323 is arranged at an intersection of the 2nd row and the 3rd column. The inverter 323 and the selection transistor 338 are connected to each other by an output terminal 303. The inverter 320 and the selection transistor 341 are connected to each other by an output terminal 304. An input terminal 359 of the inverter 323 is connected to the output terminal 304 via a contact 376. An input terminal 356 of the inverter 320 is connected to the output terminal 303 via a contact 375.

    [0105] An inverter 321 is arranged at an intersection of the 1st row and the 5th column. A selection transistor 339 is arranged at an intersection of the 1st row and the 6th column. A selection transistor 342 is arranged at an intersection of the 2nd row and the 5th column. An inverter 324 is arranged at an intersection of the 2nd row and the 6th column. The inverter 321 and the selection transistor 342 are connected to each other by an output terminal 305. The inverter 324 and the selection transistor 339 are connected to each other by an output terminal 306. An input terminal 357 of the inverter 321 is connected to the output terminal 306 via a contact 378. An input terminal 360 of the inverter 324 is connected to the output terminal 305 via a contact 377.

    [0106] The selection transistor 340 has a gate electrode 393. The selection transistor 337 and the selection transistor 338 have a gate electrode 391. The selection transistor 341 and the selection transistor 342 have a gate electrode 394. The selection transistor 339 has a gate electrode 392.

    [0107] An inverter 325 is arranged at an intersection of the 3rd row and the 2nd column. A selection transistor 343 is arranged at an intersection of the 3rd row and the 1st column. A selection transistor 346 is arranged at an intersection of the 4th row and the 2nd column. An inverter 328 is arranged at an intersection of the 4th row and the 1st column. The inverter 328 and the selection transistor 343 are connected to each other by an output terminal 307. The inverter 325 and the selection transistor 346 are connected to each other by an output terminal 308. An input terminal 364 of the inverter 328 is connected to the output terminal 308 via a contact 380. An input terminal 361 of the inverter 325 is connected to the output terminal 307 via a contact 379.

    [0108] An inverter 326 is arranged at an intersection of the 3rd row and the 3rd column. A selection transistor 344 is arranged at an intersection of the 3rd row and the 4th column. A selection transistor 347 is arranged at an intersection of the 4th row and the 3rd column. An inverter 329 is arranged at an intersection of the 4th row and the 4th column. The inverter 326 and the selection transistor 347 are connected to each other by an output terminal 309. The inverter 329 and the selection transistor 344 are connected to each other by an output terminal 310. An input terminal 362 of the inverter 326 is connected to the output terminal 310 via a contact 382. An input terminal 365 of the inverter 329 is connected to the output terminal 309 via a contact 381.

    [0109] An inverter 327 is arranged at an intersection of the 3rd row and the 6th column. A selection transistor 345 is arranged at an intersection of the 3rd row and the 5th column. A selection transistor 348 is arranged at an intersection of the 4th row and the 6th column. An inverter 330 is arranged at an intersection of the 4th row and the 5th column. The inverter 330 and the selection transistor 345 are connected to each other by an output terminal 311. The inverter 327 and the selection transistor 348 are connected to each other by an output terminal 312. An input terminal 366 of the inverter 330 is connected to the output terminal 312 via a contact 384. An input terminal 363 of the inverter 327 is connected to the output terminal 311 via a contact 383.

    [0110] The selection transistor 343 has a gate electrode 395. The selection transistor 346 and the selection transistor 347 have a gate electrode 397. The selection transistor 344 and the selection transistor 345 have a gate electrode 396. The selection transistor 348 has a gate electrode 398.

    [0111] An inverter 331 is arranged at an intersection of the 5th row and the 1st column. A selection transistor 349 is arranged at an intersection of the 5th row and the 2nd column. A selection transistor 352 is arranged at an intersection of the 6th row and the 1st column. An inverter 334 is arranged at an intersection of the 6th row and the 2nd column. The inverter 331 and the selection transistor 352 are connected to each other by an output terminal 313. The inverter 334 and the selection transistor 349 are connected to each other by an output terminal 314. An input terminal 367 of the inverter 331 is connected to the output terminal 314 via a contact 386. An input terminal 370 of the inverter 334 is connected to the output terminal 313 via a contact 385.

    [0112] An inverter 332 is arranged at an intersection of the 5th row and the 4th column. A selection transistor 350 is arranged at an intersection of the 5th row and the 3rd column. A selection transistor 353 is arranged at an intersection of the 6th row and the 4th column. An inverter 335 is arranged at an intersection of the 6th row and the 3rd column. The inverter 335 and the selection transistor 350 are connected to each other by an output terminal 315. The inverter 332 and the selection transistor 353 are connected to each other by an output terminal 316. An input terminal 371 of the inverter 335 is connected to the output terminal 316 via a contact 388. An input terminal 368 of the inverter 332 is connected to the output terminal 315 via a contact 387.

    [0113] An inverter 333 is arranged at an intersection of the 5th row and the 5th column. A selection transistor 351 is arranged at an intersection of the 5th row and the 6th column. A selection transistor 354 is arranged at an intersection of the 6th row and the 5th column. An inverter 336 is arranged at an intersection of the 6th row and the 6th column. The inverter 333 and the selection transistor 354 are connected to each other by an output terminal 317. The inverter 336 and the selection transistor 351 are connected to each other by an output terminal 318. An input terminal 369 of the inverter 333 is connected to the output terminal 318 via a contact 390. An input terminal 372 of the inverter 336 is connected to the output terminal 317 via a contact 389.

    [0114] The selection transistor 352 has a gate electrode 401. The selection transistor 349 and the selection transistor 350 have a gate electrode 399. The selection transistor 353 and the selection transistor 354 have a gate electrode 402. The selection transistor 351 has a gate electrode 400.

    [0115] A contact 403 is arranged on an nMOS transistor of the inverter 319, and a contact 404 is arranged on a pMOS transistor of the inverter 319. A contact 412 is arranged on the selection transistor 340. A contact 414 is arranged on an nMOS transistor of the inverter 322, and a contact 413 is arranged on a pMOS transistor of the inverter 322. A contact 405 is arranged on the selection transistor 337. The contact 414 is also arranged on an nMOS transistor of the inverter 323, and a contact 415 is arranged on a pMOS transistor of the inverter 323. A contact 407 is arranged on the selection transistor 338. A contact 409 is arranged on an nMOS transistor of the inverter 320, and a contact 408 is arranged on a pMOS transistor of the inverter 320. A contact 416 is arranged on the selection transistor 341. The contact 409 is also arranged on an nMOS transistor of the inverter 321, and a contact 410 is arranged on a pMOS transistor of the inverter 321. A contact 418 is arranged on the selection transistor 342. A contact 420 is arranged on an nMOS transistor of the inverter 324, and a contact 419 is arranged on a pMOS transistor of the inverter 324. A contact 411 is arranged on the selection transistor 339. A contact 406 is arranged on the gate electrode 391, and a contact 417 is arranged on the gate electrode 394.
    A contact 430 is arranged on an nMOS transistor of the inverter 328, and a contact 431 is arranged on a pMOS transistor of the inverter 328. A contact 421 is arranged on the selection transistor 343. A contact 423 is arranged on an nMOS transistor of the inverter 325, and a contact 422 is arranged on a pMOS transistor of the inverter 325. A contact 432 is arranged on the selection transistor 346. The contact 423 is also arranged on an nMOS transistor of the inverter 326, and a contact 424 is arranged on a pMOS transistor of the inverter 326. A contact 434 is arranged on the selection transistor 347. A contact 436 is arranged on an nMOS transistor of the inverter 329, and a contact 435 is arranged on a pMOS transistor of the inverter 329. A contact 425 is arranged on the selection transistor 344. The contact 436 is also arranged on an nMOS transistor of the inverter 330, and a contact 437 is arranged on a pMOS transistor of the inverter 330. A contact 427 is arranged on the selection transistor 345. A contact 429 is arranged on an nMOS transistor of the inverter 327, and a contact 428 is arranged on a pMOS transistor of the inverter 327. A contact 438 is arranged on the selection transistor 348. A contact 433 is arranged on the gate electrode 397, and a contact 426 is arranged on the gate electrode 396.
    A contact 439 is arranged on an nMOS transistor of the inverter 331, and a contact 440 is arranged on a pMOS transistor of the inverter 331. A contact 448 is arranged on the selection transistor 352. A contact 450 is arranged on an nMOS transistor of the inverter 334, and a contact 449 is arranged on a pMOS transistor of the inverter 334. A contact 441 is arranged on the selection transistor 349. The contact 450 is also arranged on an nMOS transistor of the inverter 335, and a contact 451 is arranged on a pMOS transistor of the inverter 335. A contact 443 is arranged on the selection transistor 350. A contact 445 is arranged on an nMOS transistor of the inverter 332, and a contact 444 is arranged on a pMOS transistor of the inverter 332. A contact 452 is arranged on the selection transistor 353. The contact 445 is also arranged on an nMOS transistor of the inverter 333, and a contact 446 is arranged on a pMOS transistor of the inverter 333. A contact 454 is arranged on the selection transistor 354. A contact 456 is arranged on an nMOS transistor of the inverter 336, and a contact 455 is arranged on a pMOS transistor of the inverter 336. A contact 447 is arranged on the selection transistor 351. A contact 442 is arranged on the gate electrode 399, and a contact 453 is arranged on the gate electrode 402.

    [0116] A first level metal 457 is connected to the contact 403, and a first level metal 458 is connected to the contact 404. A first level metal 459 is connected to the contact 405, and a first level metal 460 is connected to the contact 406. A first level metal 461 is connected to the contact 407, and a first level metal 462 is connected to the contact 408. A first level metal 463 is connected to the contact 409, and a first level metal 464 is connected to the contact 410. A first level metal 465 is connected to the contact 411.
    A first level metal 466 is connected to the contacts 412, 421, and a first level metal 467 is connected to the contacts 413, 422. A first level metal 468 is connected to the contacts 414, 423, and a first level metal 469 is connected to the contacts 415, 424. A first level metal 470 is connected to the contacts 416, 425. A first level metal 471 is connected to the contact 417, and a first level metal 472 is connected to the contact 472. A first level metal 473 is connected to the contacts 418, 427. A first level metal 474 is connected to the contacts 419, 428, and a first level metal 475 is connected to the contacts 420, 429.
    A first level metal 476 is connected to the contacts 430, 439, and a first level metal 477 is connected to the contacts 431, 440. A first level metal 478 is connected to the contacts 432, 441. A first level metal 479 is connected to the contact 433, and a first level metal 480 is connected to the contact 442. A first level metal 481 is connected to the contacts 434, 443. A first level metal 482 is connected to the contacts 435, 444, and a first level metal 483 is connected to the contacts 436, 445. A first level metal 484 is connected to the contacts 437, 446, and a first level metal 485 is connected to the contacts 438, 447.
    A first level metal 486 is connected to the contact 448, and a first level metal 487 is connected to the contact 449. A first level metal 488 is connected to the contact 450, and a first level metal 489 is connected to the contact 451. A first level metal 490 is connected to the contact 452, and a first level metal 491 is connected to the contact 453. A first level metal 492 is connected to the contact 454, and a first level metal 493 is connected to the contact 455. A first level metal 494 is connected to the contact 456.

    [0117] A first level via 495 is arranged on the first level metal 460, and a first level via 496 is arranged on the first level metal 471. A first level via 497 is arranged on the first level metal 466, and a first level via 498 is arranged on the first level metal 467. A first level via 499 is arranged on the first level metal 468, and a first level via 500 is arranged on the first level metal 469. A first level via 501 is arranged on the first level metal 470, and a first level via 502 is arranged on the first level metal 473. A first level via 503 is arranged on the first level metal 474. A first level via 505 is arranged on the first level metal 479, and a first level via 504 is arranged on the first level metal 472. A first level via 506 is arranged on the first level metal 477, and a first level via 507 is arranged on the first level metal 478. A first level via 508 is arranged on the first level metal 481, and a first level via 509 is arranged on the first level metal 482. A first level via 510 is arranged on the first level metal 483, and a first level via 511 is arranged on the first level metal 484. A first level via 512 is arranged on the first level metal 485. A first level via 513 is arranged on the first level metal 480, and a first level via 514 is arranged on the first level metal 491.
    A second level metal 515 is connected to the first level vias 495, 496. A second level metal 516 is connected to the first level via 497, and a second level metal 517 is connected to the first level via 498. A second level metal 518 is connected to the first level via 499, and a second level metal 519 is connected to the first level via 500. A second level metal 520 is connected to the first level via 501, and a second level metal 521 is connected to the first level via 502. A second level metal 522 is connected to the first level via 503. A second level metal 523 is connected to the first level vias 505, 504.
    A second level metal 523 is connected to the first level via 506, and a second level metal 525 is connected to the first level via 507. A second level metal 526 is connected to the first level via 508, and a second level metal 527 is connected to the first level via 509. A second level metal 528 is connected to the first level via 510, and a second level metal 529 is connected to the first level via 511. A second level metal 530 is connected to the first level via 512. A second level metal 531 is connected to the first level vias 513, 514.

    [0118] A second level via 532 is arranged on the second level metal 516, and a second level via 533 is arranged on the second level metal 517. A second level via 534 is arranged on the second level metal 518, and a second level via 535 is arranged on the second level metal 519. A second level via 536 is arranged on the second level metal 520, and a second level via 537 is arranged on the second level metal 521. A second level via 538 is arranged on the second level metal 522, and a second level via 539 is arranged on the second level metal 524. A second level via 540 is arranged on the second level metal 525, and a second level via 541 is arranged on the second level metal 526. A second level via 542 is arranged on the second level metal 527, and a second level via 543 is arranged on the second level metal 528. A second level via 544 is arranged on the second level metal 529, and a second level via 545 is arranged on the second level metal 530.
    A third level metal 546 is connected to the second level via 534, and a third level metal 549 is connected to the second level via 532. A third level metal 550 is connected to the second level via 536, and a third level metal 551 is connected to the second level via 537. A third level metal 547 is connected to the second level vias 533, 535, 538, 539, 542, 544. A third level metal 552 is connected to the second level via 540, and a third level metal 553 is connected to the second level via 541. A third level metal 554 is connected to the second level via 545, and a third level metal 548 is connected to the second level via 543.

    [0119] A third level via 561 is arranged on the third level metal 549, and a third level via 564 is arranged on the third level metal 550. A third level via 565 is arranged on the third level meta! 551, and a third level via 562 is arranged on the third level metal 552. A third level via 563 is arranged on the third level metal 553, and a third level via 566 is arranged on the third level metal 554.
    A fourth level metal 555 is connected to the third level via 561, and a fourth level metal 556 is connected to the third level via 562. A fourth level metal 557 is connected to the third level via 563, and a fourth level metal 558 is connected to the third level via 564. A fourth level metal 559 is connected to the third level via 565, and a fourth level metal 560 is connected to the third level via 566.

    101: oxide film

    102: p+-type silicon layer

    103: p-type or non-doped silicon layer

    104: resist

    105: n-type or non-doped silicon layer

    106: n-type or non-doped silicon layer

    107: oxide film

    108: nitride film

    109 to 112: resist

    113 to 116: nitride film

    117 to 119: oxide film

    121: oxide film

    122 to 125: oxide film-based sidewall

    126: nitride film

    127: nitride film-based sidewall, nitride film-based hard mask

    128, 129: nitride film-based sidewall

    130: nitride film-based sidewall, nitride film-based hard mask

    131 to 136: resist

    137: first island-shaped silicon layer

    138: third island-shaped silicon layer

    139: fourth island-shaped silicon layer

    140: second island-shaped silicon layer

    141: first arc-shaped silicon layer

    142: second arc-shaped silicon layer

    143, 144: p+-type silicon layer

    145: nitride film

    146 to 151: nitride film-based sidewall

    152 to 153: resist

    154 to 159: n+-type silicon layer

    160: resist

    161 to 164: p+-type silicon layer

    165: oxide layer

    166: resist

    167: high-K film

    168: metal

    169: nitride film

    170 to 173: resist

    174 to 177: nitride film-based sidewall

    178 to 181: gate electrode

    182: nitride film

    183 to 186: nitride film-based sidewall

    187 to 190: gate dielectric film, high-K film

    191 to 194: resist

    195: nitride film-based sidewall

    196 to 205: silicon-metal compound layer

    206: interlayer film

    207, 208: contact hole

    209, 210: contact

    211: interlayer film

    212 to 219: contact hole

    220 to 227: contact

    228 to 235: first level metal

    236: interlayer film

    237: first inverter

    239: first selection transistor

    240: second inverter

    242: second selection transistor

    301 to 318: output terminal

    319 to 336: inverter

    337 to 354: selection transistor

    355 to 372: input terminal

    373 to 390: contact

    391 to 402: gate electrode

    403 to 456: contact

    457 to 494: first level metal

    495 to 514: first level via

    515 to 531: second level metal

    532 to 545: second level via

    546 to 554: third level metal

    555 to 560: fourth level via

    561 to 566: third level via




    Claims

    1. A semiconductor device characterized by comprising:

    a first inverter (237) arranged at an intersection of the 1st row and the 1st column, the first inverter (237) including a first island-shaped semiconductor layer (137), a first gate dielectric film (187) in contact with at least a part of a periphery of the first island-shaped semiconductor layer (137), a first gate electrode (178) having a first vertical surface in contact with the first gate dielectric film (187) and a second vertical surface, a second gate dielectric film (187) having a first vertical surface in contact with the second vertical surface of the first gate electrode (178) and a second vertical surface, a first arc-shaped semiconductor layer (141) in contact with at least a part of the second vertical surface of the second gate dielectric film (187), a first first-conductive-type high-concentration semiconductor layer (161) arranged on a top of the first island-shaped semiconductor layer (137), a second first-conductive-type high-concentration semiconductor layer (162) arranged underneath the first island-shaped semiconductor layer (137), a first second-conductive-type high-concentration semiconductor layer (154) arranged on a top of the first arc-shaped semiconductor layer (141), and a second second-conductive-type high-concentration semiconductor layer (156) arranged underneath the first arc-shaped semiconductor layer (141);

    a second inverter (240) arranged at an intersection of the 2nd row and the 2nd column, the second inverter (240) including a second island-shaped semiconductor layer, a third gate dielectric film in contact with at least a part of a periphery of the second island-shaped semiconductor layer, a second gate electrode (181) having a first vertical surface in contact with the third gate dielectric film and a second vertical surface, a fourth gate dielectric film having a first vertical surface in contact with the second vertical surface of the second gate electrode (181) and a second vertical surface, a second arc-shaped semiconductor layer in contact with at least a part of the second vertical surface of the fourth gate dielectric film, a third first-conductive-type high-concentration semiconductor layer arranged on a top of the second island-shaped semiconductor layer, a fourth first-conductive-type high-concentration semiconductor layer arranged underneath the second island-shaped semiconductor layer, a third second-conductive-type high-concentration semiconductor layer arranged on a top of the second arc-shaped semiconductor layer, and a fourth second-conductive-type high-concentration semiconductor layer arranged underneath the second arc-shaped semiconductor layer;

    a first selection transistor (239) arranged at an intersection of the 1st row and the 2nd column, the first selection transistor (239) including a third island-shaped semiconductor layer (138), a fifth gate dielectric film (188) in contact with at least a part of a periphery of the third island-shaped semiconductor layer (138), a third gate electrode (179) partially in contact with the fifth gate dielectric film (188), a fifth second-conductive-type high-concentration semiconductor layer (155) arranged on a top of the third island-shaped semiconductor layer (138), and a sixth second-conductive-type high-concentration semiconductor layer (157) arranged underneath the third island-shaped semiconductor layer (138); and

    a second selection transistor (242) arranged at an intersection of the 2nd row and the 1st column, the second selection transistor (242) including a fourth island-shaped semiconductor layer (139), a sixth gate dielectric film (189) in contact with at least a part of a periphery of the fourth island-shaped semiconductor layer (139), a fourth gate electrode (180) partially in contact with the sixth gate dielectric film (189), a seventh second-conductive-type high-concentration semiconductor layer (158) arranged on a top of the fourth island-shaped semiconductor layer (139), and an eighth second-conductive-type high-concentration semiconductor layer (156) arranged underneath the fourth island-shaped semiconductor layer (139).


     
    2. The semiconductor device as defined in claim 1, characterized in that:

    the first gate dielectric film (187) is surrounding a periphery of the first island-shaped semiconductor layer (137);

    the first gate electrode (178) is surrounding a periphery of the first gate dielectric film (187);

    the third gate dielectric film is surrounding a periphery of the second island-shaped semiconductor layer;

    the second gate electrode (181) is surrounding a periphery of the third gate dielectric film;

    the fifth gate dielectric film (188) is surrounding a periphery of the third island-shaped semiconductor layer (138);

    the third gate electrode (179) is surrounding a periphery of the fifth gate dielectric film (188);

    the sixth gate dielectric film (189) is surrounding a periphery of the fourth island-shaped semiconductor layer (139); and

    the fourth gate electrode (180) is surrounding a periphery of the sixth gate dielectric film (189).


     
    3. The semiconductor device as defined in claim 2, characterized by further comprising:

    a fifth first-conductive-type high-concentration semiconductor layer (143) arranged underneath the second first-conductive-type high-concentration semiconductor layer (162), the second second-conductive-type high-concentration semiconductor layer (156) and the eighth second-conductive-type high-concentration semiconductor layer (156);

    a sixth first-conductive-type high-concentration semiconductor layer (144) arranged underneath the fourth first-conductive-type high-concentration semiconductor layer, the fourth second-conductive-type high-concentration semiconductor layer and the sixth second-conductive-type high-concentration semiconductor layer (157);

    a first semiconductor-metal compound layer (204) formed on a part of respective sidewalls of the second second-conductive-type high-concentration semiconductor layer (156) and the fifth first-conductive-type high-concentration semiconductor layer (143);

    a second semiconductor-metal compound layer (201) formed on the eighth second-conductive-type high-concentration semiconductor layer (156) and the fifth first-conductive-type high-concentration semiconductor layer (143);

    a third semiconductor-metal compound layer (205) formed on a part of respective sidewalls of the fourth second-conductive-type high-concentration semiconductor layer and the sixth first-conductive-type high-concentration semiconductor layer (144);

    a fourth semiconductor-metal compound layer (198) formed on the sixth second-conductive-type high-concentration semiconductor layer (157) and the sixth first-conductive-type high-concentration semiconductor layer (144);

    a fifth semiconductor-metal compound layer (197) formed on the first first-conductive-type high-concentration semiconductor layer (161);

    a sixth semiconductor-metal compound layer (196) formed on the first second-conductive-type high-concentration semiconductor layer (154);

    a seventh semiconductor-metal compound layer formed on the third first-conductive-type high-concentration semiconductor layer;

    an eighth semiconductor-metal compound layer formed on the third second-conductive-type high-concentration semiconductor layer;

    a ninth semiconductor-metal compound layer (199) formed on the fifth second-conductive-type high-concentration semiconductor layer (155);

    a tenth semiconductor-metal compound layer (200) formed on the seventh second-conductive-type high-concentration semiconductor layer (158);

    a first contact (209) connecting the first gate electrode (178) and the fourth semiconductor-metal compound layer (198); and

    a second contact (210) connecting the second gate electrode (181) and the second semiconductor-metal compound layer (201).


     
    4. The semiconductor device as defined in claim 2, characterized in that:

    the first first-conductive-type high-concentration semiconductor layer is a first p+-type semiconductor layer (161);

    the second first-conductive-type high-concentration semiconductor layer is a second p+-type semiconductor layer (162);

    the first second-conductive-type high-concentration semiconductor layer is a first n+-type semiconductor layer (154);

    the second second-conductive-type high-concentration semiconductor layer is a second n+-type semiconductor layer (156);

    the third first-conductive-type high-concentration semiconductor layer is a third p+-type semiconductor layer;

    the fourth first-conductive-type high-concentration semiconductor layer is a fourth p+-type semiconductor layer;

    the third second-conductive-type high-concentration semiconductor layer is a third n+-type semiconductor layer;

    the fourth second-conductive-type high-concentration semiconductor layer is a fourth n+-type semiconductor layer;

    the fifth second-conductive-type high-concentration semiconductor layer is a fifth n+-type semiconductor layer (155);

    the sixth second-conductive-type high-concentration semiconductor layer is a sixth n+-type semiconductor layer (157);

    the seventh second-conductive-type high-concentration semiconductor layer is a seventh n+-type semiconductor layer (158); and

    the eighth second-conductive-type high-concentration semiconductor layer is an eighth n+-type semiconductor layer (156).


     
    5. The semiconductor device as defined in claim 4, characterized by further comprising:

    a fifth p+-type semiconductor layer (143) arranged underneath the second p+-type semiconductor layer (162), the second n+-type semiconductor layer (156) and the eighth n+-type semiconductor layer (156);

    a sixth p+-type semiconductor layer (144) arranged underneath the fourth p+-type semiconductor layer, the fourth n+-type semiconductor layer and the sixth n+-type semiconductor layer (157);

    a first semiconductor-metal compound layer (204) formed on a part of respective sidewalls of the second n+-type semiconductor layer (156) and the fifth p+-type semiconductor layer (143);

    a second semiconductor-metal compound layer (201) formed on the eighth n+-type semiconductor layer (156) and the fifth p+-type semiconductor layer (143);

    a third semiconductor-metal compound layer (205) formed on a part of respective sidewalls of the fourth n+-type semiconductor layer and the sixth p+-type semiconductor layer (144);

    a fourth semiconductor-metal compound layer (198) formed on the sixth n+-type semiconductor layer (157) and the sixth p+-type semiconductor layer (144);

    a fifth semiconductor-metal compound layer (197) formed on the first p+-type semiconductor layer (161);

    a sixth semiconductor-metal compound layer (196) formed on the first n+-type semiconductor layer (154);

    a seventh semiconductor-metal compound layer formed on the third p+-type semiconductor layer;

    an eighth semiconductor-metal compound layer formed on the third n+-type semiconductor layer;

    a ninth semiconductor-metal compound layer (199) formed on the fifth n+-type semiconductor layer (155);

    a tenth semiconductor-metal compound layer (200) formed on the seventh n+-type semiconductor layer (158);

    a first contact (209) connecting the first gate electrode (178) and the fourth semiconductor-metal compound layer (198); and

    a second contact (210) connecting the second gate electrode (181) and the second semiconductor-metal compound layer (201).


     
    6. The semiconductor device as defined in claim 4, characterized by being configured to satisfy the following condition: Wp1 ≈ 2Wn1, wherein Wp1 is an outer peripheral length of the first island-shaped semiconductor layer (137), and Wn1 is a length of an arc of the first arc-shaped semiconductor layer (141) in contact with a part of the second surface of the second gate dielectric film (187).
     
    7. The semiconductor device as defined in claim 4, characterized by being configured to satisfy the following condition: Wp2 ≈ 2Wn2, wherein Wp2 is an outer peripheral length of the second island-shaped semiconductor layer, and Wn2 is a length of an arc of the second arc-shaped semiconductor layer in contact with a part of the second surface of the fourth gate dielectric film.
     
    8. The semiconductor device as defined in claim 4, characterized by being configured to satisfy the following condition: Ln1 ≈ Lp1, wherein Ln1 is a channel length of the first arc-shaped semiconductor layer (141), and Lp1 is a channel length of the first island-shaped semiconductor layer (137).
     
    9. The semiconductor device as defined in claim 4, characterized by being configured to satisfy the following condition: Ln2 ≈ Lp2, wherein Ln2 is a channel length of the second arc-shaped semiconductor layer, and Lp2 is a channel length of the second island-shaped semiconductor layer.
     
    10. The semiconductor device as defined in claim 4, characterized in that:

    a combination of the first island-shaped semiconductor layer (137), the first gate dielectric film (187) surrounding the periphery of the first island-shaped semiconductor layer (137), the first gate electrode (178) surrounding the periphery of the first gate dielectric film (187), the first p+-type semiconductor layer (161) arranged on the top of the first island-shaped semiconductor layer (137), and the second p+-type semiconductor layer (162) arranged underneath the first island-shaped semiconductor layer (137), forms a first pMOS transistor;

    a combination of the first gate electrode (178), the second gate dielectric film (187) surrounding a part of the periphery of the first gate electrode (178), the first arc-shaped semiconductor layer (141) in contact with a part of a periphery of the second gate dielectric film (187), a first n+-type semiconductor layer (154) arranged on the top of the first arc-shaped semiconductor layer (141), and the second n+-type semiconductor layer (156) arranged underneath the first arc-shaped semiconductor layer (141), forms a first nMOS transistor;

    a combination of the second island-shaped semiconductor layer, the third gate dielectric film surrounding the periphery of the second island-shaped semiconductor layer, the second gate electrode (181) surrounding the periphery of the third gate dielectric film, the third p+-type semiconductor layer arranged on the top of the second island-shaped semiconductor layer, and the fourth p+-type semiconductor layer arranged underneath the second island-shaped semiconductor layer, forms a second pMOS transistor; and

    a combination of the second gate electrode (181), the fourth gate dielectric film surrounding a part of the periphery of the second gate electrode (181), the second arc-shaped semiconductor layer in contact with a part of the periphery of the fourth gate dielectric film, the third n+-type semiconductor layer arranged on the top of the second arc-shaped semiconductor layer, and the fourth n+-type semiconductor layer arranged underneath the second arc-shaped semiconductor layer, forms a second nMOS transistor,

    and characterized in that:

    the first gate dielectric film (187) is adapted to allow the first pMOS transistor to operate as an enhancement type;

    the second gate dielectric film (187) is adapted to allow the first nMOS transistor to operate as an enhancement type;

    the first gate electrode (178) is made of a material allowing the first pMOS transistor and the first nMOS transistor to operate as an enhancement type;

    the third gate dielectric film is adapted to allow the second pMOS transistor to operate as an enhancement type;

    the fourth gate dielectric film is adapted to allow the second nMOS transistor to operate as an enhancement type; and

    the second gate electrode (181) is made of a material allowing the second pMOS transistor and the second nMOS transistor to operate as an enhancement type.


     
    11. The semiconductor device as defined in claim 5, characterized in that each of the first to tenth semiconductor-metal compound layers is a silicon-metal compound layer.
     
    12. The semiconductor device as defined in claim 4, characterized in that:

    the first island-shaped semiconductor layer (137) is a first island-shaped silicon layer;

    the first arc-shaped semiconductor layer (141) is a first arc-shaped silicon layer;

    the second island-shaped semiconductor layer is a second island-shaped silicon layer;

    the second arc-shaped semiconductor layer is a second arc-shaped silicon layer;

    the third island-shaped semiconductor layer (138) is a third island-shaped silicon layer;

    the fourth island-shaped semiconductor layer (139) is a fourth island-shaped silicon layer;

    each of the n+-type semiconductor layers is a n+-type silicon layer; and

    each of the p+-type semiconductor layers is a p+-type silicon layer.


     
    13. The semiconductor device as defined in claim 12, characterized in that:

    the first island-shaped silicon layer (137) is a first n-type or non-doped island-shaped silicon layer;

    the first arc-shaped silicon layer (141) is a first p-type or non-doped arc-shaped silicon layer;

    the second island-shaped silicon layer is a second n-type or non-doped island-shaped silicon layer;

    the second arc-shaped silicon layer is a second p-type or non-doped arc-shaped silicon layer;

    the third island-shaped silicon layer (138) is a third p-type or non-doped island-shaped silicon layer; and

    the fourth island-shaped silicon layer (139) is a fourth p-type or non-doped island-shaped silicon layer.


     
    14. The semiconductor device as defined in claim 1, characterized in that:

    an area over which the first gate dielectric film (187) and the first gate electrode (178) are in contact with each other is larger than an area over which the second gate dielectric film (187) and the first arc-shaped semiconductor layer (141) are in contact with each other, and

    an area over which the third gate dielectric film and the second gate electrode (181) are in contact with each other is larger than an area over which the fourth gate dielectric film and the second arc-shaped semiconductor layer are in contact with each other.


     


    Ansprüche

    1. Halbleitervorrichtung, dadurch gekennzeichnet, dass sie umfasst:

    einen ersten Inverter (237), der an einer Überschneidung der ersten Zeile und der ersten Spalte angeordnet ist, wobei der erste Inverter (237) umfasst: eine erste inselförmige Halbleiterschicht (137), einen ersten Gatedielektrikum-Film (187) in Kontakt mit wenigstens einem Teil eines Randbereichs der ersten inselförmigen Halbleiterschicht (137), eine erste Gate-Elektrode (178) mit einer ersten senkrechten Oberfläche in Kontakt mit dem ersten Gatedielektrikum-Film (187) und einer zweiten senkrechten Oberfläche, einen zweiten Gatedielektrikum-Film (187) mit einer ersten senkrechten Oberfläche in Kontakt mit der zweiten senkrechten Oberfläche der ersten Gate-Elektrode (178) und einer zweiten senkrechten Oberfläche, eine erste bogenförmige Halbleiterschicht (141) in Kontakt mit wenigstens einem Teil der zweiten senkrechten Oberfläche des zweiten Gatedielektrikum-Films (187), eine erste Halbleiterschicht hoher Konzentration eines ersten Leitertyps (161), die auf einer Oberseite der ersten inselförmigen Halbleiterschicht (137) angeordnet ist, eine zweite Halbleiterschicht hoher Konzentration eines ersten Leitertyps (162), die unterhalb der ersten inselförmigen Halbleiterschicht (137) angeordnet ist, eine erste Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (154), die auf einer Oberseite der ersten bogenförmigen Halbleiterschicht (141) angeordnet ist, und eine zweite Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (156), die unterhalb der ersten bogenförmigen Halbleiterschicht (141) angeordnet ist;

    einen zweiten Inverter (240), der an einer Überschneidung der zweiten Zeile und der zweiten Spalte angeordnet ist, wobei der zweite Inverter (240) umfasst: eine zweite inselförmige Halbleiterschicht, einen dritten Gatedielektrikum-Film in Kontakt mit wenigstens einem Teil eines Randbereichs der zweiten inselförmigen Halbleiterschicht, eine zweite Gate-Elektrode (181) mit einer ersten senkrechten Oberfläche in Kontakt mit dem dritten Gatedielektrikum-Film und einer zweiten senkrechten Oberfläche, einen vierten Gatedielektrikum-Film mit einer ersten senkrechten Oberfläche in Kontakt mit der zweiten senkrechten Oberfläche der zweiten Gate-Elektrode (181) und einer zweiten senkrechten Oberfläche, eine zweite bogenförmige Halbleiterschicht in Kontakt mit wenigstens einem Teil der zweiten senkrechten Oberfläche des vierten Gatedielektrikum-Films, eine dritte Halbleiterschicht hoher Konzentration eines ersten Leitertyps, die auf einer Oberseite der zweiten inselförmigen Halbleiterschicht angeordnet ist, eine vierte Halbleiterschicht hoher Konzentration eines ersten Leitertyps, die unterhalb der zweiten inselförmigen Halbleiterschicht angeordnet ist, eine dritte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps, die auf einer Oberseite der zweiten bogenförmigen Halbleiterschicht angeordnet ist, und eine vierte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps, die unterhalb der zweiten bogenförmigen Halbleiterschicht angeordnet ist;

    einen ersten Auswahltransistor (239), der an einer Überschneidung der ersten Zeile und der zweiten Spalte angeordnet ist, wobei der erste Auswahltransistor (239) umfasst: eine dritte inselförmige Halbleiterschicht (138), einen fünften Gatedielektrikum-Film (188) in Kontakt mit wenigstens einem Teil eines Randbereichs der dritten inselförmigen Halbleiterschicht (138), eine dritte Gate-Elektrode (179) teilweise in Kontakt mit dem fünften Gatedielektrikum-Film (188), eine fünfte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (155), die auf einer Oberseite der dritten inselförmigen Halbleiterschicht (138) angeordnet ist, und eine sechste Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (157), die unterhalb der dritten inselförmigen Halbleiterschicht (138) angeordnet ist; und

    einen zweiten Auswahltransistor (242), der an einer Überschneidung der zweiten Zeile und der ersten Spalte angeordnet ist, wobei der zweite Auswahltransistor (242) umfasst: eine vierte inselförmige Halbleiterschicht (139), einen sechsten Gatedielektrikum-Film (189) in Kontakt mit wenigstens einem Teil eines Randbereichs der vierten inselförmigen Halbleiterschicht (139), eine vierte Gate-Elektrode (180) teilweise in Kontakt mit dem sechsten Gatedielektrikum-Film (189), eine siebte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (158), die auf einer Oberseite der vierten inselförmigen Halbleiterschicht (139) angeordnet ist, und eine achte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (156), die unterhalb der vierten inselförmigen Halbleiterschicht (139) angeordnet ist.


     
    2. Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass:

    der erste Gatedielektrikum-Film (187) einen Randbereich der ersten inselförmigen Halbleiterschicht (137) umgibt;

    die erste Gate-Elektrode (178) einen Randbereich des ersten Gatedielektrikum-Films (187) umgibt;

    der dritte Gatedielektrikum-Film einen Randbereich der zweiten inselförmigen Halbleiterschicht umgibt;

    die zweite Gate-Elektrode (181) einen Randbereich des dritten Gatedielektrikum-Films umgibt;

    der fünfte Gatedielektrikum-Film (188) einen Randbereich der dritten inselförmigen Halbleiterschicht (138) umgibt;

    die dritte Gate-Elektrode (179) einen Randbereich des fünften Gatedielektrikum-Films (188) umgibt;

    der sechste Gatedielektrikum-Film (189) einen Randbereich der vierten inselförmigen Halbleiterschicht (139) umgibt; und

    die vierte Gate-Elektrode (180) einen Randbereich des sechsten Gatedielektrikum-Films (189) umgibt.


     
    3. Halbleitervorrichtung nach Anspruch 2, dadurch gekennzeichnet, dass sie ferner umfasst:

    eine fünfte Halbleiterschicht hoher Konzentration eines ersten Leitertyps (143), die unterhalb der zweiten Halbleiterschicht hoher Konzentration eines ersten Leitertyps (162), der zweiten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (156) und der achten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (156) angeordnet ist;

    eine sechste Halbleiterschicht hoher Konzentration eines ersten Leitertyps (144), die unterhalb der vierten Halbleiterschicht hoher Konzentration eines ersten Leitertyps, der vierten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps und der sechsten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (157) angeordnet ist;

    eine erste Halbleiter-Metall-Kompositschicht (204), die auf einem Teil jeweiliger Seitenwände der zweiten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (156) und der fünften Halbleiterschicht hoher Konzentration eines ersten Leitertyps (143) gebildet ist;

    eine zweite Halbleiter-Metall-Kompositschicht (201), die auf der achten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (156) und der fünften Halbleiterschicht hoher Konzentration eines ersten Leitertyps (143) gebildet ist;

    eine dritte Halbleiter-Metall-Kompositschicht (205), die auf einem Teil jeweiliger Seitenwände der vierten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps und der sechsten Halbleiterschicht hoher Konzentration eines ersten Leitertyps (144) gebildet ist;

    eine vierte Halbleiter-Metall-Kompositschicht (198), die auf der sechsten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (157) und der sechsten Halbleiterschicht hoher Konzentration eines ersten Leitertyps (144) gebildet ist;

    eine fünfte Halbleiter-Metall-Kompositschicht (197), die auf der ersten Halbleiterschicht hoher Konzentration eines ersten Leitertyps (161) gebildet ist;

    eine sechste Halbleiter-Metall-Kompositschicht (196), die auf der ersten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (154) gebildet ist;

    eine siebte Halbleiter-Metall-Kompositschicht, die auf der dritten Halbleiterschicht hoher Konzentration eines ersten Leitertyps gebildet ist;

    eine achte Halbleiter-Metall-Kompositschicht, die auf der dritten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps gebildet ist;

    eine neunte Halbleiter-Metall-Kompositschicht (199), die auf der fünften Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (155) gebildet ist;

    eine zehnte Halbleiter-Metall-Kompositschicht (200), die auf der siebten Halbleiterschicht hoher Konzentration eines zweiten Leitertyps (158) gebildet ist;

    einen ersten Kontakt (209), der die erste Gate-Elektrode (178) und die vierte Halbleiter-Metall-Kompositschicht (198) verbindet; und

    einen zweiten Kontakt (210), der die zweite Gate-Elektrode (181) und die zweite Halbleiter-Metall-Kompositschicht (201) verbindet.


     
    4. Halbleitervorrichtung nach Anspruch 2, dadurch gekennzeichnet, dass:

    die erste Halbleiterschicht hoher Konzentration eines ersten Leitertyps eine erste p+-Typ-Halbleiterschicht (161) ist;

    die zweite Halbleiterschicht hoher Konzentration eines ersten Leitertyps eine zweite p+-Typ-Halbleiterschicht (162) ist;

    die erste Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine erste n+-Typ-Halbleiterschicht (154) ist;

    die zweite Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine zweite n+-Typ-Halbleiterschicht (156) ist;

    die dritte Halbleiterschicht hoher Konzentration eines ersten Leitertyps eine dritte p+-Typ-Halbleiterschicht ist;

    die vierte Halbleiterschicht hoher Konzentration eines ersten Leitertyps eine vierte p+-Typ-Halbleiterschicht ist;

    die dritte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine dritte n+-Typ-Halbleiterschicht ist;

    die vierte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine vierte n+-Typ-Halbleiterschicht ist;

    die fünfte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine fünfte n+-Typ-Halbleiterschicht (155) ist;

    die sechste Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine sechste n+-Typ-Halbleiterschicht (157) ist;

    die siebte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine siebte n+-Typ-Halbleiterschicht (158) ist; und

    die achte Halbleiterschicht hoher Konzentration eines zweiten Leitertyps eine achte n+-Typ-Halbleiterschicht (156) ist.


     
    5. Halbleitervorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass sie ferner umfasst:

    eine fünfte p+-Typ-Halbleiterschicht (143), die unterhalb der zweiten p+-Typ-Halbleiterschicht (162), der zweiten n+-Typ-Halbleiterschicht (156) und der achten n+-Typ-Halbleiterschicht (156) angeordnet ist;

    eine sechste p+-Typ-Halbleiterschicht (144), die unterhalb der vierten p+-Typ-Halbleiterschicht, der vierten n+-Typ-Halbleiterschicht und der sechsten n+-Typ-Halbleiterschicht (157) angeordnet ist;

    eine erste Halbleiter-Metall-Kompositschicht (204), die auf einem Teil jeweiliger Seitenwände der zweiten n+-Typ-Halbleiterschicht (156) und der fünften p+-Typ-Halbleiterschicht (143) gebildet ist;

    eine zweite Halbleiter-Metall-Kompositschicht (201), die auf der achten n+-Typ-Halbleiterschicht (156) und der fünften p+-Typ-Halbleiterschicht (143) gebildet ist;

    eine dritte Halbleiter-Metall-Kompositschicht (205), die auf einem Teil jeweiliger Seitenwände der vierten n+-Typ-Halbleiterschicht und der sechsten p+-Typ-Halbleiterschicht (144) gebildet ist;

    eine vierte Halbleiter-Metall-Kompositschicht (198), die auf der sechsten n+-Typ-Halbleiterschicht (157) und der sechsten p+-Typ-Halbleiterschicht (144) gebildet ist;

    eine fünfte Halbleiter-Metall-Kompositschicht (197), die auf der ersten p+-Typ-Halbleiterschicht (161) gebildet ist;

    eine sechste Halbleiter-Metall-Kompositschicht (196), die auf der ersten n+-Typ-Halbleiterschicht (154) gebildet ist;

    eine siebte Halbleiter-Metall-Kompositschicht, die auf der dritten p+-Typ-Haibieiterschicht gebildet ist;

    eine achte Halbleiter-Metall-Kompositschicht, die auf der dritten n+-Typ-Halbleiterschicht gebildet ist;

    eine neunte Halbleiter-Metall-Kompositschicht (199), die auf der fünften n+-Typ-Halbleiterschicht (155) gebildet ist;

    eine zehnte Halbleiter-Metall-Kompositschicht (200), die auf der siebten n+-Typ-Halbleiterschicht (158) gebildet ist;

    einen ersten Kontakt (209), der die erste Gate-Elektrode (178) und die vierte Halbleiter-Metall-Kompositschicht (198) verbindet; und

    einen zweiten Kontakt (210), der die zweite Gate-Elektrode (181) und die zweite Halbleiter-Metall-Kompositschicht (201) verbindet.


     
    6. Halbleitervorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass sie dazu ausgebildet ist, die folgende Bedingung zu erfüllen: Wp1 ≈ 2Wn1, wobei Wp1 eine Länge eines äußeren Umfangs der ersten inselförmigen Halbleiterschicht (137) ist und Wn1 eine Länge eines Bogens der ersten bogenförmigen Halbleiterschicht (141) in Kontakt mit einem Teil der zweiten Oberfläche des zweiten Gatedielektrikum-Films (187) ist.
     
    7. Halbleitervorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass sie dazu ausgebildet ist, die folgende Bedingung zu erfüllen: Wp2 ≈ 2Wn2, wobei Wp2 eine Länge eines äußeren Umfangs der zweiten inselförmigen Halbleiterschicht ist und Wn2 eine Länge eines Bogens der zweiten bogenförmigen Halbleiterschicht in Kontakt mit einem Teil der zweiten Oberfläche des vierten Gatedielektrikum-Films ist.
     
    8. Halbleitervorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass sie dazu ausgebildet ist, die folgende Bedingung zu erfüllen: Ln1 ≈ Lp1, wobei Ln1 eine Kanallänge der ersten bogenförmigen Halbleiterschicht (141) ist und Lp1 eine Kanallänge der ersten inselförmigen Halbleiterschicht (137) ist.
     
    9. Halbleitervorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass sie dazu gebildet ist, die folgende Bedingung zu erfüllen: Ln2 ≈ Lp2, wobei Ln2 eine Kanallänge der zweiten bogenförmigen Halbleiterschicht ist und Lp2 eine Kanallänge der zweiten inselförmigen Halbleiterschicht ist.
     
    10. Halbleitervorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass:

    eine Kombination aus der ersten inselförmigen Halbleiterschicht (137), dem ersten Gatedielektrikum-Film (187), der den Randbereich der ersten inselförmigen Halbleiterschicht (137) umgibt, der ersten Gate-Elektrode (178), die den Randbereich des ersten Gatedielektrikum-Films (187) umgibt, der ersten p+-Typ-Halbleiterschicht (161), die auf der Oberseite der ersten inselförmigen Halbleiterschicht (137) angeordnet ist, und der zweiten p+-Typ-Halbleiterschicht (162), die unterhalb der ersten inselförmigen Halbleiterschicht (137) angeordnet ist, einen ersten pMOS-Transistor bildet;

    eine Kombination aus der ersten Gate-Elektrode (178), dem zweiten Gatedielektrikum-Film (187), der einen Teil des Randbereichs der ersten Gate-Elektrode (178) umgibt, der ersten bogenförmigen Halbleiterschicht (141) in Kontakt mit einem Teil eines Randbereichs des zweiten Gatedielektrikum-Films (187), einer ersten n+-Typ-Halbleiterschicht (154), die auf der Oberseite der ersten bogenförmigen Halbleiterschicht (141) angeordnet ist, und der zweiten n+-Typ-Halbleiterschicht (156), die unterhalb der ersten bogenförmigen Halbleiterschicht (141) angeordnet ist, einen ersten nMOS-Transistor bildet;

    eine Kombination aus der zweiten inselförmigen Halbleiterschicht, dem dritten Gatedielektrikum-Film, der den Randbereich der zweiten inselförmigen Halbleiterschicht umgibt, der zweiten Gate-Elektrode (181), die den Randbereich des dritten Gatedielektrikum-Films umgibt, der dritten p+-Typ-Halbleiterschicht, die auf der Oberseite der zweiten inselförmigen Halbleiterschicht angeordnet ist, und der vierten p+-Typ-Halbleiterschicht, die unterhalb der zweiten inselförmigen Halbleiterschicht angeordnet ist, einen zweiten pMOS-Transistor bildet; und

    eine Kombination aus der zweiten Gate-Elektrode (181), dem vierten Gatedielektrikum-Film, der einen Teil des Randbereichs der zweiten Gate-Elektrode (181) umgibt, der zweiten bogenförmigen Halbleiterschicht in Kontakt mit einem Teil des Randbereichs des vierten Gatedielektrikum-Films, der dritten n+-Typ-Halbleiterschicht, die auf der Oberseite der zweiten bogenförmigen Halbleiterschicht angeordnet ist, und der vierten n+-Typ-Halbleiterschicht, die unterhalb der zweiten bogenförmigen Halbleiterschicht angeordnet ist, einen zweiten nMOS-Transistor bildet,

    und dadurch gekennzeichnet, dass:

    der erste Gatedielektrikum-Film (187) so ausgebildet ist, dass der erste pMOS-Transistor als ein Verstärkungstyp betrieben werden kann;

    der zweite Gatedielektrikum-Film (187) so ausgebildet ist, dass der erste nMOS-Transistor als ein Verstärkungstyp betrieben werden kann;

    die erste Gate-Elektrode (178) aus einem Material gefertigt ist, welches gestattet, dass der erste pMOS-Transistor und der erste nMOS-Transistor als ein Verstärkungstyp betrieben werden können;

    der dritte Gatedielektrikum-Film so ausgebildet ist, dass der zweite pMOS-Transistor als ein Verstärkungstyp betrieben werden kann;

    der vierte Gatedielektrikum-Film so ausgebildet ist, dass der zweite nMOS-Transistor als ein Verstärkungstyp betrieben werden kann; und

    die zweite Gate-Elektrode (181) aus einem Material gefertigt ist, welches gestattet, dass der zweite pMOS-Transistor und der zweite nMOS-Transistor als ein Verstärkungstyp betrieben werden können.


     
    11. Halbleitervorrichtung nach Anspruch 5, dadurch gekennzeichnet, dass jede der ersten bis zehnten Halbleiter-Metall-Kompositschichten eine Silizium-Metall-Kompositschicht ist.
     
    12. Halbleitervorrichtung nach Anspruch 4, dadurch gekennzeichnet, dass:

    die erste inselförmige Halbleiterschicht (137) eine erste inselförmige Siliziumschicht ist;

    die erste bogenförmige Halbleiterschicht (141) eine erste bogenförmige Siliziumschicht ist;

    die zweite inselförmige Halbleiterschicht eine zweite inselförmige Siliziumschicht ist;

    die zweite bogenförmige Halbleiterschicht eine zweite bogenförmige Siliziumschicht ist;

    die dritte inselförmige Halbleiterschicht (138) eine dritte inselförmige Siliziumschicht ist;

    die vierte inselförmige Halbleiterschicht (139) eine vierte inselförmige Siliziumschicht ist;

    jede der n+-Typ-Halbleiterschichten eine n+-Typ-Siliziumschicht ist; und

    jede der p+-Typ-Halbleiterschichten eine p+-Typ-Siliziumschicht ist.


     
    13. Halbleitervorrichtung nach Anspruch 12, dadurch gekennzeichnet, dass:

    die erste inselförmige Siliziumschicht (137) eine erste n-Typ- oder nichtdotierte inselförmige Siliziumschicht ist;

    die erste bogenförmige Siliziumschicht (141) eine erste p-Typ- oder nichtdotierte bogenförmige Siliziumschicht ist;

    die zweite inselförmige Siliziumschicht eine zweite n-Typ- oder nichtdotierte inselförmige Siliziumschicht ist;

    die zweite bogenförmige Siliziumschicht eine zweite p-Typ- oder nichtdotierte bogenförmige Siliziumschicht ist;

    die dritte inselförmige Siliziumschicht (138) eine dritte p-Typ- oder nichtdotierte inselförmige Siliziumschicht ist; und

    die vierte inselförmige Siliziumschicht (139) eine vierte p-Typ- oder nichtdotierte inselförmige Siliziumschicht ist.


     
    14. Halbleitervorrichtung nach Anspruch 1, dadurch gekennzeichnet, dass:

    eine Fläche, auf der der erste Gatedielektrikum-Film (187) und die erste Gate-Elektrode (178) miteinander in Kontakt sind, größer ist als eine Fläche, auf der der zweite Gatedielektrikum-Film (187) und die erste bogenförmige Halbleiterschicht (141) miteinander in Kontakt sind, und

    eine Fläche, auf der der dritte Gatedielektrikum-Film und die zweite Gate-Elektrode (181) miteinander in Kontakt sind, größer ist als eine Fläche, auf der der vierte Gatedielektrikum-Film und die zweite bogenförmige Halbleiterschicht miteinander in Kontakt sind.


     


    Revendications

    1. Dispositif à semi-conducteur caractérisé en ce qu'il comprend :

    un premier inverseur (237) disposé au niveau d'une intersection de la première rangée et de la première colonne, le premier inverseur (237) incluant une première couche semi-conductrice (137) en forme d'îlot, un premier film diélectrique (187) de grille en contact avec au moins une partie d'une périphérie de la première couche semi-conductrice (137) en forme d'îlot, une première électrode de grille (178) comportant une première surface verticale en contact avec le premier film diélectrique (187) de grille et une deuxième surface verticale, un deuxième film diélectrique (187) de grille comportant une première surface verticale en contact avec la deuxième surface verticale de la première électrode de grille (178) et une deuxième surface verticale, une première couche semi-conductrice (141) en forme d'arc en contact avec au moins une partie de la deuxième surface verticale du deuxième film diélectrique (187) de grille, une première couche semi-conductrice (161) à concentration élevée d'un premier type de conduction disposée sur le dessus de la première couche semi-conductrice (137) en forme d'îlot, une deuxième couche semi-conductrice (162) à concentration élevée d'un premier type de conduction disposée en dessous de la première couche semi-conductrice (137) en forme d'îlot, une première couche semi-conductrice (154) à concentration élevée d'un deuxième type de conduction disposée sur le dessus de la première couche semi-conductrice (141) en forme d'arc, et une deuxième couche semi-conductrice (156) à concentration élevée d'un deuxième type de conduction disposée en dessous de la première couche semi-conductrice (141) en forme d'arc ;

    un deuxième inverseur (240) disposé au niveau d'une intersection de la deuxième rangée et de la deuxième colonne, le deuxième inverseur (240) incluant une deuxième couche semi-conductrice en forme d'îlot, un troisième film diélectrique de grille en contact avec au moins une partie d'une périphérie de la deuxième couche semi-conductrice en forme d'îlot, une deuxième électrode de grille (181) comportant une première surface verticale en contact avec le troisième film diélectrique de grille et une deuxième surface verticale, un quatrième film diélectrique de grille comportant une première surface verticale en contact avec la deuxième surface verticale de la deuxième électrode de grille (181) et une deuxième surface verticale, une deuxième couche semi-conductrice en forme d'arc en contact avec au moins une partie de la deuxième surface verticale du quatrième film diélectrique de grille, une troisième couche semi-conductrice à concentration élevée d'un premier type de conduction disposée sur le dessus de la deuxième couche semi-conductrice en forme d'îlot, une quatrième couche semi-conductrice à concentration élevée d'un premier type de conduction disposée en dessous de la deuxième couche semi-conductrice en forme d'îlot, une troisième couche semi-conductrice à concentration élevée d'un deuxième type de conduction disposée sur le dessus de la deuxième couche semi-conductrice en forme d'arc, et une quatrième couche semi-conductrice à concentration élevée d'un deuxième type de conduction disposée en dessous de la deuxième couche semi-conductrice en forme d'arc ;

    un premier transistor (239) de sélection disposé au niveau d'une intersection de la première rangée et de la deuxième colonne, le premier transistor (239) de sélection incluant une troisième couche semi-conductrice (138) en forme d'îlot, un cinquième film diélectrique (188) de grille en contact avec au moins une partie d'une périphérie de la troisième couche semi-conductrice (138) en forme d'îlot, une troisième électrode de grille (179) partiellement en contact avec le cinquième film diélectrique (188) de grille, une cinquième couche semi-conductrice (155) à concentration élevée d'un deuxième type de conduction disposée sur le dessus de la troisième couche semi-conductrice (138) en forme d'îlot, et une sixième couche semi-conductrice (157) à concentration élevée d'un deuxième type de conduction disposée en dessous de la troisième couche semi-conductrice (138) en forme d'îlot ; et

    un deuxième transistor (242) de sélection disposé au niveau d'une intersection de la deuxième rangée et de la première colonne, le deuxième transistor (242) de sélection incluant une quatrième couche semi-conductrice (139) en forme d'îlot, un sixième film diélectrique (189) de grille en contact avec au moins une partie d'une périphérie de la quatrième couche semi-conductrice (139) en forme d'îlot, une quatrième électrode de grille (180) partiellement en contact avec le sixième film diélectrique (189) de grille, une septième couche semi-conductrice (158) à concentration élevée d'un deuxième type de conduction disposée sur le dessus de la quatrième couche semi-conductrice (139) en forme d'îlot, et une huitième couche semi-conductrice (156) à concentration élevée d'un deuxième type de conduction disposée en dessous de la quatrième couche semi-conductrice (139) en forme d'îlot.


     
    2. Dispositif à semi-conducteur selon la revendication 1, caractérisé en ce que :

    le premier film diélectrique (187) de grille entoure une périphérie de la première couche semi-conductrice (137) en forme d'îlot ;

    la première électrode de grille (178) entoure une périphérie du premier film diélectrique (187) de grille ;

    le troisième film diélectrique de grille entoure une périphérie de la deuxième couche semi-conductrice en forme d'îlot ;

    la deuxième électrode de grille (181) entoure une périphérie du troisième film diélectrique de grille ;

    le cinquième film diélectrique (188) de grille entoure une périphérie de la troisième couche semi-conductrice (138) en forme d'îlot ;

    la troisième électrode de grille (179) entoure une périphérie du cinquième film diélectrique (188) de grille ;

    le sixième film diélectrique (189) de grille entoure une périphérie de la quatrième couche semi-conductrice (139) en forme d'îlot ; et

    la quatrième électrode de grille (180) entoure une périphérie du sixième film diélectrique (189) de grille.


     
    3. Dispositif à semi-conducteur selon la revendication 2, caractérisé en ce qu'il comprend :

    une cinquième couche semi-conductrice (143) à concentration élevée d'un premier type de conduction disposée en dessous de la deuxième couche semi-conductrice (162) à concentration élevée d'un premier type de conduction, de la deuxième couche semi-conductrice (156) à concentration élevée d'un deuxième type de conduction et de la huitième couche semi-conductrice (156) à concentration élevée d'un deuxième type de conduction ;

    une sixième couche semi-conductrice (144) à concentration élevée d'un premier type de conduction disposée en dessous de la quatrième couche semi-conductrice à concentration élevée d'un premier type de conduction, de la quatrième couche semi-conductrice à concentration élevée d'un deuxième type de conduction et de la sixième couche semi-conductrice (157) à concentration élevée d'un deuxième type de conduction ;

    une première couche (204) de composé de métal semi-conducteur formée sur une partie des parois latérales respectives de la deuxième couche semi-conductrice (156) à concentration élevée d'un deuxième type de conduction et de la cinquième couche semi-conductrice (143) à concentration élevée d'un premier type de conduction ;

    une deuxième couche (201) de composé de métal semi-conducteur formée sur la huitième couche semi-conductrice (156) à concentration élevée d'un deuxième type de conduction et la cinquième couche semi-conductrice (143) à concentration élevée d'un premier type de conduction ;

    une troisième couche (205) de composé de métal semi-conducteur formée sur une partie des parois latérales respectives de la quatrième couche semi-conductrice à concentration élevée d'un deuxième type de conduction et de la sixième couche semi-conductrice (144) à concentration élevée d'un premier type de conduction ;

    une quatrième couche (198) de composé de métal semi-conducteur formée sur la sixième couche semi-conductrice (157) à concentration élevée d'un deuxième type de conduction et la sixième couche semi-conductrice (144) à concentration élevée d'un premier type de conduction ;

    une cinquième couche (197) de composé de métal semi-conducteur formée sur la première couche semi-conductrice (161) à concentration élevée d'un premier type de conduction ;

    une sixième couche (196) de composé de métal semi-conducteur formée sur la première couche semi-conductrice (154) à concentration élevée d'un deuxième type de conduction ;

    une septième couche de composé de métal semi-conducteur formée sur la troisième couche semi-conductrice à concentration élevée d'un premier type de conduction ;

    une huitième couche de composé de métal semi-conducteur formée sur la troisième couche semi-conductrice à concentration élevée d'un deuxième type de conduction ;

    une neuvième couche (199) de composé de métal semi-conducteur formée sur la cinquième couche semi-conductrice (155) à concentration élevée d'un deuxième type de conduction ;

    une dixième couche (200) de composé de métal semi-conducteur formée sur la septième couche semi-conductrice (158) à concentration élevée d'un deuxième type de conduction ;

    un premier contact (209) connectant la première électrode de grille (178) et la quatrième couche (198) de composé de métal semi-conducteur ; et

    un deuxième contact (210) connectant la deuxième électrode de grille (181) et la deuxième couche (201) de composé de métal semi-conducteur.


     
    4. Dispositif à semi-conducteur selon la revendication 2, caractérisé en ce que :

    la première couche semi-conductrice à concentration élevée d'un premier type de conduction est une première couche semi-conductrice (161) de type p+ ;

    la deuxième couche semi-conductrice à concentration élevée d'un premier type de conduction est une deuxième couche semi-conductrice (162) de type p+ ;

    la première couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une première couche semi-conductrice (154) de type n+ ;

    la deuxième couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une deuxième couche semi-conductrice (156) de type n+ ;

    la troisième couche semi-conductrice à concentration élevée d'un premier type de conduction est une troisième couche semi-conductrice de type p+ ;

    la quatrième couche semi-conductrice à concentration élevée d'un premier type de conduction est une quatrième couche semi-conductrice de type p+ ;

    la troisième couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une troisième couche semi-conductrice de type n+ ;

    la quatrième couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une quatrième couche semi-conductrice de type n+ ;

    la cinquième couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une cinquième couche semi-conductrice (155) de type n+ ;

    la sixième couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une sixième couche semi-conductrice (157) de type n+ ;

    la septième couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une septième couche semi-conductrice (158) de type n+ ; et

    la huitième couche semi-conductrice à concentration élevée d'un deuxième type de conduction est une huitième couche semi-conductrice (156) de type n+.


     
    5. Dispositif à semi-conducteur selon la revendication 4, caractérisé en ce qu'il comprend en outre :

    une cinquième couche semi-conductrice (143) de type p+ disposée en dessous de la deuxième couche semi-conductrice (162) de type p+, de la deuxième couche semi-conductrice (156) de type n+ et de la huitième couche semi-conductrice (156) de type n+ ;

    une sixième couche semi-conductrice (144) de type p+ disposée en dessous de la quatrième couche semi-conductrice de type p+, de la quatrième couche semi-conductrice de type n+ et de la sixième couche semi-conductrice (157) de type n+ ;

    une première couche (204) de composé de métal semi-conducteur formée sur une partie des parois latérales respectives de la deuxième couche semi-conductrice de type n+ (156) et de la cinquième couche semi-conductrice (143) de type p+ ;

    une deuxième couche (201) de composé de métal semi-conducteur formée sur la huitième couche semi-conductrice (156) de type n+ et la cinquième couche semi-conductrice (143) de type p+ ;

    une troisième couche (205) de composé de métal semi-conducteur formée sur une partie des parois latérales respectives de la quatrième couche semi-conductrice de type n+ et de la sixième couche semi-conductrice (144) de type p+ ;

    une quatrième couche (198) de composé de métal semi-conducteur formée sur la sixième couche semi-conductrice (157) de type n+ et la sixième couche semi-conductrice (144) de type p+ ;

    une cinquième couche (197) de composé de métal semi-conducteur formée sur la première couche semi-conductrice (161) de type p+ ;

    une sixième couche (196) de composé de métal semi-conducteur formée sur la première couche semi-conductrice (154) de type n+ ;

    une septième couche de composé de métal semi-conducteur formée sur la troisième couche semi-conductrice de type p+ ;

    une huitième couche de composé de métal semi-conducteur formée sur la troisième couche semi-conductrice de type n+ ;

    une neuvième couche (199) de composé de métal semi-conducteur formée sur la cinquième couche semi-conductrice (155) de type n+ ;

    une dixième couche (200) de composé de métal semi-conducteur formée sur la septième couche semi-conductrice (158) de type n+ ;

    un premier contact (209) connectant la première électrode de grille (178) et la quatrième couche (198) de composé de métal semi-conducteur ; et

    un deuxième contact (210) connectant la deuxième électrode de grille (181) et la deuxième couche (201) de composé de métal semi-conducteur.


     
    6. Dispositif à semi-conducteur selon la revendication 4, caractérisé en ce qu'il est configuré pour satisfaire la condition suivante : Wp1 ≈ 2Wn1, où Wp1 représente une longueur périphérique externe de la première couche semi-conductrice (137) en forme d'îlot, et Wn1 représente une longueur d'un arc de la première couche semi-conductrice (141) en forme d'arc en contact avec une partie de la deuxième surface du deuxième film diélectrique (187) de grille.
     
    7. Dispositif à semi-conducteur selon la revendication 4, caractérisé en ce qu'il est configuré pour satisfaire la condition suivante : Wp2 ≈ 2Wn2, où Wp2 représente une longueur périphérique externe de la deuxième couche semi-conductrice en forme d'îlot, et Wn2 représente une longueur d'un arc de la deuxième couche semi-conductrice en forme d'arc en contact avec une partie de la deuxième surface du quatrième film diélectrique de grille.
     
    8. Dispositif à semi-conducteur selon la revendication 4, caractérisé en ce qu'il est configuré pour satisfaire la condition suivante : Ln1 ≈ Lp1, où Ln1 représente une longueur de canal de la première couche semi-conductrice (141) en forme d'arc, et Lp1 représente une longueur de canal de la première couche semi-conductrice (137) en forme d'îlot.
     
    9. Dispositif à semi-conducteur selon la revendication 4, caractérisé en ce qu'il est configuré pour satisfaire la condition suivante : Ln2 ≈ Lp2, où Ln2 représente une longueur de canal de la deuxième couche semi-conductrice en forme d'arc, et Lp2 représente une longueur de canal de la deuxième couche semi-conductrice en forme d'îlot.
     
    10. Dispositif à semi-conducteur selon la revendication 4, caractérisé en ce que :

    une combinaison de la première couche semi-conductrice (137) en forme d'îlot, du premier film diélectrique (187) de grille entourant la périphérie de la première couche semi-conductrice (137) en forme d'îlot, de la première électrode de grille (178) entourant la périphérie du premier film diélectrique (187) de grille, de la première couche semi-conductrice (161) de type p+ disposée sur le dessus de la première couche semi-conductrice (137) en forme d'îlot, et de la deuxième couche semi-conductrice (162) de type p+ disposée en dessous de la première couche semi-conductrice (137) en forme d'îlot, forme un premier transistor pMOS ;

    une combinaison de la première électrode de grille (178), du deuxième film diélectrique (187) de grille entourant une partie de la périphérie de la première électrode de grille (178), de la première couche semi-conductrice (141) en forme d'arc en contact avec une partie d'une périphérie du deuxième film diélectrique (187) de grille, d'une première couche semi-conductrice (154) de type n+ disposée sur le dessus de la première couche semi-conductrice (141) en forme d'arc, et de la deuxième couche semi-conductrice (156) de type n+ disposée en dessous de la première couche semi-conductrice (141) en forme d'arc, forme un premier transistor nMOS ;

    une combinaison de la deuxième couche semi-conductrice en forme d'îlot, du troisième film diélectrique de grille entourant la périphérie de la deuxième couche semi-conductrice en forme d'îlot, de la deuxième électrode de grille (181) entourant la périphérie du troisième film diélectrique de grille, de la troisième couche semi-conductrice de type p+ disposée sur le dessus de la deuxième couche semi-conductrice en forme d'îlot, et de la quatrième couche semi-conductrice de type p+ disposée en dessous de la deuxième couche semi-conductrice en forme d'îlot, forme un deuxième transistor pMOS ; et

    une combinaison de la deuxième électrode de grille (181), du quatrième film diélectrique de grille entourant une partie de la périphérie de la deuxième électrode de grille (181), de la deuxième couche semi-conductrice en forme d'arc en contact avec une partie de la périphérie du quatrième film diélectrique de grille, de la troisième couche semi-conductrice de type n+ disposée sur le dessus de la deuxième couche semi-conductrice en forme d'arc, et de la quatrième couche semi-conductrice de type n+ disposée en dessous de la deuxième couche semi-conductrice en forme d'arc, forme un deuxième transistor nMOS,

    et caractérisé en ce que :

    le premier film diélectrique (187) de grille est adapté pour permettre au premier transistor pMOS de fonctionner comme un type à enrichissement ;

    le deuxième film diélectrique (187) de grille est adapté pour permettre au premier transistor nMOS de fonctionner comme un type à enrichissement ;

    la première électrode de grille (178) est constituée d'un matériau permettant au premier transistor pMOS et au premier transistor nMOS de fonctionner comme un type à enrichissement ;

    le troisième film diélectrique de grille est adapté pour permettre au deuxième transistor pMOS de fonctionner comme un type à enrichissement ;

    le quatrième film diélectrique de grille est adapté pour permettre au deuxième transistor nMOS de fonctionner comme un type à enrichissement ; et

    la deuxième électrode de grille (181) est constituée d'un matériau permettant au deuxième transistor pMOS et au deuxième transistor nMOS de fonctionner comme un type à enrichissement.


     
    11. Dispositif à semi-conducteur selon la revendication 5, caractérisé en ce que chacune des première à dixième couche de composé de métal semi-conducteur est une couche de composé de silicium-métal.
     
    12. Dispositif à semi-conducteur selon la revendication 4, caractérisé en ce que :

    la première couche semi-conductrice (137) en forme d'îlot est une première couche de silicium en forme d'îlot ;

    la première couche semi-conductrice (141) en forme d'arc est une première couche de silicium en forme d'arc ;

    la deuxième couche semi-conductrice en forme d'îlot est une deuxième couche de silicium en forme d'îlot ;

    la deuxième couche semi-conductrice en forme d'arc est une deuxième couche de silicium en forme d'arc ;

    la troisième couche semi-conductrice (138) en forme d'îlot est une troisième couche de silicium en forme d'îlot ;

    la quatrième couche semi-conductrice (139) en forme d'îlot est une quatrième couche de silicium en forme d'îlot ;

    chacune des couches semi-conductrices de type n+ est une couche de silicium de type n+ ; et

    chacune des couches semi-conductrices de type p+ est une couche de silicium de type p+.


     
    13. Dispositif à semi-conducteur selon la revendication 12, caractérisé en ce que :

    la première couche de silicium (137) en forme d'îlot est une première couche de silicium en forme d'îlot de type n ou non dopée ;

    la première couche de silicium (141) en forme d'arc est une première couche de silicium en forme d'arc de type p ou non dopée ;

    la deuxième couche de silicium en forme d'îlot est une deuxième couche de silicium en forme d'îlot de type n ou non dopée ;

    la deuxième couche de silicium en forme d'arc est une deuxième couche de silicium en forme d'arc de type p ou non dopée ;

    la troisième couche de silicium (138) en forme d'îlot est une troisième couche de silicium en forme d'îlot de type p ou non dopée ; et

    la quatrième couche de silicium (139) en forme d'îlot est une quatrième couche de silicium en forme d'îlot de type p ou non dopée.


     
    14. Dispositif à semi-conducteur selon la revendication 1, caractérisé en ce que :

    une zone sur laquelle le premier film diélectrique (187) de grille et la première électrode de grille (178) sont en contact l'un avec l'autre est plus grande qu'une zone sur laquelle le deuxième film diélectrique (187) de grille et la première couche semi-conductrice (141) en forme d'arc sont en contact l'un avec l'autre, et

    une zone sur laquelle le troisième film diélectrique de grille et la deuxième électrode de grille (181) sont en contact l'un avec l'autre est plus grande qu'une zone sur laquelle le quatrième film diélectrique de grille et la deuxième couche semi-conductrice en forme d'arc sont en contact l'un avec l'autre.


     




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    Cited references

    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description




    Non-patent literature cited in the description