(19)
(11)EP 2 276 178 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
05.06.2013 Bulletin 2013/23

(21)Application number: 10181897.9

(22)Date of filing:  26.01.1996
(51)Int. Cl.: 
H03M 13/27  (2006.01)

(54)

Data transmission with interleaving through in-place addressing of RAM memory

Datenübertragung mit Verschachtelung durch in-place Addressierung eines RAM Speichers

Transmission de données avec entrelacement par addressage en place d'une mémoire RAM


(84)Designated Contracting States:
DE DK GB IT NL SE

(30)Priority: 01.02.1995 EP 95200242
03.03.1995 EP 95200520
09.03.1995 EP 95200580
16.03.1995 EP 95200642

(43)Date of publication of application:
19.01.2011 Bulletin 2011/03

(62)Application number of the earlier application in accordance with Art. 76 EPC:
05110959.3 / 1635474
02075867.8 / 1239596
96900404.3 / 0760182

(73)Proprietor: Sony Corporation
Tokyo 108-0075 (JP)

(72)Inventor:
  • Baggen, Constant
    5600 AE, Eindhoven (NL)

(74)Representative: DeVile, Jonathan Mark 
D Young & Co LLP 120 Holborn
London EC1N 2DY
London EC1N 2DY (GB)


(56)References cited: : 
EP-A1- 0 578 313
US-A- 4 881 241
US-A- 4 394 642
US-A- 5 056 105
  
  • OKADA M ET AL: "A novel concatenated block coded modulation scheme in Rayleigh fading channel", 44TH IEEE VEHICULAR TECHNOLOGY CONFERENCE, STOCKHOLM, SWEDEN, 8-10 JUNE 1994, 8 June 1994 (1994-06-08), pages 967-971, XP010123219, DOI: 10.1109/VETEC.1994.345235 ISBN: 978-0-7803-1927-1
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description


[0001] The invention relates to a method of transmission and reception of data, a transmission system for the transmission and reception of data, a transmitting section and receiving section for such a system.

[0002] A method and system of this kind is known from the book "Error correction coding for digital communications" by G.C. Clark and J.B. Cain, Plenum Press New York, 1981, sections 8.5 and 83.2.

[0003] The cited book describes a system which is intended to counteract jamming. This is achieved by a spread spectrum technique, which involves greatly expanding the transmit spectrum relative to the data rate. The idea is that this forces the jammer to deploy his power over a much wider bandwidth than would be necessary for an unspread spectrum.

[0004] The anti-jamming system modulates the information successively at different frequencies. As a function of time, the frequency "hops" from one frequency channel to another. To protect against jammed channels the information is encoded in an error correction code prior to modulation In addition, the encoded information is interleaved: the time sequential order in which the data-items are modulated is permuted with respect to the order in which they succeed each other in the error protection code. In the prior art technique, interleaving serves to make the anti-jamming system more robust against pulses that jam all frequency channels for part of the time.

[0005] The described system makes very inefficient use of the frequencies available. This forces the jammer to deploy his power over a much wider bandwidth and is therefore essential for anti-jamming as described in the book by G.C. Clark and J.B. Cain.

[0006] US 4,394,642 discloses an interleaver and de-interleaver which is arranged to respectively interleave and de-interleave data bits which have been error connection encoded to improve the integrity of the data bits during transmission. The encoded data is written into a memory row-wise and read-out column-wise to interleave the data in a conventional arrangement. An arrangements of the interleaver which reduces the amount of memory space in the interleaver memory by half allows an address counter and an address memory to write data bits into the interleaver memory at locations from which previous entries have been just read from.

[0007] EP 0578313 discloses a receiver comprising an OFDM demodulator and a frequency-deinterleaver, which is adapted to de-interleave modulation symbols from the active carriers of an OFDM symbol using a formulaic expression for the address of the de-interleaved symbol P(i) where i is the position of the symbol after de-interleaving in which P(i) = mod (100 + P(i-1), 900/+1 where P(1) = 1, 2 ≤ i ≤ 900 for 900 active carrier of the OFDM symbol.

[0008] It is inter alia an object of the invention to apply pseudo random interleaving to applications which make more efficient use of the frequencies available.

[0009] It is a further object of the invention to provide for multichannel broadcasting which is robust against degradation due to multipath transmission and which makes efficient use of the frequencies available.

[0010] The invention provides for a method of transmission and reception of data, the method comprising:
  • a transmitting step comprising transmitting data-items that are encoded according to a convolution error correcting code and subsequently pseudo-random interleaved, the data-items being transmitted modulated in a number of simultaneously active frequency channels;
  • a receiving step comprising receiving, de-interleaving and decoding the transmitted data-items according to the convolution error correcting code,
characterized in that the de-interleaving comprises writing the received data-items into locations in a memory in an order of writing, and reading the data-items in a de-interleaved order of reading, de-interleaving being performed in successive versions of a basic cycle, the data-items for a version of the basic cycle being written in the locations as the locations become available on reading for a directly preceding version of the basic cycle, the order of writing the data-items in successive cycles being alternately an order of locations with monotonously ascending or descending addresses and an order with addresses permuted according to a pseudo random function, the data-items being interleaved so as to provide an inverse of the de-interleaving. As a result of the simultaneous transmission of information in a number of frequency channels, the frequencies available are efficiently used. The invention addresses the problem of transmission channels that may suffer from multipath transmission rather than from jamming. In the case of wireless broadcasting, for example indirect transmission may occur in addition to direct transmission of electromagnetic radiation, for example due to reflection of the radiation by a building. It has been found that this often leads to variations in the receivability of the various frequency channels. Moreover, it has been found that this variation is often periodic, i.e. it recurs as a function of the frequency after a number of channels. The recurrent period is dependent on the receiving conditions and, generally speaking, it cannot be predicted.

[0011] The use of pseudo-random interleaving prevents multipath transmission from causing burst errors that are so long that they cannot be corrected.

[0012] Thus, interleaving is performed by writing data items into a memory and by subsequently reading the data items therefrom in a different order. New data is then written into memory locations vacated by reading before all other locations have been read, which makes it possible to save memory space. For monotonously ascending address series this is known per se from US 5,151,976. The invention, however, applies this operation to the writing according to a pseudo- random sequence. Despite the fact that such a pseudo-random sequence is far more complex than a monotonous series, it has been found that notably the use of direct writing after reading with random sequences can be used for interleaving.

[0013] In an embodiment of the method of the invention the memory addresses are selected alternately as a monotonously ascending or descending order and as the pseudo random function of that order. By using only two different series of addresses in an alternating fashion, interleaving is simplified.

[0014] In an embodiment of the invention, the addresses are calculated according to a linear congruential sequence satisfying

n being the position of a particular data-item in the second order, Xn being the address from which that particular data-item is read, M being the number of selectable memory locations, a and c being a factor and a summand for a linear congruential sequence respectively, the combination of the factor and the summand used being changed for each version of the basic cycle. The factor a and summand c for linear congruential sequences are such that c is a relative prime with respect to M, a-1 is a multiple of all primes factors of M, and a-1 is a multiple of 4 if m is a multiple of 4. This provides for a simple way of generating the addresses. In particular it has been found that, when all "a" used for different versions are such that the square of (a-1) is divisible by M, it is ensured that all orders of addresses which are successively required to read data-item that have been written in the order of locations in which the preceding data-items have been read, can always be generated in correspondence with this formula.

[0015] The invention also related to a method of receiving data, and to a system for applying the method and its components, to which similar measures can be applied mutatis mutandis to obtain similar advantages.

[0016] These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.

[0017] In the drawings:

Fig. 1 shows a transmission system;

Fig. 2 shows an embodiment of an interleaver;

Fig. 3 shows a further embodiment of an interleaver; and

Fig. 4 shows an embodiment of an address generator.

Fig. 5 shows an embodiment of the transmitting section according to the invention



[0018] Fig. 1 shows a transmission system. It comprises a cascade connection of successively an encoder 10, an interleaver 12, a modulator 14, a transmission channel, a demodulator 16, a de-interleaver 18 and a decoder 20.

[0019] During use data is presented to an input of the encoder 10. The encoder 10 encodes this data in an error correction code. Any known error correction code, for example a convolution code, can be used for this purpose. The encoded data is composed of, for example blocks, each of which contains a logic succession of bits.

[0020] The decoder 20 corresponds to the encoder 10 and corrects bit errors incurred during transmission from the encoder 10 to the decoder 20. The error correction code is such that bit errors which occur distributed throughout the logic succession can be readily corrected. Burst errors, where a number of successive bits in the logic succession are incorrect, can be less readily corrected when they are too long.

[0021] The modulator 14 produces a signal with a number of frequency channels which are simultaneously transmitted. The bits of each block are distributed among a number of groups. Each group corresponds to a frequency channel and the information of the bits in a group is transmitted in the corresponding frequency channel. This can be realised, for example by interpreting the bits of each group as a number, by arranging these numbers in a series and making an FFT (fast Fourier transform) of the series. The result of the FFT is subsequently transmitted via the transmission channel, for example a wireless terrestrial broadcast channel. FFT and transmission are repeated for successive blocks. This corresponds to the known OFDM (orthogonal frequency division multiplexing) technique.

[0022] The demodulator 16 corresponds to the modulator 14. The demodulator receives the various frequency channels simultaneously and reconstructs the groups of bits transmitted in a respective frequency channel. According to the OFDM technique, this is performed, for example by making an inverse FFT of the signal received and by reconstructing the numbers and hence the groups therefrom.

[0023] The interleaver 12 serves to ensure that bits which are directly adjacent in the logic succession are substantially always modulated in different frequency channels. The spacing of these channels (in terms of channels with intermediate frequencies) is preferably larger than zero, so that adjacent bits will enter non-adjacent channels. This serves to ensure that a disturbance of a single channel, or of a number of neighbouring channels, does not lead to burst errors in the logic succession.

[0024] The de-interleaver 18 corresponds to the interleaver 12 and performs the reverse operation, so that the logic succession is reconstructed in terms of order (i.e. except for bit errors) before being presented to the decoder 20.

[0025] The interleaver 12 places every adjacent pair of bits, which succeed one another in the logic succession, at a respective distance, amounting to a number of channels, from one another. The respective distances have different values and it is ensured that the various distances occur approximately equally frequently. As a result, the system is robust to disturbances of the transmission channel which lead to poor reception in a periodic system of frequency channels (in this context a periodic system is to be understood to mean a system in which the poor reception recurs as a function of the frequency each time after the same number of channels).

[0026] All other pairs of bits which are so near to one another that a simultaneous error in the bits of such a pair could give rise to burst problems are also placed at a respective distance of a number of channels from one another. These respective distances preferably also have different values and it is ensured that these different distances occur approximately equally frequently.

[0027] Fig. 2 shows an embodiment of an interleaver; this device is also suitable as a de-interleaver. The interleaver of Fig. 2 comprises a data input 42 which is coupled, via a multiplexer 34, to respective data inputs/outputs of a first and a second memory 30, 32. The data inputs/outputs of the memories 30, 32 are also coupled, via the multiplexer 34, to an output 44 of the interleaver.

[0028] The interleaver also comprises a clock input 37, coupled to clock inputs of a first and a second address generator 38, 40. The output of each of the address generators is coupled to a further multiplexer 36. The outputs of the further multiplexer 36 are coupled to a respective address input of the first and the second memory 38, 40.

[0029] During operation the interleaver is switched to and fro between two modes. In a first mode the multiplexer 34 couples the input 42 to the data input of the first memory 30 and the output 44 to the data output of the second memory 32. Furthermore, the further multiplexer 36 couples the output of the first address generator to the address input of the first memory 30 and the output of the second address generator 40 to the address input of the second memory 32. In the second mode the roles of the first and the second memory 30, 32 are reversed in comparison with the first mode.

[0030] The first address generator 38 generates a clocked first series of addresses. The various data items presented to the input 42 during successive clock cycles are written at these addresses. Data is read from the second memory 32 in a similar manner, addressed by a second series of addresses from the second address generator, and applied to the output 44. The first and the second series of addresses deviate from one another, resulting in interleaving.

[0031] The first series of addresses is, for example a monotonously ascending series (1, 2, 3 ...) and the second series of addresses is a pseudo-random series, for example a series in which a respective difference exists between each pair of directly successively generated addresses; these respective differences have various values and it is ensured that the various values occur approximately equally frequently. The differences correspond to the distances between the frequency channels in which successive bits of the logic succession are arranged.

[0032] The corresponding de-interleaver has the same structure as shown in Fig. 2, be it that the first address generator of the de-interleaver generates the same address series as the second address generator of the interleaver and vice versa.

[0033] The pseudo-random series can be generated by assembling the address generator 40 from a counter and a ROM, successive pseudo-random addresses being stored in successive locations in the ROM. Alternatively, use can be made of a known linear congruent series, the addresses Xn for the memory 32 being obtained by way of the recursion relation



[0034] These addresses can be obtained by multiplication and addition, without utilizing a ROM. A further alternative consists in the use of an LFSR (Linear Feedback Shift Register).

[0035] Fig. 3 shows a further embodiment of an interleaver. This embodiment comprises only one memory 56. The input and the output of the interleaver are coupled to a data input and a data output, respectively, of this memory 56. The interleaver also comprises a clock input 50 which is coupled to an address generator 54. An output of the address generator 54 is coupled to an address input of the memory 56. The clock input 50 is also coupled, via a read/write control unit 52, to a read/write control input of the memory.

[0036] The address generator 54 generates a series of addresses during operation. For each address a first data item is read from the memory 56 so as to be applied to the output; subsequently, the read/write control circuit switches the memory to the write mode and a data item originating from the input is written into the memory at the same address.

[0037] The address generator 54 each time generates such a series of addresses. Each series contains substantially the same addresses. The order in which the addresses succeed one another in directly successive series, however, differs each time. For example, alternately a pseudo-random series (X1, X2, X3 ... xn) and a normal monotonously ascending series (1, 2, 3 ... N) can be taken. This results in interleaving with a substantially uniform distribution of the differences between successive addresses.

[0038] By using only two different series of addresses in an alternating fashion, de-interleaving is simplified (same two series, so that each time the data items are written in the de-interleaver in memory locations which correspond to the locations wherefrom they have been read in the interleaver). However, this approach has the drawback that the method of interleaving is often repeated, so that the transmission system becomes susceptible to systematic disturbances.

[0039] Therefore, as an attractive alternative it is possible to use more than two different series and to repeat the pattern of series of addresses used only after more than two complete series. To this end, for broadcast applications a linear congruential sequence is preferably used at the receiving side in the de-interleaver, because such a sequence can be simply implemented. At the transmission side, for example an interleaver comprising a ROM is then used, the ROM containing the inverse permutation of what the de-interleaver contains at the receiving side. Given the permutation realised by the interleaver, this inverse permutation can be calculated, for example numerically. If a recurrent pattern of mutually different series of addresses is used in the de-interleaver, including a monotonously ascending series (1, 2, 3), this inverse permutation requires only a limited amount of space in the memory ROM.

[0040] When different address series are used, a synchronization signal is desirable between the receiving side and the transmission side, so that the de-interleaver can start the pattern of series of addresses in the correct phase (so as to serve as the inverse of the interleaver). For this purpose use is preferably made of a transmitted synchronization signal which also serves to mark header information for the further processing of the encoded symbol.

[0041] Fig. 4 shows an embodiment of an address generator 54 for use in an interleaver as shown in Fig. 2 or 3. The address generator 54 comprises a register 60, an output of which is coupled to the output of the address generator and to a first multiplicand multiplier 62. The output of the multiplier 62 is coupled to a first summand input of an adder 64. The output of the adder 64 is coupled to an input of the register 60. The address generator comprises a factor memory 63 and a summand memory 65 which are coupled, by way of an output, to a second multiplicand input of the multiplier 62 and to a second summand input of the adder 64, respectively.

[0042] During operation the register 60 contains the address Xn for the memory. Using the multiplier 62 and the adder 64, the next address is calculated in conformity with the formula

where M is the length of the address series. The factor "a" and the summand "c" are derived from the factor memory 63 and the summand memory 65, respectively. Between successive series the memories 63, 65 receive signals, whereby another factor and/or summand is applied to the multiplier and the adder, so that subsequently a different series is generated. In one of the series, for example a=1 and c=1, resulting in a monotonously ascending series. In the other series a is then unequal to 1 and is chosen, in a manner which is known per se, so as to generate a pseudo-random sequence (c relative prime with respect to M, a-1 is a multiple of p for all primes p sharing M (e.g. if M=45=3*3*5 then a-1 must be a multiple of both 3 and 5) and a-1 is a multiple of 4 if M is a multiple of 4).

[0043] By storing a number of different usable values of a and c, a corresponding number of different series of addresses can be generated

[0044] Preferably, the "a" values are selected only such that (a-1) squared is divisible by "M", i.e. such that (a-1) contains each prime factor of m at least half as many times as "M" itself (for example when M=675=3*3*3*5*5, (a-1) could be 45=3*3*5, in general large M values with several prime factors are required: of the M values of 1 to 20 only M=8, 9, 12, 16, 18 qualify). It can be proven that, when only "a" values having the property that the square of (a-1) is divisble by M are used for generating the addresses, any pseudo random permutation of the bits described by the formula Xn+1= (a Xn + c) mod M can be realized with an "a" value that also satisfies this condition. Also it has been found that both the addresses for interleaving and deinterleaving can then be realized with such pseudo random permutations in that case. Hence no address ROM is needed It has been found that this is true only when the square of (a-1) is divisible by M. In this case the addresses need not be calculated by actually calulating the formula Xn+1= (a Xn + c) mod M. In stead, one may use Xn+1= Xn+vn mod m; vn+1= vn+d mod m, with d=c(a-1), and v0 initialized to (a-1)X0+c. (For example, when M=100(=2*2*5*5), "a" may be chosen as 21 (a-1=4*5) and c=1).

[0045] When the modulus M with which the multiplier and adder operate is made adjustable, the interleaver/de-interleaver can be simply switched between different block lengths.

[0046] Evidently, the invention is not restricted to the embodiments given. For example, instead of operating with bits it is also possible to operate with larger symbols, for as long as the error correction code is capable of correcting random and isolated errors in these symbols better than random errors in the form of a burst.

[0047] Furthermore, the logic succession of bits produced by the encoder is not necessarily a temporal succession. Bits are "logically successive" if simultaneous errors in these bits can be corrected less readily than simultaneous errors in "non-logically successive" bits.

[0048] The inner frequency interleaving is a pseudo-random bit interleaving. The interleaving is on a block basis, i.e., the bits in each OFDM symbol are permuted in a fixed way such that bursts are randomized. However, bits of a given OFDM symbol are not mixed with bits originating from any other OFDM symbol.

[0049] In a practical example, an OFDM symbol consists ofN useful subcarriers, where N equals 6361 or 5937, that each contain 2, 4 or 6 bits of information. The task of the interleaver is to decorrelate the bits at the input of a Viterbi detector.

[0050] The (de)interleaver consists of a memory (RAM) having the size of 8 times 8192 bit and an addressing unit. The addressing unit generates a 16 bit address that can be distinguished in 3 lsb bits and 13 msb bits. The 13 msb bits determine a particular subchannel, while the 3 lsb bits determine which bit from a given subchannel. Each time as the RAM is addressed, the contents are read and put forward to the downstreamdecoder and the next bit at the input is written in the current location. At each cycle, all relevant locations must be addressed. The three lsb bits periodically go through relevant states (dependent on the number of bits per symbol), while the 13 msb bits are generated by an algorithm producing all relevant addresses in a special sequence.

[0051] Since 6361 is prime and 5937 is divisible by three, the lsb addresses can be generated in pairs, an algorithm is defined that works for 2 bits of information per subcarrier and this algorithm is used 1, 2 or 3 times dependent on the number of bits per symbol, each time with a different fixed offset on the lsb. In this way it is assured that all bits will be addressed under all circumstances before the addressing unit will be in the same state.

[0052] One way of producing a periodic interleaver would be to generate the consecutive addresses xt,n, 0 ≤ n < N of the 13 msb bits in the OFDM symbol at time t according to:


with xt,0 = 0 V t and GCD(ct,N) = 1. The increment ct depends on the time t. For a periodic interleaver, we can choose
ct = ct-1 * c0 mod N, where c0 is a judiciously chosen initial increment that corresponds to the actually realized interleave depth.

[0053] In summary, the invention relates to a transmission system, which comprises an encoder, an interleaver, a modulator, a transmission channel, a demodulator a deinterleaver and a decoder. The encoder is used for encoding a data block in an error correction code containing a logic succession of data items. The decoder is used for correcting errors in the transmission between the encoder and the decoder. The error correction code is more robust to errors which occur simultaneously and in an isolated fashion in the logic succession than to errors which occur simultaneously and in the form of a burst therein. The modulator is used for generating a signal which comprises a number of frequency channels to be transmitted simultaneously, each of the frequency channels corresponding to a group which comprises at least one of the data items and is modulated in the respective channel. The transmission channel is located between the modulator and the demodulator. The demodulator reconstructs the groups and applies the groups to the decoder. The interleaver distributes the data items between the groups and introduces a pseudo-random relationship between the logic succession and the distribution between the successive frequency channels. The de-interleaver reconstructs the logic succession from the groups reconstructed by the demodulator, before presentation to the decoder.

[0054] This transmission system can be improved when the interleaver and/or the de-interleaver realise the distribution by way of a non-monotonous linear congruential sequence.

[0055] The transmission system can be further improved when the interleaver and/or the de-interleaver are provided with a memory for the data items and with write and read means, the write means writing each time a data item in a location of the memory which has just been read before the read means read a data item from a next location of the memory, and in which an order of locations in which the logic succession is written differs for successive logic successions.

[0056] A further improvement concerns a transmission system in which the orders are periodically recurrent with a period of at least two blocks in which one monotonously ascending or descending order occurs. Also the write and/or read means may comprise an address generator which is arranged to form a linear congruential sequence with a factor and a summand, and also arranged to replace the factor and/or the summand from one block to another.

[0057] Thus information can be transmitted by the following steps:
  • encoding the data in an error correction code
  • interleaving the data according to a pseudo-random sequence
  • modulating the data in a series of frequency channels, data items which cannot be corrected together being arranged in separate frequency channels by interleaving,
  • demodulating the data
  • de-interleaving the data
  • decoding the data.


[0058] Fig. 5 shows an embodiment of the transmitting section according to the invention. The transmitting section contains a data bus 70 and a address bus 71 connecting a memory 72, a processor 76 and a transmitter 78. An encoder 74 is coupled to the data bus 70. The encoder 74 is coupled to the address bus 71 via an address generation unit 75.

[0059] In operation, the encoder 74 receives the data block and encodes it as a succession of bits. Each successive bit is fed to the data bus 70, and the presence of the bit is signalled to the address generator 75. The address generator 75 generates a respective address for each successive bit according to the pseudo random sequence. The address indicates both a word location in the memory 72 and a bit location within the word location. The word location corresponds to the group to which the bit is assigned, and the bit location corresponds to the location of the bit within the group. The address generator 75 ensures that bits which are logically adjacent are substantially always stored in different word locations. The spacing of these word locations is preferably larger than zero, so that logically adjacent bits will enter non-adjacent word locations.

[0060] The address is applied to the data bus and the bit is stored in the memory 72 at a location that corresponds to the address generated for it by the address generator 75. When the entire data block has thus been encoded in the error protecting code, and stored in the memory 72, the processor 76 is started. The processor 76 computes the FFT of the words stored in memory 72. For this purpose, it reads the words each time as they are needed for the FFT algorithm. For this purpose a known FFT algorithm can be used, which addresses the word locations of the memory 72 in a normal way, i.e. without requiring knowledge of the interleaving process. Because the bits which are logically adjacent have substantially always stored in different word locations, these adjacent bits are modulated in different frequency channels in the result of the FFT. This result is subsequently read by the transmitter 78 and transmitted via the transmission channel (not shown).

[0061] A structure similar to that of Fig. 5 can be used for the receiving section, with a receiver replacing the transmitter 78 and a decoder replacing encoder 74. In this case the receiver writes words into memory 72 and the processor 76 performs an FFT on this words. Address generator 75 effects the pseudo random interleaving, issuing successive word/bit address pairs to read out the results of the FFT bit by bit for error correction by the decoder.


Claims

1. A receiving apparatus for receiving transmitted data-items which have been interleaved, modulated onto a number of simultaneously active frequency channels, and received via a transmission channel, the receiving apparatus comprising
a reception input for receiving a signal including the transmitted data-items from the transmission channel;
a demodulator (16) for demodulating the data-items from the simultaneously active frequency channels of the signal;
de-interleaver (18, 52, 54, 56) for de-interleaving the logical position of the particular data-item received from a respective logical succession of the frequency channel from which the particular data-item was demodulated to reverse an interleaved order of the data items; the de-interleaver comprising an address generator (54), a memory (56) and a read/write controller (52), the read/write controller (52) and the address generator (54) being configured to write the received data-items into locations in the memory (56) in an order of writing, and to read the data-items in a de-interleaved order of reading, the writing of the data items into the memory (56) being in accordance with a first series of addresses of the memory generated by the address generator (54), and the reading of the data items from the memory (56) being in accordance with a second series of addresses of the memory (56) generated by the address generator (54), the first series of addresses being one of a monotonously ascending or descending series of addresses or addresses generated using a pseudo random function, and the second series of addresses being the other of a monotonously ascending or descending series of addresses or addresses generated using a pseudo random function, wherein the received signal represents the number of frequency channels which have been simultaneously_ transmitted, each of the frequency channels being demodulated to provide a group of data-items, and the de-interleaver is configured to generate each of the addresses to identify in the most significant address bits one of the frequency channels from which the data-items are to_be de-interleaved and in the least significant bits a location of the data-item in the group to de-interleave the groups of data-item to form an encoded block of data-items for error correction decoding.
 
2. A receiving apparatus as claimed in Claim 1, wherein the encoded block of data-items have been encoded by a transmitter in accordance with an error correction code, which is more robust against errors that are separate from each other than against errors that occur in a burst in the respective logic succession, the receiving apparatus comprising
a decoder for decoding the data-items received according to the error correcting code applied to the logic sequence as obtained by the de-interleaver (18, 52, 54, 56).
 
3. A receiving apparatus as claimed in Claim 1, wherein the read/write controller (52) and the address generator (54) are configured
upon reception from the demodulator (16), to write the data items from each particular version of the basic cycle into the memory (56) in an order of writing addresses for the particular version; and
to read the data items for that particular version from the memory in an order of reading addresses for the particular version, permuted according to a pseudo random function with respect to the order writing addresses for the particular version, the writing the data-items of the particular version at addresses as these addresses come available during reading of the data items of a directly preceding version of the basic cycle.
 
4. A receiving apparatus as claimed in Claim 1, wherein the address generator (52, 54) is configured to generate the orders of writing and reading addresses, the order of reading addresses in the particular version of the basic cycle being permuted with respect to the order of reading addresses used in a directly preceding version of the basic cycle according to the pseudo random function, the pseudo random function being particular to the version of the basic cycle; the address generator (54) generating the order of reading and writing addresses periodically, each order of reading addresses recurring each time after a period of exactly two versions of the basic cycle, the order of reading addresses being alternately a monotonously ascending or descending order of addresses and an order in which the addresses for reading are permuted according to the pseudo random function.
 
5. A receiving method for reception of data with data items which have been interleaved and modulated onto a number of simultaneously active frequency channels, the receiving method comprising
receiving the data items from a transmission channel, demodulating the data items from the simultaneously active frequency channels and de-interleaving the transmitted data to reverse an interleaved order of the data items; wherein the de-interleaving comprises
writing the received data-items into locations in a memory in an order of writing; and
reading the data-items in a de-interleaved order of reading from the memory in an order of reading, wherein the interleaved order of the transmitted data provides an inverse of de-interleaving, the writing including
writing the received data-items into locations in the memory in accordance with a first series of addresses of the memory, and the reading including
reading the data-items from the memory in accordance with a second series of addresses of the memory, the first series of addresses being one of a monotonously ascending or descending series of addresses or addresses generated using a pseudo random function, and the second series of addresses being the other of a monotonously ascending or descending series of addresses or addresses generated using a pseudo random function, wherein the receiving the data items includes receiving a signal representing the number of frequency channels which have been simultaneously transmitter, and the de-modulating comprising demodulating each of the frequency channels to provide a group of data-items, and the de-interleaving comprising
generating each address to identify in the most significant address bits one of the frequency channels from which the data-items are to be de-interleaved and in the least significant bits a location of the data-item in the group to be de-interleaved, and
de-interleaving the groups of data-items using the generated addresses to form an encoded block of data-items for error correction decoding.
 
6. A receiving method as claimed in Claim 5, wherein the encoded block of data-items have been encoded by a transmitter in accordance with an error correction code, which is more robust against errors that are separate from each other than against errors that occur in a burst in the respective logic succession, the method comprising
decoding the data-items received according to the error correcting code applied to the logic sequence as obtained by the de-interleaver (18, 52, 54, 56).
 
7. A receiving method as claimed in Claim 5, wherein the de-interleaving comprises de-interleaving in successive versions of a basic cycle, and the writing the data items into the memory comprises
writing the data items from each particular version of the basic cycle into a memory in an order of writing in accordance with the first series of addresses for the particular version; and the reading the data items from the memory comprises
reading the data items for that particular version from the memory in an order of reading in accordance with the second series of addresses for the particular version, permuted according to a pseudo random function with respect to the order writing addresses for the particular version, the writing including writing the data-items of the particular version at addresses as these addresses come available during reading of the data items of a directly preceding version of the basic cycle.
 
8. A receiving method as claimed in Claim 5, wherein the de-interleaving includes
using an address generating means (52, 54) to generate the orders of writing and reading addresses, the order of reading addresses in the particular version of the basic cycle being permuted with respect to the order of reading addresses used in a directly preceding version of the basic cycle according to the pseudo random function, the pseudo random function being particular to the version of the basic cycle; the address generating means generating the order of reading and writing addresses periodically, each order of reading addresses recurring each time after a period of exactly two versions of the basic cycle, the order of reading addresses being alternately a monotonously ascending or descending order of addresses and an order in which the addresses for reading are permuted according to the pseudo random function.
 


Ansprüche

1. Empfangsvorrichtung zum Empfangen von gesendeten Datenposten, die verschachtelt, auf eine Anzahl gleichzeitig aktiver Frequenzkanäle moduliert und über einen Übertragungskanal empfangen wurden, wobei die Empfangsvorrichtung Folgendes umfasst:

einen Empfangs-Eingang zum Empfangen eines Signals, das die gesendeten Datenposten umfasst, von dem Übertragungskanal;

einen Demodulator (16) zum Demodulieren der Datenposten aus den gleichzeitig aktiven Frequenzkanälen des Signals;

einen Entschachteler (18, 52, 54, 56) zum Entschachteln der logischen Position des bestimmten aus einer jeweiligen logischen Abfolge empfangenen Datenpostens des Frequenzkanals, aus dem der bestimmte Datenposten demoduliert wurde, um eine verschachtelte Reihenfolge der Datenposten umzukehren; wobei der Entschachteler einen Adressengenerator (54), einen Speicher (56) und eine Lese-/Schreibsteuerung (52) umfasst, die Lese-/Schreibsteuerung (52) und der Adressengenerator (54) dafür ausgelegt sind, die empfangenen Datenposten in Speicherstellen in dem Speicher (56) in einer Reihenfolge des Schreibens zu schreiben und die Datenposten in einer entschachtelten Reihenfolge des Lesens zu lesen, das Schreiben der Datenposten in den Speicher (56) gemäß einer ersten Reihe von Adressen des Speichers, die durch den Adressengenerator (54) erzeugt wird, und das Lesen der Datenposten aus dem Speicher (56) gemäß einer zweiten Reihe von Adressen des Speichers (56), die durch den Adressengenerator (54) erzeugt wird, erfolgt, die erste Reihe von Adressen eine einer monoton zunehmenden oder abnehmenden Reihe von Adressen oder unter Verwendung einer Pseudozufallsfunktion erzeugte Adressen ist und die zweite Reihe von Adressen das andere einer monoton zunehmenden oder abnehmenden Reihe von Adressen oder unter Verwendung einer Pseudozufallsfunktion erzeugte Adressen ist und wobei das empfangene Signal die Anzahl von Frequenzkanälen repräsentiert, die gleichzeitig gesendet wurden, jeder der Frequenzkanäle demoduliert wird, um eine Gruppe von Datenposten bereitzustellen, und der Entschachteler dafür ausgelegt ist, jede der Adressen zu erzeugen, um in den höchstwertigen Adressbit einen der Frequenzkanäle zu identifizieren, aus dem die Datenposten zu entschachteln sind, und in den niedrigstwertigen Bit eine Speicherstelle des Datenpostens in der Gruppe zum Entschachteln der Gruppen von Datenposten, um einen codierten Block von Datenposten zur Fehlerkorrekturdecodierung zu bilden.


 
2. Empfangsvorrichtung nach Anspruch 1, wobei der codierte Block von Datenposten durch einen Sender gemäß einem Fehlerkorrekturcode codiert wurde, der gegenüber Fehlern, die voneinander getrennt sind, robuster als gegenüber Fehlern, die in einem Burst in der jeweiligen logischen Abfolge auftreten, ist, wobei die Empfangsvorrichtung Folgendes umfasst:

einen Decoder zum Decodieren der empfangenen Datenposten gemäß dem Fehlerkorrekturcode, der auf die logische Sequenz angewandt wird, so, wie sie durch den Entschachteler (18, 52, 54, 56) erhalten wird.


 
3. Empfangsvorrichtung nach Anspruch 1, wobei die Lese-/Schreibsteuerung (52) und der Adressengenerator (54) dafür ausgelegt sind,
beim Empfang von dem Demodulator (16) die Datenposten aus jeder bestimmten Version des Grundzyklus in einer Reihenfolge von Schreibadressen für die bestimmte Version in den Speicher (56) zu schreiben; und
die Datenposten für diese bestimmte Version aus dem Speicher in einer Reihenfolge von Leseadressen für die bestimmte Version zu lesen, die gemäß einer Pseudozufallsfunktion mit Bezug auf die Reihenfolge-Schreibadressen für die bestimmte Version permutiert ist, wobei das Schreiben der Datenposten der bestimmten Version an Adressen, sowie diese Adressen während des Lesens der Datenposten einer direkt vorausgehenden Version des Grundzyklus verfügbar werden.
 
4. Empfangsvorrichtung nach Anspruch 1, wobei der Adressengenerator (52, 54) dafür ausgelegt ist, die Reihenfolgen der Schreib- und Leseadressen zu erzeugen, die Reihenfolge von Leseadressen in der bestimmten Version des Grundzyklus mit Bezug auf die Reihenfolge von Leseadressen, die in einer direkt vorausgehenden Version des Grundzyklus verwendet wird, gemäß der Pseudozufallsfunktion permutiert ist, die Pseudozufallsfunktion der Version des Grundzyklus eigen ist; der Adressengenerator (54) die Reihenfolge der Lese- und Schreibadressen periodisch erzeugt, jede Reihenfolge von Leseadressen jedes Mal nach einer Periode von genau zwei Versionen des Grundzyklus wieder auftritt und die Reihenfolge von Leseadressen alternativ eine monoton zunehmende oder abnehmende Reihenfolge von Adressen und eine Reihenfolge, in der die Adressen zum Lesen gemäß der Pseudozufallsfunktion permutiert sind, ist.
 
5. Empfangsverfahren zum Empfang von Daten mit Datenposten, die verschachtelt und auf eine Anzahl gleichzeitig aktiver Frequenzkanäle moduliert wurden, wobei das Empfangsverfahren Folgendes umfasst:

Empfangen der Datenposten von einem Übertragungskanal, Demodulieren der Datenposten aus den gleichzeitig aktiven Frequenzkanälen und Entschachteln der gesendeten Daten, um eine verschachtelte Reihenfolge der Datenposten umzukehren; wobei das Entschachteln Folgendes umfasst:

Schreiben der empfangenen Datenposten in Speicherstellen in einem Speicher in einer Reihenfolge des Schreibens; und

Lesen der Datenposten in einer entschachtelten Reihenfolge des Lesens aus dem Speicher in einer Reihenfolge des Lesens, wobei die verschachtelte Reihenfolge der gesendeten Daten eine Umkehrung des Entschachtelns bereitstellt, wobei das Schreiben Folgendes umfasst:

Schreiben der empfangenen Datenposten in Speicherstellen in dem Speicher gemäß einer ersten Reihe von Adressen des Speichers, und das Lesen Folgendes umfasst:

Lesen der Datenposten aus dem Speicher gemäß einer zweiten Reihe von Adressen des Speichers, wobei die erste Reihe von Adressen eine einer monoton zunehmenden oder abnehmenden Reihe von Adressen oder unter Verwendung einer Pseudozufallsfunktion erzeugte Adressen ist und die zweite Reihe von Adressen das andere einer monoton zunehmenden oder abnehmenden Reihe von Adressen oder unter Verwendung einer Pseudozufallsfunktion erzeugte Adressen ist, wobei das Empfangen der Datenposten das Empfangen eines Signals umfasst, das die Anzahl von Frequenzkanälen, die gleichzeitig gesendet wurden, repräsentiert, und das Demodulieren das Demodulieren jedes der Frequenzkanäle umfasst, um eine Gruppe von Datenposten bereitzustellen, und das Entschachteln Folgendes umfasst:

Erzeugen jeder Adresse, um in den höchstwertigen Adressbit einen der Frequenzkanäle zu identifizieren, aus dem die Datenposten zu entschachteln sind, und in den niedrigstwertigen Bit einen Ort des Datenpostens in der zu entschachtelnden Gruppe und

Entschachteln der Gruppe von Datenposten unter Verwendung der erzeugten Adressen, um einen codierten Block von Datenposten zur Fehlerkorrekturdecodierung zu bilden.


 
6. Empfangsverfahren nach Anspruch 5, wobei der codierte Block von Datenposten durch einen Sender gemäß einem Fehlerkorrekturcode codiert wurde, der gegenüber Fehlern, die voneinander getrennt sind, robuster ist als gegenüber Fehlern, die in einem Burst in der jeweiligen logischen Abfolge auftreten, wobei das Verfahren Folgendes umfasst:

Decodieren der empfangenen Datenposten gemäß dem Fehlerkorrekturcode, der auf die logische Sequenz angewandt wird, so, wie sie durch den Entschachteler (18, 52, 54, 56) erhalten wird.


 
7. Empfangsverfahren nach Anspruch 5, wobei das Entschachteln das Entschachteln in sukzessiven Versionen eines Grundzyklus umfasst und das Schreiben der Datenposten in den Speicher Folgendes umfasst:

Schreiben der Datenposten aus jeder bestimmten Version des Grundzyklus in einen Speicher in einer Reihenfolge des Schreibens gemäß der ersten Reihe von Adressen für die bestimmte Version; und das Lesen der Datenposten aus dem Speicher Folgendes umfasst:

Lesen der Datenposten für diese bestimmte Version aus dem Speicher in einer Reihenfolge des Lesens gemäß der zweiten Reihe von Adressen für die bestimmte Version, die gemäß einer Pseudozufallsfunktion mit Bezug auf die Reihenfolge-Schreibadressen für die bestimmte Version permutiert ist, wobei das Schreiben das Schreiben der Datenposten der bestimmten Version an Adressen umfasst, sowie diese Adressen während des Lesens der Datenposten einer direkt vorausgehenden Version des Grundzyklus verfügbar werden.


 
8. Empfangsverfahren nach Anspruch 5, wobei das Entschachteln Folgendes umfasst:

Verwenden eines Adressenerzeugungsmittels (52, 54) zum Erzeugen der Reihenfolgen von Schreib- und Leseadressen, wobei die Reihenfolge von Leseadressen in der bestimmten Version des Grundzyklus mit Bezug auf die Reihenfolge von Leseadressen, die in einer direkt vorausgehenden Version des Grundzyklus verwendet wird, gemäß der Pseudozufallsfunktion permutiert ist,

wobei die Pseudozufallsfunktion der Version des Grundzyklus eigen ist; das Adressenerzeugungsmittel die Reihenfolge von Lese- und Schreibadressen periodisch erzeugt, jede Reihenfolge von Leseadressen jedes Mal nach einer Periode von exakt zwei Versionen des Grundzyklus wieder auftritt und die Reihenfolge von Leseadressen alternativ eine monoton zunehmende oder abnehmende Reihenfolge von Adressen und eine Reihenfolge, in der die Adressen zum Lesen gemäß der Pseudozufallsfunktion permutiert sind, ist.


 


Revendications

1. Appareil de réception destiné à recevoir des éléments de données transmis ayant été entrelacés, modulés sur un certain nombre de canaux de fréquence simultanément actifs, et reçus par l'intermédiaire d'un canal de transmission, l'appareil de réception comprenant
une entrée de réception pour recevoir un signal comportant les éléments de données transmis en provenance du canal de transmission ;
un démodulateur (16) pour démoduler les éléments de données à partir des canaux de fréquence simultanément actifs du signal ;
un désentrelaceur (18, 52, 54, 56) pour désentrelacer la position logique de l'élément de données particulier reçu à partir d'une succession logique respective du canal de fréquence à partir duquel l'élément de données particulier a été démodulé afin d'inverser un ordre entrelacé des éléments de données ; le désentrelaceur comprenant un générateur d'adresses (54), une mémoire (56) et un organe de commande de lecture/écriture (52), l'organe de commande de lecture/écriture (52) et le générateur d'adresses (54) étant configurés pour écrire les éléments de données reçus à des emplacements de la mémoire (56) dans un ordre d'écriture, et pour lire les éléments de données dans un ordre de lecture désentrelacé, l'écriture des éléments de données dans la mémoire (56) s'effectuant conformément à une première série d'adresses de la mémoire générées par le générateur d'adresses (54), et la lecture des éléments de données depuis la mémoire (56) s'effectuant conformément à une deuxième série d'adresses de la mémoire (56) générées par le générateur d'adresses (54), la première série d'adresses étant l'une d'une série d'adresses croissant ou décroissant de manière monotone ou d'adresses générées en utilisant une fonction pseudo-aléatoire, et la deuxième série d'adresses étant l'autre d'une série d'adresses croissant ou décroissant de manière monotone ou d'adresses générées en utilisant une fonction pseudo-aléatoire, le signal reçu représentant le nombre de canaux de fréquence ayant été simultanément transmis, chacun des canaux de fréquence étant démodulé afin de fournir un groupe d'éléments de données, et le désentrelaceur étant configuré afin de générer chacune des adresses pour identifier dans les bits d'adresses de poids le plus fort l'un des canaux de fréquence à partir duquel les éléments de données doivent être désentrelacés et dans les bits de poids le plus faible un emplacement de l'élément de données dans le groupe afin de désentrelacer les groupes d'éléments de données pour former un bloc codé d'éléments de données pour un décodage de correction d'erreur.
 
2. Appareil de réception selon la revendication 1, dans lequel le bloc codé d'éléments de données a été codé par un émetteur conformément à un code de correction d'erreur qui est plus robuste vis-à-vis d'erreurs qui sont séparées les unes des autres que vis-à-vis d'erreurs qui se produisent dans une salve, dans la succession logique respective, l'appareil de réception comprenant
un décodeur pour décoder les éléments de données reçus conformément au code de correction d'erreur appliqué à la séquence logique telle qu'elle a été obtenue par le désentrelaceur (18, 52, 54, 56).
 
3. Appareil de réception selon la revendication 1, dans lequel l'organe de commande de lecture/écriture (52) et le générateur d'adresses (54) sont configurés pour écrire, lors de la réception en provenance du démodulateur (16), les éléments de données en provenance de chaque version particulière du cycle de base dans la mémoire (56) dans un ordre d'adresses d'écriture pour la version particulière ; et
pour lire les éléments de données, pour cette version particulière, depuis la mémoire, dans un ordre d'adresses de lecture permuté, pour la version particulière, conformément à une fonction pseudo-aléatoire par rapport à l'ordre d'adresses d'écriture pour la version particulière, l'écriture des éléments de données de la version particulière à des adresses au fur et à mesure que ces adresses deviennent disponibles pendant la lecture des éléments de données d'une version directement précédente du cycle de base.
 
4. Appareil de réception selon la revendication 1, dans lequel le générateur d'adresses (52, 54) est configuré pour générer les ordres d'adresses d'écriture et de lecture, l'ordre d'adresses de lecture, dans la version particulière du cycle de base, étant permuté par rapport à l'ordre d'adresses de lecture utilisé dans une version directement précédente du cycle de base conformément à la fonction pseudo-aléatoire, la fonction pseudo-aléatoire étant particulière à la version du cycle de base ; le générateur d'adresses (54) générant l'ordre d'adresses de lecture et d'écriture périodiquement, chaque ordre d'adresses de lecture se répétant chaque fois après une période d'exactement deux versions du cycle de base, l'ordre d'adresses de lecture étant en alternance un ordre d'adresses croissant ou décroissant de manière monotone et un ordre dans lequel les adresses de lecture sont permutées conformément à la fonction pseudo-aléatoire.
 
5. Procédé de réception pour la réception de données comportant des éléments de données ayant été entrelacés et modulés sur un certain nombre de canaux de fréquence actifs simultanément, le procédé de réception comprenant
la réception des éléments de données provenant d'un canal de transmission, la démodulation des éléments de données à partir des canaux de fréquence simultanément actifs et le désentrelacement des données transmises afin d'inverser un ordre entrelacé des éléments de données ; dans lequel le désentrelacement comprend l'écriture des éléments de données reçus à des emplacements d'une mémoire dans un ordre d'écriture ;
et
la lecture des éléments de données dans un ordre de lecture désentrelacé depuis la mémoire dans un ordre de lecture, l'ordre entrelacé des données transmises fournissant un inverse du désentrelacement, l'écriture comprenant
l'écriture des éléments de données reçus à des emplacements de la mémoire conformément à une première série d'adresses de la mémoire, et la lecture comprenant
la lecture des éléments de données depuis la mémoire conformément à une deuxième série d'adresses de la mémoire, la première série d'adresses étant l'une d'une série d'adresses croissant ou décroissant de manière monotone ou d'adresses générées en utilisant une fonction pseudo-aléatoire, et la deuxième série d'adresses étant l'autre d'une série d'adresses croissant ou décroissant de manière monotone ou d'adresses générées en utilisant une fonction pseudo-aléatoire, la réception des éléments de données comprenant la réception d'un signal représentant le nombre de canaux de fréquence qui ont été simultanément transmis, et la démodulation comprenant la démodulation de chacun des canaux de fréquence afin de fournir un groupe d'éléments de données, et le désentrelacement comprenant
la génération de chaque adresse afin d'identifier, dans les bits d'adresses de poids le plus fort, l'un des canaux de fréquence à partir duquel les éléments de données doivent être désentrelacés et, dans les bits de poids le plus faible, un emplacement de l'élément de données dans le groupe devant être désentrelacé, et
le désentrelacement des groupes d'éléments de données en utilisant les adresses générées afin de former un bloc codé d'éléments de données pour le décodage de correction d'erreur.
 
6. Procédé de réception selon la revendication 5, dans lequel le bloc codé d'éléments de données a été codé par un émetteur conformément à un code de correction d'erreur qui est plus robuste vis-à-vis d'erreurs qui sont séparées les unes des autres que vis-à-vis d'erreurs qui se produisent dans une salve, dans la succession logique respective, le procédé comprenant
le décodage des éléments de données reçus conformément au code de correction d'erreur appliqué à la séquence logique telle qu'elle a été obtenue par le désentrelaceur (18, 52, 54, 56).
 
7. Procédé de réception selon la revendication 5, dans lequel le désentrelacement comprend un désentrelacement dans des versions successives d'un cycle de base, et l'écriture des éléments de données dans la mémoire comprend
l'écriture des éléments de données à partir de chaque version particulière du cycle de base dans une mémoire dans un ordre d'écriture conforme à la première série d'adresses pour la version particulière,
et la lecture des éléments de données depuis la mémoire comprend
la lecture des éléments de données, pour cette version particulière, depuis la mémoire, dans un ordre de lecture conforme à la deuxième série d'adresses pour la version particulière, permuté conformément à une fonction pseudo-aléatoire par rapport à l'ordre d'adresses d'écriture pour la version particulière, l'écriture comportant l'écriture des éléments de données de la version particulière, à des adresses au fur et à mesure que ces adresses deviennent disponibles pendant la lecture des éléments de données d'une version directement précédente du cycle de base.
 
8. Procédé de réception selon la revendication 5, dans lequel le désentrelacement comprend
l'utilisation d'un moyen générateur d'adresses (52, 54) afin de générer les ordres d'adresses d'écriture et de lecture, l'ordre d'adresses de lecture, dans la version particulière du cycle de base, étant permuté par rapport à l'ordre d'adresses de lecture utilisé dans une version directement précédente du cycle de base conformément à la fonction pseudo-aléatoire, la fonction pseudo-aléatoire étant particulière à la version du cycle de base ; le moyen générateur d'adresses générant l'ordre d'adresses de lecture et d'écriture périodiquement, chaque ordre d'adresses de lecture se répétant chaque fois après une période d'exactement deux versions du cycle de base, l'ordre d'adresses de lecture étant en alternance un ordre d'adresses croissant ou décroissant de manière monotone et un ordre dans lequel les adresses de lecture sont permutées conformément à la fonction pseudo-aléatoire.
 




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REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description