(19)
(11)EP 2 301 154 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
14.11.2012 Bulletin 2012/46

(21)Application number: 09786535.6

(22)Date of filing:  07.07.2009
(51)Int. Cl.: 
H03K 23/54  (2006.01)
(86)International application number:
PCT/IB2009/052952
(87)International publication number:
WO 2010/004508 (14.01.2010 Gazette  2010/02)

(54)

SIGNAL PROCESSING ARRANGEMENT

SIGNALVERARBEITUNGSANORDNUNG

AGENCEMENT DE TRAITEMENT DE SIGNAL


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

(30)Priority: 08.07.2008 EP 08159890

(43)Date of publication of application:
30.03.2011 Bulletin 2011/13

(73)Proprietor: NXP B.V.
5656 AG Eindhoven (NL)

(72)Inventor:
  • BREKELMANS, Johannes, Hubertus, Antonius
    NL-5656 AE Eindhoven (NL)

(74)Representative: Schouten, Marcus Maria 
NXP B.V. IP & Licensing Department High Tech Campus 60
5656 AG Eindhoven
5656 AG Eindhoven (NL)


(56)References cited: : 
EP-A- 0 189 744
JP-A- 56 098 030
WO-A-2006/018754
US-A1- 2008 013 671
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    FIELD OF THE INVENTION



    [0001] An aspect of the invention relates to a signal processing arrangement wherein a frequency division is carried out. The signal processing arrangement may be in the form of, for example, an integrated circuit that is capable of carrying out a frequency conversion. Such integrated circuits are typically applied in a front-end module of a receiver. Other aspects of the invention relate to a receiver system and a method of signal processing, which involves a frequency division.

    BACKGROUND OF THE INVENTION



    [0002] There are various types of signal processing that may involve a frequency division by an odd number. Frequency synthesis is an example. A frequency division by 3, 5, or 7, and so on, may be desired for generating a signal at a particular frequency, or for generating a signal having particular characteristics, or both. A controllable frequency divider, which is capable of providing closely spaced even and odd frequency division ratios, such as, for example, 2, 3, 4, 5, 6, and 7, may be used to advantage in a frequency synthesis system. Such a controllable frequency divider can provide an output signal that can be tuned over a relatively wide frequency range on the basis of an input signal that can be tuned over a relatively small frequency range only. Accordingly, it is possible to achieve a relatively wide tuning range, without this requiring an oscillator having a relatively wide tuning range.

    [0003] Frequency division by an odd number can also used to advantage in radiofrequency systems that comprise a so-called harmonic rejection mixer. A harmonic rejection mixer effectively multiplies an input signal with a composite mixer driver signal, which is made up of individual square-wave-like signal components. The individual square-wave-like signal components have a particular magnitude, frequency, and phase relationship with respect to each other. This particular magnitude, frequency and phase relationship allows suppression of one or more of harmonic frequency components in the composite mixer driver signal, which would otherwise cause significant spurious responses. Achieving this particular frequency and phase relationship may involve at least one frequency division by an odd number.

    [0004] In numerous applications, such as frequency synthesis and harmonic rejection mixing as discussed hereinbefore, it is desired that a frequency division by an odd number produces an output signal that has a 50% duty cycle. Such an output signal may also be in the form of a pair of signals, which have a 180° phase relationship. What matters is that the output signal comprises transitions that are equidistantly spaced in time. Such a 50% duty cycle signal allows generating precise in-phase and quadrature signals, in the sense that these signals have a precise 90° in phase relationship with respect to each other. In practice, an output signal will suffer from a duty cycle error: a deviation from the ideal of equidistantly spaced transitions. A duty cycle error, for example, will cause a phase error between the in-phase and quadrature signals, which will adversely affect signal processing quality. In a harmonic rejection mixer, a duty cycle error may adversely affect the suppression of one or more of harmonic frequency components.

    [0005] JP 56 098030 describes a variable-modulo frequency divider. To obtain a fast variable-modulo divider over a wide operating range the idea of the invention is to use twin flip-flops for the feedbacks. The benefit of this configuration is that it avoids the use of decoding gates between the flip-flops this increasing the propagation times of the feedback signals.

    [0006] International patent application published under number WO 2006/ 018754 describes a frequency-division circuit capable of providing a frequency division by an odd number and producing an output signal that has a small duty cycle error. The frequency-division circuit comprises a pair of multi-state circuits, each of which can be switched throughout a cycle of states. One multi-state circuit switches to a next state in response to a rising edge in an input signal. The other multi-state circuit switches to a next state in response to a falling edge in the input signal. Each multi-state circuit has at least one state in which the multi-state circuit inhibits the other multi-state circuit so as to prevent the other multi-state circuit from switching to the next state. Although the frequency-division circuit allows satisfactory signal processing quality, implementations are relatively costly because two multi-state circuits are required.

    SUMMARY OF THE INVENTION



    [0007] There is a need for low-cost circuits that allow a frequency division by an odd number with relatively small duty cycle errors.

    [0008] In order to better address this need, a signal processing circuit in accordance with the invention has the following characteristics. The signal processing arrangement comprises a series of latches arranged as a clocked delay line having a data input and a data output that are coupled to each other so as to form an inverting loop. An enable circuit allows or prevents a latch in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary value, respectively, from the preceding latch in the series of latches.

    [0009] The following holds for all latches within the clocked delay line, except for the latch concerned. In case a transition, which may be a rising edge or a falling edge, occurs at the data input of a latch, this transition will occur at the output of the latch with a delay of approximately one half clock cycle. However, the aforementioned applies only to one of the two aforementioned types of transition for the latch concerned. In case the other type of transition occurs at the data input of the latch concerned, there is an additional delay because the latch concerned is prevented from changing state. The latch concerned must wait one clock cycle counting from the occurrence of the transition concerned in order to be allowed to change state. That is, for one of the two possible transitions, a rising edge or a falling edge, the latch concerned effectively introduces an additional delay of one clock cycle.

    [0010] Consequently, in case the enable circuit is active, the clocked delay line provides different delays depending on whether a rising edge or a falling edge travels, as it were, through the clocked delay line. In case the clocked delay line provides a delay of N/2 clock cycles for a rising edge, the clocked delay line provides a delay of N/2+1 clock cycles for a falling edge, and vice versa, N being an integer representing the number of latches that are active within the clocked delay line. As a result, the clocked delay line will effectively provide a frequency division by an odd number. More specifically, the clocked delay line generates a signal having a frequency that is N+1 times lower than that of a clock signal used to clock the clocked delay line. What is more, a supplementary signal having the same frequency can be derived from the rate at which the latch concerned is allowed or prevented from changing state. This supplementary signal has a relatively precise 180° phase relationship with respect to the aforementioned signal, which is taken from the clocked delay line. Accordingly, a relatively small duty cycle error can be obtained, which contributes to achieving satisfactory signal processing quality as explained hereinbefore.

    [0011] A frequency-division circuit in accordance with the present invention typically requires fewer elements than the frequency-division circuit described in the aforementioned international patent application. Nonetheless, a comparable performance can be achieved. For example, a frequency-division circuit in accordance with the invention can be obtained by adding two latch circuits to a conventional series of latches arranged as a clocked delay line, which is capable of providing a frequency division by an even number.

    [0012] An implementation of the invention advantageously comprises one or more of the following additional features, which are described in separate paragraphs that correspond with individual dependent claims.

    [0013] The enable circuit preferably comprises an additional series of latches arranged as an additional clocked delay line having a data input and a data output. The data input is coupled to a data output of a latch in the first-mentioned series of latches. The data output of the additional clocked delay line is coupled to an enable input of said latch concerned in the first-mentioned series of latches, which is allowed or prevented from changing state if a given binary value or the inverse of that given binary value, respectively, is present at the enable input.

    [0014] The additional clocked delay line preferably comprises two latches between its data input and its data output, whereby the data input is coupled to a data output of said preceding latch in the first-mentioned series of latches.

    [0015] Said preceding latch in the first-mentioned series of latches preferably has a pair of outputs, which are inverting with respect to each other. One output is coupled to a data input of said latch concerned in the first-mentioned series of latches. The other output of the preceding latch is coupled to the data input of the additional clocked delay line.

    [0016] The enable circuit is preferably switchable to an idle state wherein the enable circuit cannot prevent said latch concerned in the first-mentioned series of latches from changing state. This allows odd and even frequency division ratios.

    [0017] Preferably, at least one latch in the additional series of latches has a reset input. The additional series of latches is arranged so that, when a reset signal is applied to the reset input, the given binary value is present at the enable input of said latch concerned in the first-mentioned series of latches, which is thereby allowed to change state.

    [0018] Said latch concerned in the first-mentioned series of latches preferably comprises a reset input. The latch that provides the data output of the additional clock line comprises a reset input. The aforementioned reset inputs are coupled to each other so that the aforementioned latches can be simultaneously reset. This allows a well-defined initial state to be imposed.

    [0019] A pair of clock lines is preferably provided for receiving a differential clock signal having a non-inverted component and an inverted component. One clock line is arranged to apply the non-inverted component to respective clock inputs of a set of respective latches. The other clock line is arranged to apply the inverted component of the differential clock signal to respective clock inputs of another set of respective latches. This obviates the need for inverters for inverting a clock signal.

    [0020] The latches are preferably of the D-type.

    [0021] A flip-flop circuit of the JK-type having a pair of data inputs may be provided. One data input is coupled to a data output of said latch concerned in the first-mentioned series of latches. The other data input of the flip-flop circuit is coupled to the enable input of said latch concerned in the first-mentioned series of latches.

    [0022] An oscillator may be provided for generating a clock signal that drives the series of latches.

    [0023] In addition, a mixer circuit may be provided for multiplying an input signal with at least one mixer driver signal, and a mixer driver circuit for generating the at least one mixer driver signal at least partially on the basis of a signal taken from the series of latches.

    [0024] A detailed description, with reference to drawings, illustrates the invention summarized hereinbefore as well as the additional features.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0025] 

    Fig. 1 is a block diagram that illustrates a receiver system.

    Fig. 2 is a block diagram that illustrates a frequency divider, which forms part of the receiver system.

    Fig. 3 is a time diagram that illustrates state changes of various latches in the frequency divider.

    Fig. 4 is a block diagram that illustrates a flip-flop circuit, which may be included in the frequency divider.

    Fig. 5 is a block diagram that illustrates a controllable delay line portion, which forms part of the frequency divider.

    Fig. 6 is a circuit diagram that illustrates a latch that can be prevented from switching state, which forms part of the frequency divider.


    DETAILED DESCRIPTION OF THE DRAWINGS



    [0026] Fig. 1 illustrates a receiver system that comprises a receiver REC and a rendering device RND. The receiver REC receives a radio frequency signal RF by means of, for example, an antenna or a cable connection. The receiver REC extracts an information signal IS from the radiofrequency signal RF. In response to the information signal IS, the rendering device RND provides perceptible information, audibly or visually, or both.

    [0027] The receiver REC comprises a front-end circuit FEC, a mixer MIX, and a backend circuit BEC, which constitute a processing path that can be tuned to a channel. The receiver REC further comprises an oscillator OSC, a frequency-division circuit DIV, and a controller CTRL, which may be regarded as a tuning system. The controller CTRL may receive user commands from a user interface UIF, which may comprise a remote-control device. The user interface UIF may further comprise, for example, a display, which indicates the channel to which the receiver REC is tuned. The display may form part of the rendering device RND.

    [0028] The receiver REC basically operates as follows. Let it be assumed that the receiver REC is tuned to a particular channel, which will be referred to as desired channel hereinafter. The front-end circuit FEC filters and amplifies the radiofrequency signal RF so as to obtain a processed radiofrequency signal RP, which comprises an amplified version of the desired channel. Other channels are preferably attenuated with respect to the desired channel. Relatively simple filter circuits can attenuate channels that are relatively remote in frequency from the desired channel.

    [0029] The mixer MIX receives a mixer driver signal MD, which causes the mixer MIX to convert the processed radiofrequency signal RP into an intermediate frequency signal IF. More specifically, the mixer driver signal MD causes the mixer MIX to shift the desired channel in frequency so as to obtain a frequency-shifted version thereof, which falls within a predefined intermediate frequency pass band. The backend circuit BEC suppresses signals that are outside the predefined intermediate frequency pass band. Only the frequency-shifted version of the desired channel is retained. The backend circuit BEC applies various types of processing to the frequency-shifted version of the desired channel so as to extract the information signal IS there from. These various types of processing may include, for example, amplification, demodulation, demultiplexing, decoding, and error correction.

    [0030] A user may tune the receiver REC to the desired channel in the following fashion. The user designates the desired channel by means of the user interface UIF. In response, the controller CTRL applies tuning control signals TC1 and TC2 to the oscillator OSC and the frequency-division circuit DIV, respectively. Tuning control signals TC1 causes the oscillator OSC to provide an oscillator signal OS having a particular frequency, which will be referred to as oscillator frequency hereinafter. Tuning control signals TC2 causes the frequency-division circuit DIV to divide this particular frequency by a particular number which will be referred to as frequency division ratio hereinafter.

    [0031] Accordingly, the mixer driver signal MD, which the frequency-division circuit DIV provides, has a frequency that is equal to the oscillator frequency divided by the frequency division ratio. The frequency of the mixer driver signal MD will be referred to as mixing frequency hereinafter. As explained hereinbefore, the mixer MIX carries out a frequency shift. The mixing frequency defines this frequency shift. The controller CTRL sets the oscillator frequency and the frequency division ratio so that the frequency-shifted version of the desired channel falls within the predefined intermediate frequency pass band.

    [0032] In practice, the mixer MIX may frequency shift channels other than the desired channel within the predefined intermediate frequency pass band. Such a frequency shift constitutes a spurious response, which may degrade reception of the desired channel. These spurious responses can be reduced, or attenuated, by careful design of the mixer MIX and, what is more, by ensuring that the mixer driver signal MD has appropriate characteristics.

    [0033] In this respect, the frequency-division circuit DIV plays an important role. For example, the mixer driver signal MD preferably comprises an in-phase component and a quadrature component, which have a 90° phase relationship. The mixer MIX preferably comprises two mixer circuits, one of which receives the in-phase component, the other receiving the quadrature component. Such a mixer MIX structure allows reducing, or attenuating, spurious responses. The better the mixer driver signal MD approximates the 90° phase relationship, the greater the extent to which spurious responses will be reduced, or attenuated.

    [0034] Fig. 2 illustrates the frequency-division circuit DIV. The frequency-division circuit DIV comprises a clocked delay line CDL, an additional clocked delay line ACDL, a mixer driver circuit MDC, and a control circuit CC. In more detail, the clocked delay line CDL comprises a controllable delay portion XDL followed by two latches L1, L2 of the D-type. The controllable delay portion XDL has a data input 1 and a data output O. The additional clocked delay line ACDL comprises two latches of the D- type L3, L4. Each latch has a data input D, a clock input CLK, a non-inverting data output Q+, and an inverting data output Q-. Latch L2 has an enable input E. Latches L2 and L4 each have a reset input R.

    [0035] It should be noted that the clocked delay line CDL has a data input that corresponds with the data input I of the controllable delay portion XDL. The clocked delay line CDL has a data output that corresponds with the inverting data output of latch L2. The data output of the clocked delay line CDL is coupled to its data input so as to form an inverting loop. The additional clocked delay line ACDL has a data input and a data output that correspond with the data input of latch L3 and the non-inverting data output of latch L4, respectively. The additional clocked delay line ACDL is coupled between the inverting data output of latch L1 and the enable input of latch L2, which form part of the clocked delay line CDL.

    [0036] The frequency-division circuit DIV receives the oscillator signal OS and tuning control signal TC2 from the oscillator OSC and the controller CTRL, respectively, illustrated in Fig. 1. The oscillator signal OS is in the form of a differential signal, which has a non-inverted component OS+ and an inverted component OS-. The frequency-division circuit DIV comprises a pair of clock lines, one CL+ for the non-inverted component OS+ of the oscillator signal OS, the other clock line CL- being for the inverted component OS-. The pair of clock lines CL+, CL- applies the oscillator signal OS to the controllable delay portion XDL and the respective clock inputs of aforementioned latches L1-L4. More specifically, latch L 1 receives the inverted component OS- of the oscillator signal OS, whereas latch L2 receives the non-inverted component OS+. Latch L3 receives the non-inverted component OS+ of the oscillator signal OS, whereas latch L4 receives the inverted component OS-.

    [0037] The frequency-division circuit DIV operates as follows. The control circuit CC provides various internal control signals on the basis of tuning control signals TC: a delay control signal DC, and odd/even control signal OE, and a reset signal RS. The delay control signal DC defines a delay between the data input J and the data output O of the controllable delay portion XDL. This delay corresponds with an integer number of cycles of the oscillator signal OS, whereby the aforementioned integer number depends on the delay control signal DC. These cycles of the oscillator signal OS, which may also be designated as periods of the oscillator signal OS, are referred to as clock cycles hereinafter. The delay control signal DC also defines a delay between the data input and the data output of the clocked delay line CDL. This delay is one clock cycle more than the delay of the controllable delay portion XDL. This is because, in combination, latches L1, L2 introduce a delay corresponding to one clock cycle, which adds to the delay of the controllable delay portion XDL.

    [0038] The odd/even control signal OE, which latch L3 receives at its reset input, determines whether the additional clocked delay line ACDL of which latch L3 forms part is enabled (active) or inhibited (idle). More specifically, the odd/even control signal OE enables the additional clocked delay line ACDL by allowing latch L3 to change state. The odd/even control signal OE inhibits the additional delay line ACDL by forcing latch L3 to provide binary value I at its non-inverting data output. Accordingly, latch L4 is also forced to provide binary value 1 at its non-inverting data output, which constitutes the data output of the additional clocked delay line ACDL.

    [0039] The reset signal RS serves to ensure that the frequency-division circuit DIV is in a well-defined state following, for example, a change in tuning control signal TC2. To that end, latches L2 and L4 jointly receive the reset signal RS at their respective reset inputs. That is, the aforementioned reset inputs are coupled to each other as illustrated in Fig. 2 so that latches L2 and L4 can simultaneously be reset by means of the reset signal RS.

    [0040] Let it be assumed that the control circuit CC inhibits the additional clocked delay line ACDL by means of the odd/even control signal OE, which is applied to the reset input of latch L3. In that case, latch L2 receives binary value I at its enable input so that this latch is allowed to change state, irrespective of a value present at the data input of the additional clocked delay line ACDL. As a result, the frequency-division circuit DIV provides an even frequency division ratio. This even frequency division ratio is equal to two times the delay of the clocked delay line CDL in terms of number of clock cycles. In case the controllable delay portion XDL does not introduce any delay, in other words zero delay, the even frequency division ratio is equal to two (2). In case the delay of the controllable delay portion XDL is equal to one clock cycle, the even frequency division ratio is equal to four (4). In case the aforementioned delay is equal to two clock cycles, the even frequency division ratio is equal to six (6), and so on. As explained hereinbefore, the delay control signal DC effectively defines the frequency division ratio.

    [0041] Let it now be assumed that the control circuit CC enables the additional clocked delay line ACDL by means of the odd/even control signal OE. In that case, the inverse of a binary value that is present at the data input of latch L2, will occur at the enable input of the same latch one clock cycle later. This is because the additional clocked delay line ACDL is coupled between the inverting data output of latch L I and the enable input of latch L2, as illustrated in Fig. 2. In effect, the additional clocked delay line ACDL constitutes an enable circuit that allows or prevents latch L2 from changing state depending on whether, one clock cycle ago, latch L2 received binary value 0 or binary value 1, respectively, and its data input. As a result, the frequency-division circuit DIV provides an odd frequency division ratio. This would equally be the case when replacing latch L4 by a latch used for L2 having an additional enable input that is driven by the non-inverting output of latch L2. In that case appropriate measures may need to be taken in order to prevent latch up.

    [0042] Let it be assumed that the additional clocked delay line ACDL is enabled and that a 0 to I transition, which corresponds with a rising edge, occurs at the data input of latch L2 at a given instant. This means that, one clock cycle ago, binary value 0 was present at the data input of latch L2. The additional clocked delay line ACDL causes the inverse of the binary value that was present at the data input of latch L2 to be present at the enable input of this latch. Consequently, binary value 1 will be present at the enable input of latch L2 when the 0 to 1 transition occurs. This means that latch L2 is enabled. The 0 to 1 transition, which occurs at the data input of latch L2, will occur at its data output with a standard delay corresponding to half a clock cycle. There is no additional delay.

    [0043] Let it now be assumed that the additional clocked delay line ACDL is enabled and that a 1 to 0 transition, which corresponds with a rising edge, occurs at the data input of latch L2 at a given instant. This means that, one clock cycle ago, binary value 1 was present at the data input of this latch. The additional clocked delay line ACDL causes the inverse of the binary value that was present at the data input of latch L2 to be present at the enable input of this latch. Consequently, binary value 0 will be present at the enable input of latch L2 when the 1 to 0 transition occurs. This means that latch L2 is inhibited. Latch L2 will not transfer the 1 to 0 transition to its data output with the standard delay of half a clock cycle. The 1 to 0 transition will occur at the data output with an additional delay corresponding to one clock cycle. This is because binary value 1 will be present at the enable input of latch L2 one clock cycle after the occurrence of the I to 0 transition at the data input of latch L2. In effect, the additional clocked delay line ACDL transfers the inverse of the 1 to 0 transition, which is a 0 to 1 transition, from the data input of latch L2 to the enable input of this latch with one clock cycle in delay. In the mean time, the additional clocked delay line ACDL prevents latch L2 from changing state.

    [0044] In summary, in the frequency-division circuit DIV illustrated in Fig. 2, a 0 to I transition experiences a standard delay within the clocked delay line CDL. This standard delay is equal to the delay experienced by any transition, 0 to 1 or 1 to 0, in case the additional delay line is inhibited and the frequency-division circuit DIV provides an even frequency division ratio. In case the additional clocked delay line ACDL is enabled, a 1 to 0 transition experiences an additional delay of one clock cycle, which causes the frequency-division circuit DIV to provide an odd frequency division ratio. That is, one clock cycle additional delay is selectively introduced for 1 to 0 transitions. It should be noted that, in case the additional clocked delay line ACDL was coupled between the non-inverting data output of latch L1 and the enable input of latch L2, one clock cycle additional delay would selectively be introduced for 0 to 1 transitions.

    [0045] Fig. 3 illustrates various signals within the frequency-division circuit DIV in case the following two conditions apply. The delay of the controllable delay portion XDL is equal to one clock cycle. The additional clocked delay line ACDL is enabled so as to obtain an odd frequency division ratio, which is equal to five (5).

    [0046] Fig. 3 is a time diagram having a horizontal axis that represents time. A series of instants t1-t19 are indicated on the horizontal axis, each of which corresponds with a transition in the oscillator signal OS. The instants t1-t19 are equidistantly spaced on a grid of one half a clock cycle. A clock cycle Tpos corresponds with a time interval between two subsequent transitions of an identical type, which may be falling edges, or rising edges.

    [0047] The time diagram of Fig. 3 comprises respective horizontal sections, each illustrating a particular signal. Horizontal sections OS+ and OS- illustrate the non-inverted component OS+ and the inverted component OS- of the oscillator signal OS, respectively. Horizontal section L1D illustrates a signal present at the data input of latch L1. Horizontal section L1Q+ L2D illustrates a signal present at the non-inverting data output of latch L1, which corresponds with a signal present at the data input of latch L2. Horizontal section L2Q+ illustrates a signal at the non-inverting data output of latch L2. Horizontal section L2Q- illustrates a signal present at the inverting data output of latch L2. Horizontal section L1Q- L3D illustrates a signal present at the inverting data output of latch L1, which corresponds with a signal present at the data input of latch L3. Finally, horizontal section L4Q+ L2E illustrates a signal present at the non-inverting data output of latch L4, which corresponds with a signal present at the enable input of latch L2.

    [0048] A 0 to 1 transition, which constitutes a rising edge, occurs at the data input of latch L1 at instant t1. This rising edge occurs one half clock cycle later at the non-inverting data output of latch L1 and the data input of latch L2 at instant t2, and one clock cycle later at the non-inverting data output of latch L2 at instant t3. At the same instant, t3, a falling edge occurs at the inverting data output of latch L2. This falling edge travels, as it were, through the controllable delay portion XDL illustrated in Fig. 2 so as to occur at the data input of latch L 1 with one clock cycle delay at instant t5. The falling edge occurs one half clock cycle later at the non-inverting output of latch L1 and the data input of latch L2 at instant t6.

    [0049] The falling edge, which occurs the data input of latch L2 at instant t6, occurs 1 1/2 clock cycle later at the non-inverting output of latch L2, at instant t9. This is in contrast with the rising edge that occurs at the data input of latch L2 at instant t2, which occurs half a clock cycle later at the data output of the same latch, at instant t3. There is an additional delay of one clock cycle because latch L2 is inhibited at instant t7, which is marked by a cross. More precisely, latch L2 is inhibited during a time interval that extends from instant t4 to instant t8. This is because during this time interval binary value 0 is present at the enable input of latch L2, as illustrated in the lower horizontal section of Fig. 3. As mentioned hereinbefore, the enable input of latch L2 is coupled to the data output of the additional clocked delay line ACDL, which corresponds with the non-inverting data output of latch L4.

    [0050] The additional clocked delay line ACDL inhibits latch L2 during the time interval t4-t8 as a result of the following. The rising edge that occurs at the data input of latch L2 at instant t2 coincides with a falling edge at the inverting data output of latch L1. This falling edge, which occurs at instant t2, is also present at the data input of latch L3, which constitutes the data input of the additional clocked delay line ACDL. The falling edge travels through the additional clocked delay line ACDL and occurs one clock cycle later, which means at instant t4, at its data output, which is formed by the non-inverting data output of latch L4. Since the falling edge constitutes a 1 to 0 transition, the enable input of latch L2 receives binary value 1 before instant t4 and receives binary value 0 after instant t4 until instant t8, when a 0 to 1 transition occurs at the enable input of latch L2 as illustrated in Fig. 3.

    [0051] Fig. 3 shows that the signal illustrated in horizontal section L4Q+ L2E, which is present at the enable input of latch L2, is an inverted and delayed version of the signal illustrated in horizontal section L1Q+ L2D, which is present at the data input of latch L2. The delay is one clock cycle. This is because the additional clocked delay line ACDL transfers the inverse of the signal that is present at the data input of latch L2 to the enable input of this latch with a delay equal to one clock cycle. Consequently, at any given instant, the enable input of latch L2 receives a binary value that is the inverse of the binary value that was present at the data input of this latch one clock cycle ago. In case a 0 to 1 transition occurs at the data input of latch L2, this implies that the data input of this latch L2 received binary value 0 one clock cycle ago. Since the enable input of latch L2 receives the inverse of a binary value that is present at the data input of this latch one clock cycle ago, this further implies that latch L2 receives binary value 1 at its enable input when the 0 to 1 transition occurs. Latch L2 is enabled when the 0 to 1 transition occurs. Conversely, latch L2 receives binary value 0 at its enable input when a 1 to 0 transition occurs at its data input. Latch L2 is inhibited.

    [0052] More specifically, in Fig. 3, a 1 to 0 transition occurs at the data input of latch L2 at instant t6. One clock cycle ago, at instant t4, the data input of latch L2 received binary value 1. Consequently, the enable input of latch L2 receives binary value 0, which is the inverse of binary value 1, when the 1 to 0 transition occurs at instant t6. Latch L2 is thus inhibited when the I to 0 transition occurs. This inhibition will effectively be removed after one clock cycle, at instant t8. This is because the additional clocked delay line ACDL causes an inverse transition, from 0 to 1, to occur at the enable input of latch L2 after one clock cycle at instant t8. That is, at instant t8, the binary value that the data input of latch L2 received one cycle ago, corresponding to instant t6, is equal to 0. Since the inverse of this binary value is present at the enable input of latch L2, latch L2 is enabled.

    [0053] Conversely, a 0 to I transition occurs at the data input of latch L2 at instant t12. One clock cycle ago, at instant t10, the data input of latch L2 received binary value 0. Consequently the enable input of latch L2 receives binary value 1, which is the inverse of binary value 0, when the 0 to 1 transition occurs at instant t12. Latch L2 is thus enabled when the 0 to 1 transition occurs at instant t12. This 0 to 1 transition is a delayed version of the rising edge that occurs at the inverting data output of latch L2 at instant t9. This rising edge travels, as it were, through the controllable delay portion XDL and latch L1. Accordingly, the rising edge experiences a delay equal to 1 1/2 clock cycle so as to produce the 0 to 1 transition at instant t12. Instant t12 can be regarded as the start of a cycle which it is identical to the cycle starting at instant t2 and ending at instant t12.

    [0054] The signal at the non-inverting data output of latch L2, which is illustrated in horizontal section L2Q+ in Fig. 3, and the signal at the non-inverting data output of latch L4, which is illustrated in horizontal section L4Q+, L2E constitute a pair of frequency-divided signals that is applied to the mixer driver circuit MDC. Each of these signals has a frequency that is 1/5 of the frequency of the oscillator signal OS. The frequency division ratio is equal to 5. This is due to the fact that the controllable delay portion XDL provides one clock cycle delay and that the additional clocked delay line ACDL is enabled.

    [0055] Importantly, the aforementioned frequency-divided signals are mutually phase shifted with respect to each other by 180°. This allows the mixer driver circuit MDC to generate mixer driver signal components, which have a precise 90° phase relationship. That is, the frequency-divided signals allow a precise phase quadrature relationship. This contributes to reducing spurious responses of the mixer MIX illustrated in Fig. 1, as mentioned hereinbefore. The mixer driver circuit MDC may be, for example, similar to the quadrature generation circuit illustrated in Fig. 13 of the international patent application published under number WO 2006/018754 mentioned hereinbefore.

    [0056] Fig. 4 illustrates a flip-flop circuit FF of the JK type, which may form part of the mixer driver circuit MDC. The flip-flop circuit FF has a pair of data inputs J and K, respectively, a non-inverting data output Q+, and an inverting data output Q-. The K input is coupled to receive the signal L2Q+ illustrated in horizontal section of Fig. 3, which is the signal from the non-inverting data output of latch L2 that constitutes the data output of the clocked delay line CDL. The J input is coupled to receive the signal illustrated in horizontal section L4Q+ L2E of Fig. 3, which is the signal from the non-inverting data output of latch L4 that constitutes the data output of the additional clocked delay line ACDL. The flip-flop circuit FF effectively combines the aforementioned pair of frequency-divided signals into a single output signal with a duty cycle that is precisely 50% provided that the oscillator signal OS also has a duty cycle that is precisely 50%.

    [0057] Fig. 5 illustrates the controllable delay portion XDL, or rather an implementation thereof. The controllable clocked delay line CDL comprises four latches L11, L12, L13, L14 of D type and two switches SW1, SW2, which may equally be considered as multiplexers. Each latch has a data input D, a clock input CLK, a non-inverting data output Q+, and an inverting data output Q-. Each switch has two inputs and an output. The data input of latch L 11 constitutes the data input I of the controllable delay portion XDL. The output of switch SW2 constitutes the output O of the controllable delay portion XDL. Latches L12 and L14 receive the non-inverted component OS+ of the oscillator signal OS at their respective clock inputs via clock line CL+. Latches L11, L13 receive the inverted component OS- of the oscillator signal OS at their respective clock inputs via clock line CL+. The delay control signal DC, which the control circuit CC illustrated in Fig. 2 provides, comprises two switch control signals SC1, SC2, one switch control signal SC1 for switch SW1, the other switch control signal SC2 for switch SW2.

    [0058] The controllable delay portion XDL operates as follows. In combination, latches L11 and L12 constitute a flip-flop circuit FF of the D type that provides a delay of one clock. The same applies to latches L13 and L14. Switch SW1 can be in a delay-enabling state or in a bypass state depending on switch control signal SC1. Similarly, switch SW2 can be in a delay-enabling state or in a bypass state depending on switch control signal SC2. In the delay-enabling state, switch SW1 couples the data input of latch L13 to the non-inverting data output of latch L12. In the bypass state, switch SW1 couples the data input of latch L13 directly to the data input I of the controllable delay portion XDL. In the delay-enabling state, switch SW2 couples the output O of the controllable delay portion XDL to the non-inverting output of latch L14. In the bypass state, switch SW2 couples the output O of the controllable delay portion XDL directly to the data input I of the same.

    [0059] Accordingly, the delay of the controllable delay portion XDL is equal to 0, one clock cycle, or two clock cycles, depending on the respective states of the two switches SW1, SW2, which are defined by means of the delay control signal DC. In case switch SW2 is in the bypass state, the data input I of the controllable delay portion XDL is directly coupled to the data output O of the same so that the delay is 0, irrespective of the state of switch SW1. Let it be assumed that switch SW2 is in the delay-enabling state. In that case, the delay is equal to one clock cycle or two clock cycles depending on whether switch SW1 is in the bypass state or in the delay-enabling state, respectively.

    [0060] Fig. 6 illustrates latch L2, or rather an implementation thereof. Latch L2 comprises several transistors M1-M 12 and several resistances R1-R5. The transistors may be, for example, of the field-effect type, comprising a gate, a source, and a drain. Transistors M I and M2 form an input differential pair. The respective gates of these transistors constitute the data input D of latch L2 in a differential form, comprising a non-inverting port + and an inverting port -. The respective sources of transistors M1 and M2 are coupled to each other and coupled to signal ground via transistor M3 and transistor M4. The gate of transistor M3 constitutes a non-inverting port + of the enable input E of latch L2, which enable input is in a differential form. The gate of transistor M4 constitutes the clock input CLK of latch L2. Resistances R1 and R2 and transistors M5 and M6 constitute a load circuit for the aforementioned differential pair formed by transistors M 1 and M2. The gate of transistor M6 constitutes the reset input R of latch L2.

    [0061] Transistors M7 and M8 constitute an auxiliary differential pair. The respective sources of these transistors are coupled to signal ground. The gate of transistor M7 is also coupled to signal ground, whereas the gate of transistor M8 constitutes an inverting port - of the enable input E of latch L2. The drain of transistor M7 is coupled to the drain of transistor M1, which is further coupled to resistance R1 and transistor M5 of the load circuit. The drain of transistor M8 is coupled to the drain of transistor M2, which is further coupled to resistance R2 and transistor M6 of the load circuit. The auxiliary differential pair formed by transistors M7 and M8 is thus effectively arranged in parallel with the input differential pair formed by transistors M1 and M2.

    [0062] Transistors M9 and M10 constitute a data retention differential pair. The gate of transistor M9 is coupled to the drain of transistor M10. In a symmetrical fashion, the gate of transistor M10 is coupled to the drain of transistor M9. The drain of transistor M9 is coupled to the drain of transistor M1. The drain of transistor M10 is coupled to the drain of transistor M2. The respective sources of transistors M9 and M 10 are jointly coupled to signal ground via resistance R3.

    [0063] Transistors M11 and M 12 constitute an output differential pair. The gate of transistor M11 is coupled to the respective drains of transistors M1, M7, and M9. The gate of transistor M 12 is coupled to the respective drains of transistors M2, M8, and M10. The respective sources of transistors M11 and M12 and are jointly coupled to signal ground. Resistances R4 and R5, which are coupled to the drains of transistors M11 and M 12, respectively, constitute a load circuit for the output differential pair. The drain of transistor M12 constitutes the non-inverting output Q+ of latch L2. The drain of transistor M11 constitutes the inverting output Q- of latch L.

    [0064] Latch L2 operates as follows. The input differential pair M1, M2 is active only when transistors M3 and M4 are in a conductive state. This occurs when the clock input CLK receives binary value I and the non-inverting port of the enable input E receives binary value 1. In case the differential input pair is active, a binary value that is present at the non-inverting port + of the data input D of latch L2, will be transferred to the non-inverting output Q+. The inverse of this binary value will be present at the inverting output Q-. Latch L2 is in a transparent state, which may also be referred to as open state. The data retention differential pair M9, M 10 copies, as it were, the binary value that is present at the data input D of latch L2.

    [0065] The differential input pair M1, M2 is idle when either transistor M3 or transistor M4 is in a non-conductive state. This occurs when either the clock input CLK receives binary value zero or the non-inverting port + of the enable input E receives binary value 0. In case the differential input pair is idle, the data retention differential pair M9, M 10 determines the respective binary values that are present at the non-inverting output Q+ and the inverting output Q- of latch L2. These respective binary values are in equal to the respective binary value that these outputs had at the most recent instant when the input differential pair was switched from an active state to an idle state. Latch L2 does not respond, as it were, to a binary value that is present at its state input. Latch L2 is in a hold state, which may also be referred to as a closed state. Latch L2 can thus be forced to in the hold state, irrespective of the binary value that is present at the clock input CLK, by applying binary value 0 to the non-inverting port + of the enable input E. In effect, an "and" function is applied to a clock signal and an enable signal, so as to obtain an effective clock signal for latch L2. Transistors M3 and M4 implement this "and" function.

    [0066] The auxiliary differential pair M7 and M8 contributes to a favorable highfrequency performance of latch L2. That is, latch L2 reacts relatively rapidly to a change at its enable input E.

    CONCLUDING REMARKS



    [0067] The detailed description hereinbefore with reference to the drawings is merely an illustration of the invention and the additional features, which are defined in the claims. The invention can be implemented in numerous different ways. In order to illustrate this, some alternatives are briefly indicated.

    [0068] The invention may be applied to advantage in numerous types of products or methods that involve a frequency division. A receiver system is merely an example. The invention may equally the applied in, for example, a transmitter system, a transceiver system, or a measurement system, such as a spectrum analyzer.

    [0069] The detailed description provides an example in which the enable circuit is in the form of a clocked delay line. Alternatively, the enable circuit may comprise a different type of delay circuit, which allows a determination of whether, one clock cycle ago, the latch of interest received a given binary value or the inverse of that given binary value. For example, referring to Fig. 2, latches L3 and L4 may be replaced by a circuit that provides a delay determined by physical properties of particular elements of the circuit, such as, for example, a resistance value and a capacitance value, which define a time constant. The delay need not necessarily be precisely one clock cycle.

    [0070] What is more, the enable circuit may apply a delay of several clock cycles in order to make the aforementioned determination. For example, referring to Figs. 2 and 5, the frequency-division circuit DIV may be modified as follows. Switch SW2 illustrated in Fig. 5 is removed. The data input of latch L3 is no longer coupled to the inverting output of latch L1, as illustrated in Fig. 2, but to the inverting output of latch L12 illustrated in Fig. 5 via two additional latches. That is, the additional clocked delay line ACDL is extended to produce a delay of two clock cycles. Nonetheless, the output of the thus extended additional clocked delay line ACDL indicates whether, one clock cycle ago, the data input of latch L2 received binary value 0 or 1. Notwithstanding the aforementioned, the frequency-division circuit DIV illustrated in Figs. 2 and 5 is preferred because this implementation requires fewer latches than the modified version thereof described hereinbefore.

    [0071] It should further be noted that there are numerous ways of inhibiting the enable circuit so as to obtain an even frequency division ratio. Fig. 2 illustrates an example in which the enable circuit is inhibited by means of an odd/even signal control OE that is applied to the reset input R of latch L3. As another example, the odd/even control signal OE may also be applied to latch L4, which may comprise a supplementary reset input for that purpose.

    [0072] The given binary value one which the aforementioned determination is based, may either be 0 or 1. For example, referring to Fig. 2, the frequency-division circuit DIV will equally provides an odd frequency division ratio in case the data input of the additional clocked delay line ACDL is coupled to the non-inverting data output of latch L1. In that case, rising edges will experience an additional delay of one clock cycle instead of falling edges as illustrated in Fig. 3. It may be necessary to take certain precautions in order to prevent latch up. Referring to Fig. 2 latch L2 may be replaced by a latch that does not have any enable input. In that case, an enable/inhibit function may be achieved by means of an AND gate in front of the clock input of the last mentioned latch, whereby one input port of the AND gate receives the non-inverted oscillator signal component OS+, whereas another input port is coupled to the non-inverting output of latch L4.

    [0073] The term "latch" should be understood in a broad sense. The term includes any type of circuit that can be switched between an open state, in which an output value may vary as a function of an input value, and a closed state, in which the circuit maintains the output value that most recently applied in the open state.

    [0074] In broad terms, there are numerous ways of implementing functional entities by means of hardware or software, or a combination of both. In this respect, the drawings are very diagrammatic. Although a drawing shows different functional entities as different blocks, this by no means excludes implementations in which a single entity carries out several functions, or in which several entities carry out a single function. For example, referring to Fig. 5, switch SW1 and latch L13 may be combined to form an adapted latch L circuit, which has multiplexed inputs.

    [0075] The remarks made herein before demonstrate that the detailed description with reference to the drawings, illustrate rather than limit the invention. There are numerous alternatives, which fall within the scope of the appended claims. Any reference sign in a claim should not be construed as limiting the claim. The word "comprising" docs not exclude the presence of other elements or steps than those listed in a claim. The word "a" or "an" preceding an element or step does not exclude the presence of a plurality of such elements or steps. The mere fact that respective dependent claims define respective additional features, does not exclude a combination of additional features, which corresponds to a combination of dependent claims.


    Claims

    1. A signal processing arrangement comprising:

    - a series of latches (XDL, L1, L2) arranged as a clocked delay line (CDL) having a data input and an data output that are coupled to each other so as to form an inverting loop; and

    - an enable circuit (ACDL) arranged to allow or prevent a latch (L2) in the series of latches from changing state depending on whether, one clock cycle ago, the latch concerned received a given binary value or the inverse of that given binary value, respectively, from the preceding latch (L1) in the series of latches,

    characterized in that in case a transition, which may be a rising edge or a falling edge, occurs at the data input of a latch, this transition will occur at the output of the latch with a delay of approximately one half clock cycle, the latter holding for all latches within the clocked delay line, except for the latch concerned.
     
    2. A signal processing arrangement according to claim 1, the enable circuit (ACDL) comprising an additional series of latches (L3, L4) arranged as an additional clocked delay line having a data input and a data output, the data input being coupled to a data output of a latch (L1) in the first-mentioned series of latches, the data output of the additional clocked delay line being coupled to an enable input (E) of said latch concerned (L2) in the first-mentioned series of latches, which is allowed or prevented from changing state if a given binary value or the inverse of that given binary value, respectively, is present at the enable input.
     
    3. A signal processing arrangement according to claim 2, the additional clocked delay line comprising two latches (L3, L4) between its data input and its data output, whereby the data input is coupled to a data output of said preceding latch (L1) in the first-mentioned series of latches.
     
    4. A signal processing arrangement according to claim 3, said preceding latch (L1) in the first-mentioned series of latches having a pair of outputs (Q+, Q-), which are inverting with respect to each other, one output (Q+) being coupled to a data input (D) of said latch concerned (L2) in the first-mentioned series of latches, the other output (Q-) of the preceding latch (L1) being coupled to the data input of the additional clocked delay line.
     
    5. A signal processing arrangement according to claim 1, the enable circuit (ACDL) being switchable to an idle state wherein the enable circuit cannot prevent said latch concerned (L2) in the first-mentioned series of latches from changing state.
     
    6. A signal processing arrangement according to claim 2, at least one latch (L3) in the additional series of latches having a reset input (R), the additional series of latches being arranged so that, when a reset signal (RS) is applied the reset input, the given binary value is present at the enable input (E) of said latch concerned (L2) in the first-mentioned series of latches, which is thereby allowed to change state.
     
    7. A signal processing arrangement according to claim 2, wherein said latch concerned (L2) in the first-mentioned series of latches comprises a reset input (R), and wherein the latch (L4) that provides the data output of the additional clock line comprises a reset input (R), the aforementioned reset inputs being coupled to each other so that the aforementioned latches can be simultaneously reset.
     
    8. A signal processing arrangement according to claim 2, comprising a pair of clock lines (CL+, CL-) for receiving a differential clock signal (OS) having a non-inverted component (OS+) and an inverted component (OS-), one clock line being arranged to apply the non-inverted component to respective clock inputs (CLK) of a set of respective latches (L2, L3) included in both the clocked delay line and in the enable circuit, the other clock line being arranged to apply the inverted component of the differential clock signal to respective clock inputs of another set of respective latches (L1, L4) included in both the clocked delay line and in the enable circuit.
     
    9. A signal processing arrangement according to claim 1, the latches being of the D-type.
     
    10. A signal processing arrangement according to claim 4, comprising a flip-flop circuit (FF) of the JK-type having a pair of data inputs (J, K), one data input (K) being coupled to a data output of said latch (L2) concerned in the first-mentioned series of latches, the other data input (J) of the flip-flop circuit being coupled to the enable input (E) of said latch (L2) concerned in the first-mentioned series of latches.
     
    11. A signal processing arrangement according to claim 1, comprising an oscillator (OSC) for generating a clock signal (OS) that drives the series of latches (XDL, L1, L2).
     
    12. A signal processing arrangement according to claim 1, comprising:

    - a mixer circuit (MIX) for multiplying an input signal (RP) with at least one mixer driver signal (MD); and

    - a mixer driver circuit (MDC) for generating the at least one mixer driver signal at least partially on the basis of a signal taken from the series of latches (XDL, L1, L2).


     
    13. A receiver system (REC) comprising a signal processing circuit according to claim 12 and a backend circuit (BEC) for processing an output signal (IF) of the mixer circuit (MIX) so as to obtain an information signal (IS) that can be applied to a rendering device (RND).
     


    Ansprüche

    1. Signalverarbeitungsanordnung, welche aufweist:

    eine Reihe von Latches (XDL, L1, L2), welche als eine getaktete Verzögerungsleitung (CDL) eingerichtet sind, welche einen Dateneingang und einen Datenausgang hat, welche aneinander gekoppelt sind, sodass eine invertierende Schleife gebildet ist; und

    einen Aktivier-Schaltkreis (ACDL), welcher eingerichtet ist, einem Latch (L2) in der Reihe von Latches eine Zustandsveränderung zu erlauben oder zu verhindern, abhängig davon ob der betroffene Latch einen Taktzyklus vorher einen gegebenen binären Wert bzw. das Inverse des gegebenen binären Wertes von dem vorhergehenden Latch (L1) in der Reihe von Latches empfing,

    dadurch gekennzeichnet, dass falls ein Übergang, welcher eine steigende Flanke oder eine fallende Flanke sein mag, an dem Dateneingang eines Latches auftritt, dieser Übergang an dem Ausgang des Latches mit einer Verzögerung von näherungsweise einem halben Taktzyklus auftreten wird, wobei letzteres für alle Latches innerhalb der getakteten Verzögerungsleitung außer für den betroffenen Latch gilt.
     
    2. Signalverarbeitungsanordnung gemäß Anspruch 1, wobei der Aktivier-Schaltkreis (ACDL) eine zusätzliche Reihe von Latches (L3, L4) aufweist, welche als zusätzliche getaktete Verzögerungsleitung eingerichtet ist, welche einen Dateneingang und einen Datenausgang hat, wobei der Dateneingang an einen Datenausgang von einem Latch (L1) in der erst-angeführten Reihe von Latches gekoppelt ist, wobei der Datenausgang der zusätzlichen getakteten Verzögerungsleitung an einen Aktivier-Eingang (E) des betroffenen Latches (L2) in der erst-angeführten Reihe von Latches gekoppelt ist, welchem ein Zustandsändern erlaubt oder verhindert ist bzw. wenn ein gegebener binärer Wert das Inverse von dem gegebenen binären Wert an dem Aktivier-Eingang anliegt.
     
    3. Signalverarbeitungsanordnung gemäß Anspruch 2, wobei die zusätzliche getaktete Verzögerungsleitung zwei Latches (L3, L4) zwischen deren Dateneingang und deren Datenausgang aufweist, womit der Dateneingang an einen Datenausgang des vorhergehenden Latches (L1) in der erst-angeführten Reihe von Latches gekoppelt ist.
     
    4. Signalverarbeitungsanordnung gemäß Anspruch 3, wobei der vorhergehende Latch (L1) der erst-angeführten Reihe von Latches ein Paar von Ausgängen (Q+, Q-) hat, welche in Bezug auf einander invertierend sind, wobei ein Ausgang (Q+) an einen Dateneingang (D) des betroffenen Latches (L2) der erst-angeführten Reihe von Latches gekoppelt ist, wobei der andere Ausgang (Q-) des vorhergehenden Latches (L1) an den Dateneingang der zusätzlichen getakteten Verzögerungsleitung gekoppelt ist.
     
    5. Signalverarbeitungsanordnung gemäß Anspruch 1, wobei der Aktivier-Schaltkreis (ACDL) in einen Ruhezustand schaltbar ist, worin der Aktivier-Schaltkreis den betroffenen Latch (L2) in der erst-angeführten Reihe von Latches nicht vom Zustandsändern abhalten kann.
     
    6. Signalverarbeitungsanordnung gemäß Anspruch 2, wobei zumindest ein Latch (L3) in der zusätzlichen Reihe von Latches einen Rücksetzeingang (R) hat, wobei die zusätzlichen Reihen von Latches eingerichtet sind, sodass, wenn an dem Rücksetzeingang ein Rücksetzsignal (RS) angelegt ist, der gegebene binäre Wert an dem Aktivier-Eingang (E) des betroffenen Latches (L2) in der erst-angeführten Reihe von Latches anliegt, welchem dadurch erlaubt ist, den Zustand zu ändern.
     
    7. Signalverarbeitungsanordnung gemäß Anspruch 2, wobei der betroffene Latch (L2) in der erst-angeführten Reihe von Latches einen Rücksetzeingang (R) aufweist, und wobei der Latch (L4), welcher den Datenausgang der zusätzlichen Taktleitung bereitstellt, einen Rücksetzeingang (R) aufweist, wobei die vor-angeführten Rücksetzeingänge aneinander gekoppelt sind, sodass die vor-angeführten Latches simultan zurückgesetzt werden können.
     
    8. Signalverarbeitungsanordnung gemäß Anspruch 2, welche ein Paar von Taktleitungen (CL+, CL-) zum Empfangen eines differentiellen Taktsignals (OS) aufweist, welches eine nicht-invertierte Komponente (OS+) und eine invertierte Komponenten (OS-) hat,
    wobei eine Taktleitung eingerichtet ist, die nicht-invertierte Komponente an jeweilige Takteingänge (CLK) eines Satzes von jeweiligen Latches (L2, L3) anzulegen, welche sowohl in der getakteten Verzögerungsleitung als auch dem Aktivier-Schaltkreis beinhaltet sind,
    wobei die andere Taktleitung eingerichtet ist, die invertierte Komponente des differentiellen Taktsignals an jeweilige Takteingänge eines anderen Satzes von jeweiligen Latches (L1, L4) anzulegen, welche sowohl in der getakteten Verzögerungsleitung als auch dem Aktivier-Schaltkreis beinhaltet sind.
     
    9. Signalverarbeitungsanordnung gemäß Anspruch 1, wobei die Latches von Typ D sind.
     
    10. Signalverarbeitungsanordnung gemäß Anspruch 4, welche
    einen Flipflop Schaltkreis (FF) des Typs JK aufweist, welcher ein Paar von Dateneingängen (J, K) hat, wobei der eine Dateneingang (K) an einen Datenausgang des betroffenen Latches (L2) der erst-angeführten Reihe von Latches gekoppelt ist, und der andere Dateneingang (J) des Flipflop Schaltkreises an den Aktivier-Eingang (E) des betroffenen Latches (L2) in der erst-angeführten Reihe von Latches gekoppelt ist.
     
    11. Signalverarbeitungsanordnung gemäß Anspruch 1, welche einen Oszillator (OSC) aufweist, um ein Taktsignal (OS), welches die Reihe von Latches (XDL, L1, L2) antreibt, zu generieren.
     
    12. Signalverarbeitungsanordnung gemäß Anspruch 1, welche aufweist:

    einen Mischer-Schaltkreis (MIX) zum Multiplizieren eines Eingangssignals (RP) mit zumindest einem Mischer-Antriebs-Signal (MD); und

    einen Mischer-Antriebs-Schaltkreis (MDC), um das zumindest eine Mischer-Antriebs-Signal zumindest teilweise auf Basis eines Signals, welches von der Reihe von Latches (XDL, L1, L2) genommenen ist, zu generieren.


     
    13. Empfängersystem (REC), welches einen Signalverarbeitungsschaltkreis gemäß Anspruch 12 und einen Back-End-Schaltkreis (BEC) zum Verarbeiten eines Ausgangssignals (IF) des Mischer-Schaltkreises (MIX) aufweist, sodass ein Informationssignal (IS), welches an eine Renderingvorrichtung (RND) angelegt werden kann, erlangt wird.
     


    Revendications

    1. Agencement de traitement du signal comprenant :

    - une série de bascules (XDL, L1, L2) disposée comme une ligne à retard synchronisée (CDL) ayant une entrée de données et une sortie de données qui sont raccordées l'une à l'autre pour former une boucle inverseuse ; et

    - un circuit d'activation (ACDL) agencé de manière à autoriser ou à interdire un changement d'état d'une bascule (L2) dans la série de bascules selon que la bascule concernée a reçu, un cycle d'horloge auparavant, une valeur binaire donnée ou l'inverse de cette valeur binaire donnée, respectivement, en provenance de la bascule précédente (L1) dans la série de bascules,

    caractérisé par le fait que dans le cas où une transition se produit à l'entrée de données d'une bascule, celle-ci pouvant être un front montant ou un front descendant, cette transition se produit à la sortie de la bascule avec un retard d'approximativement la moitié d'un cycle d'horloge, la deuxième valant pour toutes les bascules dans la ligne à retard synchronisée, à l'exception de la bascule concernée.
     
    2. Agencement de traitement du signal selon la revendication 1, le circuit d'activation (ACDL) comprenant une série supplémentaire de bascules (L3, L4) disposée comme une ligne à retard synchronisée additionnelle ayant une entrée de données et une sortie de données, l'entrée de données étant raccordée à la sortie de données d'une bascule (1) dans la première série de bascules mentionnée, la sortie de données de la ligne à retard synchronisée additionnelle étant raccordée à une entrée d'activation (E) de ladite bascule concernée (L2) de la première série de bascules mentionnée, dont le changement d'état est autorisé ou interdit si une valeur binaire donnée ou l'inverse de cette valeur binaire donnée, respectivement, se trouve sur l'entrée d'activation.
     
    3. Agencement de traitement du signal selon la revendication 2, la ligne à retard synchronisée additionnelle comprenant deux bascules (L3, L4) entre son entrée de données et sa sortie de données, dans lequel l'entrée de données est raccordée à la sortie de données de ladite bascule précédente (L1) dans la première série de bascules mentionnée.
     
    4. Agencement de traitement du signal selon la revendication 3, ladite bascule précédente (L1) dans la première série de bascules mentionnée ayant une paire de sorties (Q+, Q-) qui sont l'inverse l'une de l'autre, une sortie (Q+) étant raccordée à une entrée de données (D) de ladite bascule concernée (L2) dans la première série de bascules mentionnée, l'autre sortie (Q-) de la bascule précédente (L1) étant raccordée à l'entrée de données de la ligne à retard synchronisée additionnelle.
     
    5. Agencement de traitement du signal selon la revendication 1, le circuit d'activation (ACDL) étant commutable vers un état de repos dans lequel le circuit d'activation ne peut pas empêcher le changement d'état de ladite bascule concernée (L2) dans la première série de bascules mentionnée.
     
    6. Agencement de traitement du signal selon la revendication 2, au moins une bascule (L3) dans la série additionnelle de bascules ayant une entrée de remise à zéro (R), la série additionnelle de bascules agencée de manière à ce que, lorsqu'un signal de remise à zéro (RS) est appliqué à l'entrée de remise à zéro, la valeur binaire donnée est présente sur l'entrée d'activation (E) de ladite bascule concernée (L2) dans la première série de bascules mentionnée, qui est ainsi autorisée à changer d'état.
     
    7. Agencement de traitement du signal selon la revendication 2, dans lequel ladite bascule concernée (L2) de la première série de bascules mentionnée comprend une entrée de remise à zéro (R), et dans lequel la bascule (L4) qui fournit la sortie de données de la ligne d'horloge additionnelle comporte une entrée de remise à zéro (R), lesdites entrées de remise à zéro étant raccordées les unes aux autres de sorte que les bascules mentionnées ci-dessus puissent simultanément être remises à zéro.
     
    8. Agencement de traitement du signal selon la revendication 2, comprenant une paire de lignes d'horloge (CL+, CL-) pour recevoir un signal d'horloge différentiel (OS) ayant une composante non inversée (OS+) et une composante inversée (OS-), une ligne d'horloge étant agencée de manière à appliquer la composante non inversée sur les entrées d'horloge respectives (CLK) d'un ensemble de bascules correspondantes (L2, L3) incluses à la fois dans la ligne à retard synchronisée et dans le circuit d'activation, l'autre ligne d'horloge étant agencée de manière à appliquer la composante inversée du signal d'horloge différentiel sur les entrées d'horloge respectives d'un autre ensemble de bascules correspondantes (L1, L4) incluses à la fois dans la ligne à retard synchronisée et dans le circuit d'activation.
     
    9. Agencement de traitement du signal selon la revendication 1, les bascules étant de type D.
     
    10. Agencement de traitement du signal selon la revendication 4, comprenant un circuit flip-flop (FF) du type JK ayant une paire d'entrées de données (J, K), une entrée de données (K) étant raccordée à une sortie de données de ladite bascule concernée (L2) de la première série de bascules mentionnée, l'autre entrée de données (J) du circuit flip-flop étant raccordée à l'entrée d'activation (E) de ladite bascule concernée (L2) de la première série de bascules mentionnée.
     
    11. Agencement de traitement du signal selon la revendication 1, comprenant un oscillateur (OSC) pour générer un signal d'horloge (OS) qui pilote les séries de bascules (XDL, L1, L2).
     
    12. Agencement de traitement du signal selon la revendication 1, comprenant :

    un circuit mélangeur (MIX) pour multiplier un signal d'entrée (RP) avec au moins un signal de pilotage de mélangeur (MD) ; et

    un circuit de pilotage de mélangeur (MDC) pour générer au moins un signal de pilotage de mélangeur au moins partiellement en fonction d'un signal prélevé à partir des séries de bascules (XDL, L1, L2).


     
    13. Système récepteur (REC) comprenant un circuit de traitement du signal selon la revendication 12 et un circuit de traitement final (BEC) pour traiter un signal de sortie (IF) du circuit mélangeur (MIX) de manière à obtenir un signal d'information (IS) qui peut être appliqué à un dispositif de rendu (RND).
     




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    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description