(19)
(11)EP 2 313 972 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
04.09.2013 Bulletin 2013/36

(21)Application number: 09790943.6

(22)Date of filing:  29.07.2009
(51)International Patent Classification (IPC): 
H03F 3/60(2006.01)
H03F 19/00(2006.01)
(86)International application number:
PCT/US2009/052122
(87)International publication number:
WO 2010/017078 (11.02.2010 Gazette  2010/06)

(54)

METHOD AND APPARATUS FOR JOSEPHSON DISTRIBUTED OUTPUT AMPLIFIER

VERFAHREN UND VORRICHTUNG FÜR JOSEPHSON VERSTÄRKER MIT DEZENTRALEM AUSGANG

PROCÉDÉ ET APPAREIL POUR UN AMPLIFICATEUR DE SORTIE DISTRIBUÉ DE TYPE JOSEPHSON


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

(30)Priority: 05.08.2008 US 186465

(43)Date of publication of application:
27.04.2011 Bulletin 2011/17

(73)Proprietor: Northrop Grumman Systems Corporation
Los Angeles, CA 90067 (US)

(72)Inventors:
  • HERR, Quentin, P.
    Ellicott City MD 21042 (US)
  • MILLER, Donald, L.
    Export PA 15632 (US)
  • PRZYBYSZ, John, X.
    Severna Park MD 21146 (US)

(74)Representative: Schmidt, Steffen J. 
Wuesthoff & Wuesthoff Patent- und Rechtsanwälte Schweigerstrasse 2
81541 München
81541 München (DE)


(56)References cited: : 
US-A- 5 479 131
US-A1- 2001 025 012
  
  • TARUTANI ET AL: "Interface circuit using JTLs as control lines of SQUID array" IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY, IEEE SERVICE CENTER, LOS ALAMITOS, CA, US, vol. 11, no. 1, 1 March 2001 (2001-03-01), pages 341-344, XP011141804 ISSN: 1051-8223
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

BACKGROUND


Field of the Invention



[0001] The disclosure generally relates to wideband distributed amplifiers. More specifically, the disclosure relates to a method and apparatus for providing high-speed, low signal power amplification using superconducting technology.

Description of Related Art



[0002] A well-known wideband amplifier known as a distributed amplifier amplifies the incoming signal to an output signal commensurate with the desired amplification level. Distributed amplifier architecture introduces delay to achieve wideband characteristics. Conventional distributed amplifiers include a pair of transmission lines, each having a characteristic impedance, for independently connecting the inputs and outputs of several active devices.

[0003] Fig. 1 shows the circuit diagram for a conventional distributed amplifier ("DA"). In Fig. 1, input signal 100 is directed to a first transmission line 110 having impedances ZI-I to ZI-5. The amplified output signal 190 is provided by the transmission line 120 which includes impedances ZO-1 to ZO-5. In the embodiment of Fig. 1, active devices are modeled as field effect transistors ("FET") Q1, Q2, Q3 and Q4. As the input signal 100 propagates down the input transmission line 100, each FET responds to the forward-traveling input step by inducing an amplified forward-traveling wave on the output transmission line 120. The number of active devices defines the number of stages for the DA. The amplifier of Fig. 1, shows 4 stages.

[0004] The gain of the distributed amplifier is additive rather than multiplicative. The gain is determined, in part, by the number of stages. This property enables the distributed amplifier to provide a gain at frequencies beyond that of the unity-gain frequency of any individual stage. The delays of the input transmission line 110 and the output transmission line 120 can be made equal through the selection of propagation constants and line lengths to ensure that the output signals from each individual device sums in phase. Both input and output lines must be resistively terminated, by resistors 130 and 140. A major drawback of the conventional distributed amplifier is poor efficiency because power matching and phasing cannot be achieved at the same time.

[0005] A conventional distributed amplifier is also inoperable with high-speed superconducting systems. Superconductor digital circuits feature high clock rates (i.e., 10-40 GHz) and extremely low signal power levels (i.e., 2-8 nW). Superconductor circuits are ideally suited for mixed-signal applications such as analog to digital conversion due to high sample rates and quantum accurate feedback distributed amplifiers, which use the same operating principles as the metrological voltage standard. However, because signal levels are so low and data rates are so high, establishing data links to conventional electronics, at low bit error rate, has been proved difficult.
US Patent Document US 5,479,131 A discloses a Josephson junction voltage standard based on RF-controlled DC SQUIDS. A microwave signal is injected using RF control lines. A D/A converter based on series-connected RF-controlled SQUIDS is also disclosed.

[0006] Therefore, there is a need for a method and apparatus to provide a distributed amplifier adapted to high clock rates and low signal power.

SUMMARY



[0007] The disclosure relates to a superconducting amplifier as recited by claim 1.

BRIEF DESCRIPTION OF THE DRAWINGS



[0008] These and other embodiments of the disclosure will be discussed with reference to the following exemplary and non-limiting illustrations, in which like elements are numbered similarly, and where:

[0009] Fig. 1 shows the circuit diagram for a conventional distributed amplifier,

[0010] Fig. 2 schematically illustrates a distributed amplifier according to one embodiment of the disclosure;

[0011] Fig. 3 schematically illustrates the device-level detail of the distributed amplifier of Fig. 2; and

[0012] Fig. 4 schematically illustrates a distributed amplifier according to another embodiment of the disclosure.

DETAILED DESCRIPTION



[0013] Fig. 2 schematically illustrates a distributed amplifier according to one embodiment of the disclosure. Circuit 200 of Fig. 2 illustrates a 12 stage amplifier represented by stages 1, 2 ... 12. For brevity, only stages, 1, 2 and 12 are shown. Each stage is shown as having a voltage source. Thus, the first stage includes voltage source 201; the second stage is shown with voltage source 202. Amplification stage 12 is shown with voltage source 212. Each stage may optionally include a lumped resonant circuit connected to the voltage source. In Fig. 2, voltage source 202 is connected to inductor 203 and capacitor 204. Inductor 203 and capacitor 204 form a lumped resonant circuit. Similarly, voltage source 12 is connected to inductor 213 and capacitor 214.

[0014] Fig. 2 also shows bias 254 connected in parallel with resistor 253. In an exemplary application, termination resistor 255 was matched to resistor 253 and each was provided with 50 Ω resistance. A lumped circuit comprising inductor 251 and capacitor 252 are connected in series with bias 253. Circuit 200 terminates in the 50 Ohm resistor 255. 254 and 253 are not explicit parts of the amplifier, but are external power supply and load. Resistor 255 may be an explicit part of the amplifier, or it may also be an external load.

[0015] In Fig. 2, a combination of an inductor and a capacitor forms a lumped LC circuit having a characteristic transmission delay. Determining the value of the transmission delay through the lumped circuit is well-known in the art and is not discussed here. In one embodiment of the disclosure, inductors 203, 213 and other inductors in circuit 200, are selected to have an identical inductance. In another embodiment of the disclosure, inductors for each stage can be selected to have a unique inductance value independent of the inductors in other amplification stages. Similarly, capacitors 204, 214 can be selected to provide substantially identical capacitance with the other capacitors of different amplification stages. In another embodiment, a capacitor can be selected to have a unique capacitance value independent of the capacitors of the other amplification stages.

[0016] Transmission lines 230 and 240 are formed in parallel and communicate set/reset signals to each amplification stage. In the embodiment of Fig. 2, transmission line 230 provides set signal 232 to amplification stages 1-12 while transmission line 240 provides reset signal 242 to amplification stages 1-12.

[0017] In one embodiment of the disclosure, transmission lines 230 and 240 are configured to have one or more Josephson transmission lines ("JTLs") for transmitting the set/reset signals. Josephson transmission lines are advantageous for providing high clock rates and low signal power. Each JTL has a characteristic transmission delay. Referring to Fig. 2, JTLs 233 and 235 are serially connected along transmission line 230 and JTLs 243 and 245 are serially connected along transmission lines 240.

[0018] According to one embodiment of the disclosure, an amplification stage comprises two JTLs connected in parallel with a voltage source and a resonant circuit interposed therebetween. Referring to exemplary embodiment of Fig. 2, JTL 233 and JTL 243 are connected to voltage source 202. JTL 233 provides set signal 232 to voltage source 202 while JTL 243 provides reset signal to voltage source 202. The second amplification stage also includes inductor 203 and capacitor 204 connected in series with voltage source 202. While the exemplary embodiment of Fig. 2 shows inductor 203 and capacitor 204 as the resonant circuit, it should be noted that the disclosure is not limited exclusively to an inductor and a capacitor connected to the voltage source. Indeed, any active or passive circuit configuration having a characteristic delay can be used in place of a resonant circuit. For example, the delay could be provided by a passive transmission line circuit.

[0019] The set signal 232 and reset signal 242 provide extremely small, single flux quantum ("SFQ") voltage pulses to each amplification. An exemplary set/reset signal may be about 0.5 mV high and 4 pS wide, FWHM. The SFQ signals are distributed on the active JTLs and turn ON and OFF the voltage sources connected in series. In one embodiment, each JTL was built to provide about 6 pS delay. The resonant circuit was selected to have a resonant delay of about 6 pS, thereby matching the resonant delay of the JTLs. Thus, the resonant circuit delay was matched to a JTL delay of about 6 pS. The resonant circuit also provided 50 Ohm impedance and the circuit provided 20 GHz bandwidth, supporting 10 Gb/S NRZ data. The amplifier bandwidth-gain product was substantially higher than that of the conventional distributed amplifiers, and substantially higher than other amplifiers of SFQ input signals.

[0020] Fig. 3 schematically illustrates the device-level detail of the distributed amplifier of Fig. 2. More specifically, Fig. 3 provides a detailed drawings of a distributed amplifier having an exemplary voltage source. The distributed amplifier of Fig. 3 illustrates a 12 stage amplifier. For brevity, only stages 1, 2 and 12 are shown. In Fig. 3, bias 354 is connected to resistor 353 and a lumped LC circuit comprising inductor 351 and capacitor 352.

[0021] Voltage sources 301, 302 ... 312 include two Josephson junctions arranged in a superconducting-quantum-interference-device ("SQUID"). Each voltage source is set and reset through inductive coupling with transmission lines 330 and 340. SQUID 312 comprises Josephson junctions 315 and 316, as well as inductor 313 and shunt resistor 314. The shunt resistor in each SQUID (applied asymmetrically to the right junction, as shown) enforces the out-of-phase voltage mode required to reset the circuit. During operation, inductor 360 is energized by an SFQ Pulse from Set/Reset gates 332/342. The inductive coupling energizes inductor 313 of SQUID 312. Shunt resistor 314 provides out-of-phase voltage mode which enables resetting SQUID circuit 312. The application of shunt resistor 314 with SQUID 312 is exemplary and non-limiting. Other circuit configurations which enable resetting of the SQUID circuit can be used without departing from the principles disclosed herein.

[0022] Similar to Fig. 2, transmission lines 330 and 340 comprise JTLs 333, 335, 345 and 343 (additional JTLs are omitted for brevity). In addition, each voltage source is serially connected to a resonant circuit including an inductor and a capacitor. Thus, voltage source 312 is connected to inductor 321 and capacitor 322, which cumulatively form resonant circuit (interchangeably, lumped LC circuit) 323.

[0023] In one embodiment of the disclosure, the active Josephson transmission delay on the input is matched to lumped LC transmission line delay on the output. Thus, transmission delay through JTL 335 can be matched to transmission delay of lumped LC circuit 323. In another embodiment, transmission delay through JTL 345 can be matched to transmission delay of lumped LC circuit 323. In still another embodiment, each of JTLs 335, 345 is selected to have a transmission line delay matching that of lumped circuit 323. In still another embodiment, lump circuit 323 has a characteristic delay matching transmission line delay through JTL 333 or 343.

[0024] Each voltage source shown in Fig. 3 was externally loaded by 355 and 353 according to the following Equation:



[0025] In one embodiment of Fig. 3, shunt resistor 314 is selected to be smaller than the value of Equation 1. That is, shunt resistor 314 can be selected to be smaller than 8 [Omega].

[0026] Fig. 4 schematically illustrates a distributed amplifier according to another embodiment of the disclosure. Circuit 400 of Fig. 4 comprises bias 454 connected in parallel with resistor 453. In an exemplary implementation of circuit 400, resistor 453 was selected as 50 [Omega] resistor. As with Figs. 2 and 3, the embodiment of Fig. 4 comprises of 12 voltage sources corresponding to 12 amplification stages. For brevity, only the first, second and twelfth voltage sources are shown.

[0027] In Fig. 4, set/reset signal 432 is provided to transmission line 430. The set and reset signals have opposite polarity so that the reset pulse annihilates the signal generated by the set pulse. The set and reset pulse can each define an SFQ signal. Thus, the set and reset pulses 432 are applied to transmission line 430 input. Propagation of signals of opposite polarity requires AC power source on the JTL instead of DC power as shown in Fig. 4.

[0028] Transmission line 430 comprises a plurality of JTLs, with each JTL matched to an amplification stage such that a circuit with n amplification stages has n-1 JTLs. As discussed, each JTL has a characteristic delay associated therewith.

[0029] In contrasts with circuits of Figs. 2 and 3, each voltage source of circuit 400 communicates with only one transmission line (transmission line 430). Thus, voltage sources 401, 402 and 412 are connected to transmission line 432 and are grounded through lines 470, 471 and 478 respectively. Because the set and reset signals can be SFQ signals of opposite polarity, circuit 400 can be directly connected to "flux-powered signal-flux-quantum circuits," as described in patent US 7,724,020 B2 by Herr for signal amplification and readout.

[0030] As with flux-powered single-flux-quantum logic gates, such an amplifier configuration can avoid static power dissipation in the JTL by elimination of the associated bias resistors.

[0031] Inductor 451 and capacitor 452 complete circuit 400 by forming a resonant circuit which communicates with voltage source 412. In one exemplary embodiment, resistor 455 was matched to resistor 453 and each was provided a 50 Ω resistance.

[0032] While the principles of the disclosure have been illustrated in relation to the exemplary embodiments shown herein, the principles of the disclosure are not limited thereto and include any modification, variation or permutation thereof.


Claims

1. A superconducting amplifier (200, 300, 400) comprising:

a first transmission line (230, 330, 430) having a plurality of Josephson transmission lines denoted as JTLs connected in series (233, 235; 333, 335; 433, 435), each JTL having a respective JTL delay;

a plurality of voltage sources (201, 202, 212; 301, 302, 312; 401, 402, 412) arranged in series with a plurality of resonant circuits (203, 204; 213, 214; 323; 403, 404; 413, 414), each of the plurality of voltage sources electro-magnetically communicating with at least one JTL (233, 235; 333, 335; 433, 435); and each of the resonant circuits (203, 204; 213, 214; 323; 403, 404; 413, 414) having a resonant circuit delay substantially matching the delay of one of the plurality of JTLs (233, 235; 333, 335; 433, 435).


 
2. The superconducting amplifier (400) of claim 1, wherein each voltage source (401, 402, 412) defines a SQUID which is set and reset through an inductive coupling with one of the JTLs (433, 435)
 
3. The superconducting amplifier (400) of claim 2, wherein a single flux quantum denoted as SFQ passing through the first transmission line (430) sets the voltage source, and an SFQ of opposite polarity on the same first transmission line (430) resets the voltage source.
 
4. The superconducting amplifier (400) of claim 2, wherein the SQUID is asymmetrically- shunted to provide an internal out-of-phase voltage mode for resetting the voltage source.
 
5. The superconducting amplifier (400) of claim 2, wherein the SQUID is activated through inductive coupling to the first transmission line (430).
 
6. The superconducting amplifier (400) of claim 2, wherein the SQUID further comprises a shut resistor (314) having a first resistance value.
 
7. The superconducting amplifier (400) of claim 6, wherein the SQUID is externally loaded, with the load resistance value greater than the first resistance value.
 
8. The superconducting amplifier (200, 300) of claim 1, further comprising:

a second transmission line (240, 340) having a plurality of JTLs, each JTL (243, 245; 343, 345) of the second transmission line (240, 340) having a respective JTL delay;

wherein the plurality of voltage sources (201, 202, 212; 301, 302, 312) and the plurality of resonant circuits (203, 204; 213, 214; 323) are interposed between the first transmission line (230, 330) and the second transmission line (240, 340).


 
9. The superconducting amplifier (300) of claim 8, wherein each voltage source (301, 302, 312) further comprises a SQUID (301, 302, 312) configured to be set and reset through inductive coupling with the first transmission line (330).
 
10. The superconducting amplifier (300) of claim 8, wherein each voltage source (201, 202, 212) further comprises a resistively shunted SQUID circuit (301, 302, 312).
 
11. The superconducting amplifier (300) of claim 10, wherein the resistive shunt (314) is asymmetrical.
 
12. The superconducting amplifier (200, 300) of claim 8, wherein the resonant circuit (203, 204; 213, 214; 323) defines an LC circuit having a first signal transmission delay.
 
13. The superconducting amplifier (200) of claim 8, wherein each voltage source (201, 202, 212) is a dc-powered, controllable voltage source.
 
14. The superconducting amplifier (200, 300) of claim 8, wherein the first transmission line (230, 330) is in parallel with the second transmission line (240, 340).
 
15. The superconducting amplifier (200, 300) of claim 8, wherein a first JTL (233, 333) from the first transmission line (230, 330) is connected to a first voltage source (201, 301) of the plurality of voltage sources, a first resonant circuit (203, 204; L,C) of the plurality of resonant circuits, and a first JTL (243, 343) from the second transmission line (240, 340) forming an amplifier stage.
 


Ansprüche

1. Ein supraleitender Verstärker (200, 300, 400), der aufweist:

eine erste Übertragungsleitung (230, 330, 430) mit mehreren in Reihe geschalteten Josephson-Übertragungsleitungen, die als JTLs (233, 235; 333, 335; 433, 435) bezeichnet werden, wobei jede JTL eine zugehörige JTL-Verzögerung aufweist;

mehrere mit mehreren Schwingkreisen (203, 204; 213, 214; 323; 403, 404; 413, 414) in Reihe angeordnete Spannungsquellen (201, 202, 212; 301, 302, 312; 401, 402, 412), wobei jede der mehreren Spannungsquellen elektromagnetisch mit wenigstens einer JTL (233, 235; 333, 335; 433, 435) in Verbindung steht; und jeder der Schwingkreise (203, 204; 213, 214; 323; 403, 404; 413, 414) eine Schwingkreisverzögerung aufweist, die im Wesentlichen der Verzögerung von einer der mehreren JTLs (233, 235; 333, 335; 433, 435) entspricht.


 
2. Supraleitender Verstärker (400) nach Anspruch 1, wobei jede Spannungsquelle (401, 402, 412) ein SQID definiert, das durch eine induktive Kopplung mit einer der JTLs eingestellt und zurückgesetzt wird.
 
3. Supraleitender Verstärker (400) nach Anspruch 2, wobei ein einzelnes durch die erste Übertragungsleitung (430) fließendes Flussquant, das als SFQ bezeichnet wird, die Spannungsquelle einstellt, und ein SFQ einer entgegengesetzten Polarität der gleichen ersten Übertragungsleitung (430) die Spannungsquelle zurücksetzt.
 
4. Supraleitender Verstärker (400) nach Anspruch 2, wobei das SQID asymmetrisch verschoben ist, um einen internen phasenverschobenen Spannungsmodus zum Zurücksetzen der Spannungsquelle bereitzustellen.
 
5. Supraleitender Verstärker (400) nach Anspruch 2, wobei das SQUID durch induktive Kopplung mit der ersten Übertragungsleitung (430) aktiviert wird.
 
6. Supraleitender Verstärker (400) nach Anspruch 2, wobei das SQID weiterhin einen Nebenschlusswiderstand (314) mit einem ersten Widerstandswert aufweist.
 
7. Supraleitender Verstärker (400) nach Anspruch 6, wobei das SQID extern geladen wird, wobei der Ladewiderstandswert größer ist als der erste Widerstandswert.
 
8. Supraleitender Verstärker (200, 300) nach Anspruch 1, der weiterhin aufweist:

eine zweite Übertragungsleitung (240, 340) mit mehreren JTLs, wobei jede JTL (243, 245; 343, 345) der zweiten Übertragungsleitung (240, 340) eine zugehörige JTL-Verzögerung aufweist;

wobei die mehreren Spannungsquellen (201, 202, 212; 301, 302, 312) und die mehreren Schwingkreise (203, 204; 213, 214; 323) zwischen der ersten Übertragungsleitung (32, 330) und der zweiten Übertragungsleitung (240, 340) angeordnet sind.


 
9. Supraleitender Verstärker (300) nach Anspruch 8, wobei jede Spannungsquelle (301, 302, 312) weiterhin ein SQID (301, 302, 312) aufweist, das dazu ausgebildet ist, durch induktive Kopplung mit der ersten Übertragungsleitung (330) eingestellt und zurückgesetzt zu werden.
 
10. Supraleitender Verstärker (300) nach Anspruch 8, wobei jede Spannungsquelle (201, 202, 212) weiterhin eine über einen Widerstand nebengeschlossene SQUID-Schaltung (301, 302, 312) aufweist.
 
11. Supraleitender Verstärker (300) nach Anspruch 10, wobei der Nebenschlusswiderstand (314) asymmetrisch ist.
 
12. Supraleitender Verstärker (200, 300) nach Anspruch 8, wobei der Schwingkreis (203, 204; 213, 214; 323) eine LC-Schaltung mit einer ersten Signalübertragungsverzögerung definiert.
 
13. Supraleitender Verstärker (200) nach Anspruch 8, wobei jede Spannungsquelle (201, 202, 212) eine gleichstrombetriebene, steuerbare Spannungsquelle ist.
 
14. Supraleitender Verstärker (200, 300) nach Anspruch 8, wobei die erste Übertragungsleitung (230, 330) parallel zur zweiten Übertragungsleitung (240, 340) ist.
 
15. Supraleitender Verstärker (200, 300) nach Anspruch 8, wobei eine erste JTL (233, 333) der ersten Übertragungsleitung (230, 330) mit einer ersten Spannungsquelle (201, 301) der Vielzahl von Spannungsquellen, einem ersten Schwingkreis (203, 204; L,C) der mehreren Schwingkreise und einer ersten JTL (243, 343) der zweiten Übertragungsleitung (240, 340) verbunden ist, die eine Verstärkerstufe bilden.
 


Revendications

1. Amplificateur supraconducteur (200, 300, 400) comprenant :

une première ligne de transmission (230, 330, 430) ayant une pluralité de lignes de transmission de type Josephson dénotées comme JTL connectées en série (233, 235 ; 333, 335 ; 433, 435), chaque JTL ayant un retard respectif de JTL ;

une pluralité de sources de tension (201, 202, 212 ; 301, 302, 312 ; 401, 402, 412) agencées en série avec une pluralité de circuits résonants (203, 204 ; 213, 214 ; 323 ; 403, 404 ; 413, 414), chacune de la pluralité de sources de tension communiquant par voie électromagnétique avec au moins une JTL (233, 235; 333, 335 ; 433, 435) ; et chacun des circuits résonants (203, 204 ; 213, 214 ; 323; 403, 404 ; 413, 414) ayant un retard de circuit résonant correspondant sensiblement au retard d'une parmi la pluralité de JTL (233, 235 ; 333, 335 ; 433, 435).


 
2. Amplificateur supraconducteur (400) selon la revendication 1, dans lequel chaque source de tension (401, 402, 412) définit un SQUID qui est fixé et réinitialisé par l'intermédiaire d'un couplage inductif avec une des JTL (433, 435).
 
3. Amplificateur supraconducteur (400) selon la revendication 2, dans lequel un quantum de flux unique dénoté comme SFQ traversant la première ligne de transmission (430) fixe la source de tension, et un SFQ de polarité opposée sur la même première ligne de transmission (430) réinitialise la source de tension.
 
4. Amplificateur supraconducteur (400) selon la revendication 2, dans lequel le SQUID est shunté asymétriquement pour donner un mode de tension interne en opposition de phase pour réinitialiser la source de tension.
 
5. Amplificateur supraconducteur (400) selon la revendication 2, dans lequel le SQUID est activé par l'intermédiaire d'un couplage inductif à la première ligne de transmission (430).
 
6. Amplificateur supraconducteur (400) selon la revendication 2, dans lequel le SQUID comprend en outre une résistance de shunt (314) ayant une première valeur de résistance.
 
7. Amplificateur supraconducteur (400) selon la revendication 6, dans lequel le SQUID est chargé de l'extérieur, avec la valeur de résistance de charge supérieure à la première valeur de résistance.
 
8. Amplificateur supraconducteur (200, 300) selon la revendication 1, comprenant en outre :

une deuxième ligne de transmission (240, 340) ayant une pluralité de JTL, chaque JTL (243, 245 ; 343, 345) de la deuxième ligne de transmission (240, 340) ayant un retard respectif de JTL ;

dans lequel la pluralité de sources de tension (201, 202, 212 ; 301, 302, 312) et la pluralité de circuits résonants (203, 204 ; 213, 214 ; 323) sont interposés entre la première ligne de transmission (230, 330) et la deuxième ligne de transmission (240, 340).


 
9. Amplificateur supraconducteur (300) selon la revendication 8, dans lequel chaque source de tension (301, 302, 312) comprend en outre un SQUID (301, 302, 312) configuré pour être fixé et réinitialisé par l'intermédiaire d'un couplage inductif avec la première ligne de transmission (330).
 
10. Amplificateur supraconducteur (300) selon la revendication 8, dans lequel chaque source de tension (201, 202, 212) comprend en outre un circuit de SQUID (301, 302, 312) shunté par voie résistive.
 
11. Amplificateur supraconducteur (300) selon la revendication 10, dans lequel le shunt résistif (314) est asymétrique.
 
12. Amplificateur supraconducteur (200, 300) selon la revendication 8, dans lequel le circuit résonant (203, 204 ; 213, 214 ; 323) définit un circuit LC ayant un premier retard de transmission de signal.
 
13. Amplificateur supraconducteur (200) selon la revendication 8, dans lequel chaque source de tension (201, 202, 212) est une source de tension commandable alimentée par CC.
 
14. Amplificateur supraconducteur (200, 300) selon la revendication 8, dans lequel la première ligne de transmission (230, 330) est en parallèle avec la deuxième ligne de transmission (240, 340).
 
15. Amplificateur supraconducteur (200, 300) selon la revendication 8, dans lequel une première JTL (233, 333) de la première ligne de transmission (230, 330) est connectée à une première source de tension (201, 301) parmi la pluralité de sources de tension, un premier circuit résonant (203, 204 ; LC) parmi la pluralité de circuits résonants, et une première JTL (243, 343) de la deuxième ligne de transmission (240, 340) formant un étage d'amplificateur.
 




Drawing

















Cited references

REFERENCES CITED IN THE DESCRIPTION



This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

Patent documents cited in the description