(19)
(11)EP 2 330 741 A3

(12)EUROPEAN PATENT APPLICATION

(88)Date of publication A3:
17.09.2014 Bulletin 2014/38

(43)Date of publication A2:
08.06.2011 Bulletin 2011/23

(21)Application number: 10193417.2

(22)Date of filing:  02.12.2010
(51)Int. Cl.: 
H03K 17/16  (2006.01)
H03K 17/06  (2006.01)
G11C 27/02  (2006.01)
H03K 17/14  (2006.01)
(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated Extension States:
BA ME

(30)Priority: 03.12.2009 US 630708
22.12.2009 US 645298

(71)Applicant: NXP B.V.
5656 AG Eindhoven (NL)

(72)Inventors:
  • Wu, Qiong
    Redhill, Surrey RH1 1DL (GB)
  • Mahooti, Kevin
    Redhill, Surrey RH1 1DL (GB)

(74)Representative: Hardingham, Christopher Mark 
NXP B.V. Intellectual Property & Licensing Red Central 60 High Street
Redhill, Surrey RH1 1SH
Redhill, Surrey RH1 1SH (GB)

  


(54)Switch-body PMOS switch with switch-body dummies


(57) An analog sample-and-hold switch has parallel branches extending from an input node to an output node connected to a hold capacitor, each branch having a PMOS signal switch FET in series with a PMOS dummy FET. A sample clock controls on-off switching of the PMOS signal switch FETs, and an inverse of the sample clock controls a complementary on-off switching of the PMOS dummy FETs. A bias sequencer circuit biases the PMOS signal switch FETs and biases the PMOS dummy FETs, in a complementary manner, synchronous with their respective on-off states. The on-off switching of the PMOS dummy FETs injects charge cancelling a charge injection by the PMOS signal switch FETs, and injects glitches cancelling glitches injected by the PMOS signal switch FETs.