(19)
(11)EP 2 386 074 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
06.05.2020 Bulletin 2020/19

(21)Application number: 10700062.2

(22)Date of filing:  08.01.2010
(51)Int. Cl.: 
G03F 7/20  (2006.01)
(86)International application number:
PCT/NL2010/050004
(87)International publication number:
WO 2010/080028 (15.07.2010 Gazette  2010/28)

(54)

METHOD OF SELECTING A SET OF ILLUMINATION CONDITIONS OF A LITHOGRAPHIC APPARATUS FOR OPTIMIZING AN INTEGRATED CIRCUIT PHYSICAL LAYOUT

VERFAHREN ZUR AUSWAHL EINER REIHE VON BELEUCHTUNGSBEDINGUNGEN EINER LITHOGRAFISCHEN VORRICHTUNG ZUR OPTIMIERUNG DER PHYSIKALISCHEN ANORDNUNG EINER INTEGRIERTEN SCHALTUNG

PROCÉDE DE SÉLECTION D'UN ENSEMBLE DE CONDITIONS D'ILLUMINATION D'UN APPAREIL LITHOGRAPHIQUE POUR OPTIMISER LE TRACÉ PHYSIQUE D'UN CIRCUIT INTÉGRÉ


(84)Designated Contracting States:
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO SE SI SK SM TR

(30)Priority: 09.01.2009 EP 09150298

(43)Date of publication of application:
16.11.2011 Bulletin 2011/46

(73)Proprietor: Takumi Technology Corporation
Santa Clara, California 95050 (US)

(72)Inventors:
  • BERKENS, Martinus, Maria
    NL-5613 EA Eindhoven (NL)
  • MITTAL, Anurag
    42478 Longacre Drive South Riding, CA 950 54 (US)

(74)Representative: V.O. 
P.O. Box 87930
2508 DH Den Haag
2508 DH Den Haag (NL)


(56)References cited: : 
US-A1- 2002 122 994
US-A1- 2007 035 716
US-A1- 2004 184 030
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    Field



    [0001] The invention relates to a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate, the layout comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other.

    Background



    [0002] An integrated circuit has circuit functionality that is determined by the geometrical layout of its constituting complex circuit elements, formed as polygons or polygon structures, which are arranged in layered structures of various materials, such as polysilicon (poly), silicon dioxide, doped regions, dielectrics and metal regions. Examples of complex circuit elements are: FET (Field Effect Transistor), BJT(Bipolar Junction Transistor), diodes with various functional goals, resistor, inductor, capacitor, interconnect to connect various passive and active elements with desired goals and configuration etc. Further, any possible circuit configurations formed from combination of such elements from a single device such as a transistor to matched transistor pairs, transistors on critical timing paths, decoupling capacitor/coupling inductor to more complex configurations such as clock trees, sense amplifiers, IO drivers, row/column decoder of a memory, current mirrors, temperature sensor, PLL, DLL & whole memory arrays are considered complex circuit elements. In short, these elements have a recognized and predefined electrical function in an electrical circuit scheme, and thereby constitute the active and passive elements of the electrical circuits that are defined by the polygon structures. Generally, the circuit layout is provided as a mask layout of a mask element in a photolithographic apparatus. The mask layout can comprise geometric adaptations to optically correct for proximity effects which take place during optical transfer in the lithographic apparatus, for instance, by a lens system and/or projection system. These optical transfer systems have specific optical characteristics that can be tuned to provide an optimal setup of lithographic tunic parameters. The parameters may sometimes even be associated to a specific circuit layout requiring specific setup of the lithographic apparatus. In addition, the lithographic system has certain optical system deficiency characteristics (lens aberration etc) that can be accounted for in the optical proximity corrections carried out in the circuit layout.

    [0003] Since the mask layout is often tuned to the specific lithographic system, it will result in printing difficulties when the illumination parameters are not carefully selected. This is especially true when a manufacturer chooses to change the lithographic systems. Accordingly, the objective is to select a set of illumination conditions in a lithographic apparatus, in a process for transferring a pattern to a target substrate, to an extent that acceptable transfer characteristics are achieved which will result limited production loss of malfunctioning circuits. Generally, throughout this text, by optimizing the illumination conditions it is sought to optimize lithographic process parameters relevant for obtaining correctly functioning integrated circuits, including but not limited to tuning parameters such as focus, dose, numerical aperture, sigma in, sigma out.

    [0004] Calculating a cost number for specific illumination settings, which cost number can be optimized to optimize to a yield prediction value, can be seen as an advanced way of identifying illumination settings for a different production setup: if the cost number is too bad one may opt to modify the illumination settings to get better manufacturing yield.

    [0005] One publication that deals with calculating a yield prediction value is US patent No. 6,738,954. In this publication, a quality number calculation is performed on a proposed layout. A number of subdivisions of a circuit are assessed each resulting in an average fault number and a statistical error value of said fault number. Iteratively, a statistical error of the average number is reduced until the statistical error is below an error limit.

    [0006] US patent No. 7,013,441 is another publication that is concerned with calculating a predicted manufacturing yield from an integrated circuit. Here, by selecting library elements from a design database to include in a proposed design for the integrated circuit, a yield is calculated based on a normalization factor that is associated to the library element and used to account for a sensitivity of the library element to a given defect.

    [0007] US7245356 concerns a method of configuring a transfer of an image of a patterning device pattern. A pattern, representative of an aggressive configuration included in the mask layout is selected to optimize the parameters of the lithographic apparatus. A simulation model is provided that simulates a transferred image, to identify a response of the illumination system for a number of individual source points, which results in a determination of an optimal illumination arrangement.

    [0008] US2004/ 0184030 discloses a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. The geometric pattterns have critical dimensions approaching the resolution limit of the optical exposure tool. For an initial set of illumination conditions a local cost number is calculated. The illumination conditions are varied to select an optimal set of illumination conditions having an optimized aggregated cost number.

    [0009] US2002/012294 discloses to select a cost function depending on the design intent in methods for phase shifters of masks used to fabricate integrated circuits.

    [0010] US20070035716 discloses an exposure method for exposing a pattern of a reticle on a plate. A relationship is obtained between an exposure parameter that determines a mode to expose a plate, and an electrical characteristic of a device derived from the device by direct calculation of illumination parameters.

    Summary



    [0011] It is desirable to provide a further optimization in a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate. According to an aspect of the invention, there is provided a method according to claim 1. In particular, according to said aspect, there is provided a method including providing an initial set of illumination conditions; providing a plurality of polygon patterns requiring illumination conditions critical for circuit functionality; calculating for the initial set of illumination conditions a local cost number for each polygon pattern of the plurality of polygon patterns, defining a difference measure of at least one critical dimension between the polygon pattern and a transferred polygon pattern as a function of illumination condition; aggregating for each polygon pattern of the plurality of polygon patterns the local cost numbers; and varying the illumination conditions so as to select an optimal set of illumination conditions having an optimized aggregated cost number. The method further comprises identifying the plurality of polygon patterns as predefined complex circuit elements wherein the local cost numbers are expressed as circuit element cost number functions that are individually associated with said identified complex circuit elements, so as to express circuit element design intent. In another aspect there is provided a system according to claim 13. The system comprises an input, an output and a processor arranged to perform the method of claim 1.

    [0012] In yet another aspect, there is provided a computer program product according to claim 11 and an article of manufacture with a computer usable medium according to claim 12.

    Brief description of the drawings



    [0013] Embodiments of the invention will now be described, by way of example only, with reference to the accompanying schematic drawings in which corresponding reference symbols indicate corresponding parts, and in which:

    Figure 1 illustrates schematically a critical area in a detail of an integrated circuit layout;

    Figures 2-4 shows various examples of scanner optimizations using design intent;

    Figure 5 shows an example flow of an optimization scheme;

    Figure 6 shows the effect of a proximal polygon structure;

    Figure 7 shows a conventional single dimensional variation of a grid pattern;

    Figure 8 - 10 show a multidimensional geometrical variation of a grid pattern;

    Figure 11 shows resulting printing contours of a comparative example; and

    Figure 12 shows a schematic illustration of a system according to an aspect of the invention.


    Detailed description



    [0014] Referring to Figure 1 there is shown schematically a layout detail 1 of polygons 2-4 in an integrated circuit. The detail comprises two adjacent metal tracks 2, 3. These tracks 2, 3 define space S1 which may be critical for providing an electrical connection, or electrical isolation, to provide correct electrical functioning. The polygon layout, for instance of the form as shown in Figure 1, is to be transferred to the substrate using a lithographic apparatus. During transfer, transfer deficiencies may give rise to distortions, which will yield a difference between the printed dimensions, and the target dimensions. This is in particular the case when a layout is to be transferred on a different lithographic apparatus, or when a lithographic apparatus has aged or been altered over time. A selection of illumination conditions for optimal transfer is then desired. To this end, for any segment, a penalty is calculated for the deviation between the (simulated) printed CD (referenced as print_CD) with reference to the target drawn CD (referenced as target_CD). This is done using some cost function, which is then optimized. In this example, the goal would be to minimize the cost. An example implementation for cost on a single segment could be:



    [0015] CD here is defined as either a width of a segment or space between 2 segments, for example, S1 or any one of W1-W3 or S1, S2. If more than one of these parameters are considered critical, they may be added as additional terms in the cost function.

    [0016] For a layout composed of several segments on a given design layer, the goal would be to minimize the total cost, for example as a sum of least squares.

    [0017] Such cost functions can be used to model a wide variety of effects and can be generally seen as a quality number, for instance, for predicting a printing related yield (e.g. putting cost on bad contrast); random defect related yield (e.g. sensitivity to particles, or bad contacts); electrical properties (e.g. put cost on drain area's because it slows down circuit speed and increases dynamic power consumption); or mask making related cost (e.g. put cost on jogs in shape edges because it increases mask-fracture count, and mask writer time).

    [0018] An integral quality number of this layout is therefore provided by this cost function, which may relate to an estimated yield loss as a simple aggregated number. To assist a user or an automatic optimisation tool in optimising the illumination conditions, according to an aspect of the invention, illumination or other lithographic conditions may be perturbed to evaluate a perturbed quality number of said perturbed layout; and layout perturbations are selected that optimize the quality number. Thus, in the present example, this amounts to finding a layout that has minimal total cost. Where in the example in Figure 1 only a single layout detail (critical distance S1) is taken into account for the cost function (that is, a single "hotspot" wherein positioning of adjacent complex circuit elements influence the cost), generally, in a cost function, details of many "hot spots", that is, layout details where a cost problem may be expected, are taken into account to arrive at a total aggregated cost number.

    [0019] Figure 2a-c shows various examples of scanner optimizations. In Figure 2a a simple conventional optimization is sought, using a regular cost function that optimizes the space S between two poly segments according to: cost = (print_S - target_S)^2. However, in Figure 2b, an additional aspect is introduced in the cost function, associated with a design aspect of the circuit. In this particular case, when the contacts 23-24 are shown with reference to polystructures 20-21, the contact overlap S1/S2 is maximized provided printed S is a non-zero minimal value. The goal would be to make sure that the contact lands fully on the poly to make a good contact.

    where S1min= S2min is the minimum via overlap and Smin=minimum space to prevent shorts, and reflect pre-defined thresholds.

    [0020] In Figure 2c, yet another design or functional aspect can be associated to a cost function expressing the two dimensional embedding of the critical distance S: Here the cost function can then reflect that the space S is a function of not only the poly along the critical distance S but also of the poly pattern along a direction transverse to the critical distance. Indeed, the presence of additional poly elements 25 may influence the printability of the space S, which can be accounted for as a contribution of a cost factor from more than a single geometrical dimension.

    [0021] Figure 3a-c show yet another example of optimization of illumination conditions, taking into account functional aspects of the hotspot patterns according to some pre-classified aspects. In particular, Figure 3A merely shows a regular line 30 (which could be a metal line or a poly line without any additional layer information), having a critical width distance CD that can be optimized according to cost = (print_CD - target_CD)^2.However, the critical width distance may be calculated with a different cost function taking into account a pre-classified functional aspect of the circuit. In particular, it may be identified, for instance, via a layer recognition technique, that the poly CD represents a channel length of a transistor 31. For instance, the target design channel length CD of the transistor 31can be optimized based on the design goal and functionality of transistor 31. Consequently, where the layout concerns a low power circuit, the CD can err on being larger; and accordingly, the cost can be defined as:
    if print_CD >= target_CD, cost= (print_CD - target_CD)∗∗2, else = infinite

    [0022] Similarly if the layout concerns a high speed layout, the CD can err on being smaller and cost can be defined as:
    if print_CD <= target_CD, cost= (print_CD - target_CD)∗∗2, else = infinite

    [0023] Furthermore, it may be identified that the transistor 31 is on a critical timing path, which might need to match the print CD to the target CD more critically than a quadratic contribution in order to predict the timing path as accurately as possible.

    [0024] Consequently, its cost function could be defined as: cost = exp | (print_CD - target_CD) |

    [0025] It is shown that in such a critical design configuration, the cost number function can be selected to change in other mathematical forms besides quadratic or other power series such as exponential.

    [0026] Furthermore, with reference to Figure 3c it may be identified through additional input that the CD's CD1 and CD2 are part of a pair of matched transistors 31, 32 such as in sense amplifier, current mirror or other critical analogue circuit configurations of matched transistors. Accordingly, the identification could associate a cost function to the optimization, which would be optimized such that the difference between the CD1 and CD2 is minimal with only a slight penalty attributed to a difference between print layout and target layout of respective critical distances CD1, CD2. So an example of a cost function could be:



    [0027] It is shown that the cost can be expressed as a number of interdependent critical dimensions, wherein interdependency is expressed as an algebraic expression of cost factors including variables each influencing each other to some degree. This can also be expressed as a statistical correlation if desired. Interdependency may be identified by a non zero derivative of the cost function in more than one geometrical dimensions to express pattern design intent and/or two dimensional pattern geometry.

    [0028] As an example of identifying polygon patterns as predefined complex circuit elements the examples of Figures 3A-C show that polygon patterns 30-32 can be matched against a predefined set of complex circuit elements, and a cost number function can be selected for each polygon pattern relative to a matched circuit element to account for a designed element functionality. Typically, this process involves identifying polygon patterns as predefined complex circuit elements and expressing a cost number as a circuit element cost number functions that is individually associated with said identified complex circuit elements, so as to express circuit design intent.

    [0029] This design intent can be extracted using existing layers and/or an additional input layer which can be regarded as a complex circuit element indicator layer indicating complex circuit elements in the polygon patterns. The circuit element cost number functions are calculated based on said complex circuit element indicator layer. (see Figure 12, input 1211) Alternatively, fuzzy pattern matching can be used in the circuit layout analysis expressing design intent. More generally, the complex circuit element cost functions can be formed based on any information that can be extracted from layout or that can be given in addition to layout that concerns an interpretation to their electrical function or purpose. Specifically, such complex circuit element information differs from simple width/space/topology knowledge that can be extracted from a set of polygons without an interpretation on their purpose.

    [0030] As an example, such information might be determining the presence of a polygon pattern in a stacked layer configuration, which can be assessed, typically, by a boolean evaluation:
    and/or/and not between any set of layers.

    [0031] See for instance the structures of Figure 4a. The overlap (Boolean AND) of layers 40 and 41 is used to identify the functional element as transistor gate. In this way the polygon pattern can be identified as a functional element of a complex circuit element. In addition, the size of the polygons in a polygon pattern can be assessed to derive a complex circuit element function.

    [0032] As another example, selections of cost functions can be based on: presence of text label, connectivity, interaction with other shapes (in whatever layer), shape properties such as (but not limited: area, #points, max/min width/height, corner types (inward/outward)))

    [0033] Figures 4a and 4b give yet another example, where a functional aspect of the circuit layout is expressed as a cost penalty in the cost function which is sought to be optimized. This functional aspect is reflected in the choice of a particular cost function. Taking only into account an optimal transfer, without taking into account the functional aspects of the circuit, a cost in a layout of Figure 4a would be the uncorrelated sum of individual costs attributed to the critical distances CD1, CD2, and CD3 of polygons 41-43. However, assuming that CD1, which is a CD of a transistor 41, needs to be optimized on a critical timing path and CD2 and CD3 are optimized just as poly segments 41, 42, then a cost function could be expressed as:



    [0034] This is similar to the Figure 4b example, where in the conventional optimization, all poly CD's will be optimized independently and cost will be expressed as a sum of cost_i= (print_CD_i - target_CD_i)∗∗2, for all i (1-8).

    [0035] However, if an active layer is present, CD1-CD4 may be identified as part of transistors 44, 45, where CD5-CD8 may deviate significantly as they represent dummy features 46, 47. Which may result in a modified cost function of cost_i= (print_CD_i-target_CD_i)∗∗2, for i (1-4) - leaving out the contributions of the dummy polygons 46, 47. It is shown, that element design intent can be expressed in the local cost function by having a constant (zero) contribution of selected polygon patterns.

    [0036] In the previous examples, it is shown that a plurality of polygon patterns 40-47 can be provided requiring illumination conditions critical for circuit functionality; wherein a cost number function is adapted in relation to circuit element functionality that is associated with the polygon areas 40-47. Accordingly, element design intent can be expressed in the local cost function. Alternatively, from a regular mask layout pattern to be transferred, predetermined polygon areas may be selected as hotspot regions identified in the mask layout pattern. This is further explained by the flow in Figure 5. Steps are as follows:
    1. 1. Analyze the mask layout to find areas that are potentially problematic to print and process. The result of this step is a number of layout patterns that can be used to assess printing quality. The main reason for this step is to a have more efficient operation: the total mask layout can be over 100Gb in size which is impossible to handle during optimization. The resulting patterns, hotspot clips, are much smaller data. For example, 1K to 1M (potential) hotspots can be found of for instance 2x2 micron. This would then result in 1Mb to 1Gb of hotspot data.
    2. 2. On the database of layout clips (see Figure 12) the optimization is run. Effectively for varying printing setup, the clips are being analyzed for the printing yield. The outcome is the setup with best result.
    3. 3. Final step is a verification step. With the litho setup as found in step 2, simulation and hotspot detection is ran over the full layout. When no hotspots are found the job finishes, otherwise additional layout clips are added (step 4) to the hotspot database and step 2 is repeated. Finally all hotspots are processed and final optimal illumination conditions can be derived (step 5).


    [0037] In addition, as illustrated in step 3 of Figure 5, cost function analysis is done for all clips in the hotspot clip database. Two modes can be distinguished:
    1. 1. Independent rating of all hotspot clips. All the clips produce a scoring number and these will simply be added. Optimization will try to minimize the total number. This rating is good for independent failure mechanisms.
    2. 2. Concurrent rating of the clips. The independent rating method does not account for the systematic nature of printing related yield loss. For instance if one hotspot has acceptable dose range from -1% to +20% it can have a good score according to mode #1. Same holds for a hotspot with range -20% to +1%. So in method #1 this would be an acceptable combination, but effectively the dose range for the two clips is -1% to +1% which is not good. To account for this, in the concurrent rating we assume that the clip analysis produces a set of ranges for statistically independent process variation parameters (like dose, focus) in which the layout prints OK according to the acceptable limits (e.g. for CD variation) which are checked in yield assessment functions. When optimizing, the overlap of all ranges for all the hotspots is determined, and this overlap (weighted for the different variation parameters) is optimized.


    [0038] Thus, a method is illustrated comprising selecting a plurality of hotspot regions in the integrated circuit layout so as to provide the polygon patterns as a selected number of hotspot regions, the hotspot regions requiring illumination conditions critical for circuit functionality and ranked according to a criticality measure. A rating of the clips can be done according to the examples in Figures 2-4.

    [0039] Figure 6 shows an electron microscope image 60 of a circuit 61, which shows a risk of shorts without adapting the cost function due to the effect of proximal polygon structures. As shown in the corresponding image, the contact 60 on left short circuits to the metal line 61 (CD1 could be sub-minimal) because of the proximity of the landing tab 62 to the contact 60.

    [0040] The cost function for this configuration can be selected to account for the optical proximity effect of a proximal geometrical pattern 61, 62. An aspect not forming part of the invention concerns the selection of a cost function which accounts for the two dimensional geometry of a hotspot pattern, so as to control optical proximity distortions.

    [0041] Figure 7 shows a conventional single dimensional variation of a grid pattern 70. In particular, in the grid pattern 70, the pitch is varied between 130, 150, 170 and 300 nm and a width variation of the critical dimension is varied between 40, 50 and 60 nm. A cumulative cost function is calculated for this set of patterns, which is defined (for each pattern) as (print_CD - target_CD)^2.

    [0042] Figure 8 -Figure 10 shows a number of polygon patterns 80-100 that may be identified in an integrated circuit layout. The polygon patterns may comprise critical dimensions indicated as CD for which correct image transfer is critical for circuit functionality and which may constitute hotspots in a generic circuit layout potentially affecting the circuit functionality. In addition to the single dimensional variation of the grid pattern, a line end space 81 variation in the orthogonal direction was applied in Figure 8 of 90, 90, 100 and 120 nm. In Figure 9, in addition to linear pitch and width variation, a T configuration 91 was applied having a width variation. In Figure 10, another line-end variation 101 was applied.

    [0043] This results in additional patterns, wherein local proximity effects may affect transfer of the critical dimension, and which may contribute to a cost function to be minimized.

    [0044] As an exemplary embodiment, a hotspot may be identified when one of the following conditions is met in conventional C-programming notation:
    • Too small space. At sample points space may not be below 75nm Cost = s>75nm ? 0 : (s-75nm)^2
    • Too small width. At sample points width may not be below 40nm Cost = w>40nm ? 0 : (s-40nm)^2
    • Too small via cover margin (assuming pattern is metal that should overlap contact or via). At sample points margin may not be below -5nm
      Cost = m>-5nm ? 0 : (m+5nm)^2


    [0045] It is shown that in this example, the cost functions may be expressed as discontinuous functions, to express element geometry in the local cost function.

    [0046] Comparative simulated printing results between the conventional selection and the new selection results are shown in Figure 10. Specifically, in a comparative example illumination conditions were sought for a target scanner, where the original scanner operated with a numerical aperture of 1.3, an approximate Sigma-in of 0.55; an approx sigma-out of 0.85 and a threshold of 0.34. Other lithographic apparatus tuning parameters may include resist processing parameters such as bake time and resist development time.

    [0047] Accordingly, a number of illumination parameters of a target scanner were stepwise varied according to Table 1 below, yielding a total of 5*9*9*9 = 3645 conditions in a standard grid search:
    Table 1
     minmaxstep
    NA 1.15 1.35 0.05
    Threshold 0.31 0.39 0.01
    Sigma in 0.45 0.65 0.025
    Sigma out 0.75 0.95 0.025


    [0048] It was assumed that no further aberrations were present in the optical system and illumination system.
    Optimization using 1-D variation without using Design Intent and 2-D variations; equivalent 2-D rank of this optimized condition not in top-10 of Table 3.
    Table 2
    2-D rankNASigma InSigma outThreshold2-D score1-D stdev
    >10 1,3 0,5 0,95 0,33 243,5 32,6
    >10 1,3 0,525 0,925 0,34 130,86 35,2
    >10 1,25 0,525 0,85 0,34 545,945 45,2
    2 1,3 0,55 0,9 0,35 93,59 50,9
    >10 1,3 0,525 0,95 0,34 199,46 51
    1 1,3 0,55 0,875 0,35 83,04 51,6
    >10 1,25 0,525 0,875 0,34 553,84 52,7
    >10 1,3 0,525 0,9 0,34 147,41 58,7
    >10 1,25 0,55 0,85 0,35 240,19 59,5
    5 1,25 0,525 0,9 0,35 108,8 60,5
    Optimization with Design Intent and 2-D variations; equivalent 1-D rank of this optimized condition equals rank 6 in Table 2.
    Table 3
    1-D RankNASigma InSigma outThreshold2-D score1-D stdev
    6 1,3 0,55 0,875 0,35 83,04 51,6
    5 1,3 0,55 0,9 0,35 93,59 50,9
    >10 1,3 0,575 0,85 0,36 94,325 71,7
    >10 1,3 0,575 0,875 0,36 94,79 62,1
    10 1,25 0,525 0,9 0,35 108,8 60,5
    >10 1,3 0,65 0,95 0,33 116,51 237,25
    >10 1,3 0,625 0,95 0,33 118,27 253,35
    >10 1,25 0,525 0,875 0,35 128,16 83,2
    >10 1,35 0,65 0,9 0,33 128,37 294,65
    >10 1,3 0,55 0,85 0,35 128,52 61


    [0049] The resulting printing contours are shown in Figure 11, wherein the optimum contour 1101 for a T-shaped target 1100 is shown, selected according to the 1D method, against the optimum contour 1102, selected according to the 2D method is shown. It shows in Figure 11 that the 1D contour 1101 yields minimal width dimensions W that may affect circuit functionality.

    [0050] Accordingly, comparative results indicate:

    1-D OPE matching and 2-D matching select different scanner parameters

    Best 1-D parameters results in 2-D layouts that print bad, and these layouts have very reduced process window

    Best 2-D parameters avoids printing problems and have better process window

    Best 2-D parameters give more CD-variation for 1-D pattern but increase of max CD error is limited (2.3nm -> 2.6nm)

    With 1-D matching most CD's match better, but apparently worst-case is not much different



    [0051] Figure 12 shows a setup of a system 1200 for selecting a set of illumination conditions of a lithographic apparatus for an integrated circuit layout to be transferred to a target substrate illustrating a schematic illustrative data flow. The system comprises an input 1201, a processing part 1202, a database 1203 and an output 1204.

    [0052] Specifically, the input 1201 may non-limitatively concern the following functional entries.

    [0053] Mask layout input 1210: a full layout of a mask for which optimized scanner settings have to be found.

    [0054] Design layout data input 1211 for the layer for which the optimization is ran. This input is optional and can be regarded as a complex circuit element indicator layer, indicating the presence of predefined types of complex circuit elements. This data layer may be used when cost functions are defined as explained in the figures 2-4, where additional design information can be included when selecting a cost function. In addition, design layout data of layers annex to layer for which the optimization is run may be included.

    [0055] Simulated contour input 1212 according to original (not optimized) setup. This input may be used when yield functions are present that match target printing against original printing.

    [0056] SEM image input 1313. For some locations SEM images can be present and for these locations the CD matching may be done.

    [0057] Furthermore, the processing part 1202 may comprise the following functional processing circuits:

    detection circuitry 1220 to detect a plurality of hotspot regions in the integrated circuit layout inputted from data input 1210. The detection is optional, alternatively, a single or plural predefined hotspot areas may be entered;

    a selection circuit 1221 to select a cost number function adapted to the polygon pattern. The selection may be done by input processing of the design layout data received from input 1211. Alternatively, the system 1200 may be arranged to receive adapted cost functions from external input.

    a calculation circuit 1222 to calculate the aggregated cost numbers for the polygon patterns; and

    an optimizing circuit 1223 set of illumination conditions having an optimized aggregated cost number. The optimizing circuit functions as explained in detail in Figure 5.



    [0058] The hotspot regions may be stored in a hotspot clipping database 1203 for further use in the processing, and for easy access in the optimization process and for outputting. To this end, the system comprises an output 1204, for example, in the form of an output data file 1240 in combination with a GUI 1241. The output 1204 is arranged to list a limited number of hotspots that contribute most to the resulting cost score; a breakdown of the total score into yield loss categories (as defined by the yield assessment functions) and the hotspots that contribute most there; and General optimization info like runtimes, job distribution, optimization progress, scoring values for start/intermediate/final results etc.

    [0059] In the invention it is not relevant how the actual global optimisation is done, the concern is on how to prepare cost functions for proper trade off, and proper computation. Actual optimisation can for instance be done by linear programming (if the cost functions are convex and piece wise linear), integer linear programming (if cost functions are piece wise linear but not convex), genetic algorithms or simulated annealing (if cost functions are ill shaped) etc.

    [0060] Furthermore, the optimization can be carried out for various circuit layout structures, including polysilicon structures, metal structures or active regions areas including doped materials. For example, for metal structures, when these are identified to belong to symmetrical segments of a clock tree, they will be optimized identically with high priority assigned to minimizing the delta between their CDs. Note that such could be located quite a distance apart from each other and yet be part of the same clock-tree.

    [0061] Furthermore, when it's known that the segment is part of a critical timing arc, and the delay through the segment needs to be known precisely, the delta in the CD relating to the width of the metal line (as well as space from any neighbouring lines), from the target layout could be related to timing net slack information in ps.

    [0062] For example, if the acceptable timing slack can be 5ps, then the delta in CD can be x nm, while if it is lOps, the delta in CD could be y nm. Similarly for meeting a smaller timing slack, the space to any neighbouring line could be optimized. If the location of the via is also known for the same segment which is part of critical timing arc, then the via overlap S is optimized to result in a tighter spec for via resistance. If there are multiple vias present, then the overlap S could be optimized with a less stringent resistance spec for a single via.

    [0063] As a further example the cost function can be adapted according to circuit functionality, for instance, when it's known that a signal line is flanked by aggressor lines, which cause AC coupling. If the circuit is designed such that the AC coupling from such aggressor lines are supposed to be equal, then it's advantageous that the widths of their lines and their spaces to the signal line are optimized to the same exact tolerance. If on the other hand, the flanking lines of a signal line are not aggressor lines but static shield lines such optimization can be left out.

    [0064] In some aspects, the method can be characterized as a method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout pattern to a target substrate, the layout comprised of a number of polygons having a predetermined geometrical relation relative to each other, the method comprising: providing an initial set of illumination conditions and providing the integrated circuit layout; identifying at least one hotspot region in the integrated circuit layout; the hotspot region requiring illumination conditions critical for circuit functionality; assessing, for the initial set of illumination conditions, in the hotspot region, a local cost number, expressing a difference measure between the hotspot region and a transferred hotspot region as a function of hotspot geometry and illumination condition; perturbing said cost number by varying said set of illumination conditions; and selecting perturbations of said illumination conditions that optimize the cost number, so as to select an optimal set of illumination conditions, wherein the cost number is expressed as cost functions that are classified according to predetermined classes associated with a predetermined hotspot circuit functionality. The hotspot circuit functionality may be determined by matching the hotspot geometry against a set of predetermined functional circuit structures.

    [0065] In the figures, a focus is given on cost function analysis wherein best match physical characteristics are evaluated that include geometrical characteristics of said circuit layout, in particular, by storing corner and edge coordinates of polygons. However, cost function may also include non-geometrical parameters, such as material composition ratio's or the like. Furthermore, the cost function analysis not only focuses on two-dimensional variations of layout components, but may also concern height variations. In particular, this is of interest in providing accurate prediction of metal height variations as induced by chemical mechanical polishing or providing or providing dummy 3D structures to mitigate variation due to chemical mechanical polishing of the metal/dielectric system. In general, the cost functions, or quality numbers, may concern any aspect that is considered of relevance to a layout optimization, including but not limited thereto printing related predicted yield; a random defect related predicted yield; a predicted electrical circuit performance value, in particular, circuit speed and/or power consumption; a mask making related cost; a random defect sensitivity, a quality of vias connecting multiple conducting layers in the design, a quality of electrical elements in the circuit layout, and/or a electro-migration sensitivity. Furthermore, not only the optimum analysis of these aspects may be of interest, but also robustness analysis of the selected optima. The latter aspect may include higher order differential analysis of the cost functions.

    [0066] The skilled artisan will appreciate that, in the context of this description, the use of the term "critical area" refers to an area to be inspected for defects, in particular, an area which provides correct electrical functioning in terms of providing an electrical connection or an electrical isolation and is formed by adjacent edges and a common run length. Hence, critical areas are defined by polygons areas that make up a layout detail of an integrated circuit or spaces between such polygons. Polygons, throughout the application, refer to entities in the forms of polygons, used to define physical entities on a substrate, that in combination provide and define the functioning of a (micro) electric circuit.

    [0067] The terms "perturbing", "pertubation" etc. are used in its standard mathematical meaning but also may concern small variations, in particular, step variations in illumination settings.

    [0068] While specific embodiments of the invention have been described above, it will be appreciated that the invention may be practiced otherwise than as described. In particular, the descriptions above are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made to the invention as described without departing from the scope of the claims set out below.


    Claims

    1. Method of selecting a set of illumination conditions of a lithographic apparatus, in a process for transferring an integrated circuit layout to a target substrate, the layout comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other, the method comprising:

    - providing an initial set of illumination conditions;

    - providing a plurality of polygon patterns (1, 20, 30, 40) from the number of polygon patterns (2,3; 20,21; 30,31; 40,41) requiring illumination conditions critical for circuit functionality;

    - calculating for the initial set of illumination conditions a local cost number for each polygon pattern of the plurality of polygon patterns (2,3; 20,21; 30,31; 40,41), defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition;

    - aggregating for each polygon pattern of the plurality of polygon patterns (2,3; 20,21; 30,31; 40,41) the local cost numbers; and

    - varying the illumination conditions so as to select an optimal set of illumination conditions having an optimized aggregated cost number, wherein the method further comprises:

    - identifying the plurality of polygon patterns (2,3; 20,21; 30,31; 40,41) as predefined complex circuit elements (1, 20, 30, 40) and wherein the local cost numbers are expressed as circuit element cost number functions that are individually associated with said identified complex circuit elements (1, 20, 30, 40), so as to express circuit design intent.


     
    2. Method according to claim 1, further comprising selecting a plurality of hotspot regions (1) in the integrated circuit layout so as to provide the plurality of polygon patterns from the number of polygon patterns (2,3; 20,21; 30,31; 40,41) as a selected number of hotspot regions (1), the hotspot regions requiring illumination conditions critical for circuit functionality and ranked according to a criticality measure.
     
    3. Method according to claim 1, further comprising matching the polygon patterns against a predefined set of circuit elements, and selecting for each polygon pattern of the plurality of polygon patterns a local cost number function relative to a matched circuit element (1, 20, 30, 31, 32, 40, 44, 45).
     
    4. Method according to claim 3, wherein the matching includes determining the presence of the polygon pattern in a predefined stacked layer configuration (40, 44, 45).
     
    5. Method according to claim 1, wherein the plurality of polygon patterns are provided associated with a complex circuit element indicator layer indicating complex circuit elements in the polygon patterns; and wherein the circuit element cost number functions are calculated based on said complex circuit element indicator layer.
     
    6. Method according to claim 1, wherein the local cost number function increases more than quadratically when a polygon pattern is transferred outside a predetermined target region.
     
    7. Method according to claim 1, wherein the local cost number function is constant when a polygon pattern is transferred within a predetermined geometrical region.
     
    8. Method according to claim 1, wherein the local cost number functions are exponential functions and/or discontinuous functions.
     
    9. Method according to claim 1, wherein said local cost number represents a printing related predicted yield; a predicted electrical circuit performance value; a quality of vias connecting multiple conducting layers in the design, a quality of electrical elements in the circuit layout, and/or a electro-migration sensitivity.
     
    10. A method according to claim 1, wherein said plurality of polygon patterns is provided by storing corner and edge coordinates of the polygons patterns.
     
    11. A computer program product, comprising program code portions for performing steps of a method as claimed in any one of claims 1-8, when run on a programmable apparatus.
     
    12. An article of manufacture with a computer usable medium having computer readable instructions therein for providing access to resources available on that computer, the computer readable instructions comprising to cause the computer to perform the steps of a method as claimed in any one of claims 1-8.
     
    13. A system (1200) for selecting a set of illumination conditions of a lithographic apparatus for an integrated circuit layout to be transferred to a target substrate, the layout comprised of a number of polygon patterns having a predetermined geometrical relation relative to each other, the system comprising:

    - an input (1201) for receiving an initial set of illumination conditions and for receiving a plurality of polygon patterns from the number of polygon patterns requiring illumination conditions critical for circuit functionality

    - a processing circuit (1202) arranged to

    ∘ identify a plurality of polygon patterns as predefined complex circuit elements ;

    ∘ calculate for the initial set of illumination conditions a local cost number for each polygon pattern of the plurality of polygon patterns, defining a difference measure of at least one critical dimension, between the polygon pattern and a transferred polygon pattern as a function of illumination condition; wherein the local cost number is expressed as a circuit element cost number function that is individually associated with said identified complex circuit element, so as to express circuit element design intent;

    ∘ aggregate for each polygon pattern the local cost numbers; and

    ∘ vary the illumination conditions so as to select an optimal set of illumination conditions having an optimized aggregated cost number; and

    - an output (1204) for outputting said optimal set of illumination conditions.


     
    14. The system according to claim 11, wherein the processing circuit is arranged to identify hotspot circuit functionality by matching a hotspot geometry against a set of predetermined functional circuit structures (1203); and wherein said local cost number functions are classified according to predetermined classes associated with the identified hotspot circuit functionality.
     
    15. The system according to claim 11, the input comprising a design layout data input (1211); and wherein the processing circuit (1202) is arranged to receive the design layout data to select a local cost number function in response to the design layout data of a polygon pattern.
     


    Ansprüche

    1. Verfahren zum Auswählen eines Satzes von Beleuchtungsbedingungen einer lithografischen Vorrichtung in einem Verfahren zum Übertragen eines integrierten Schaltungslayouts auf ein Zielsubstrat, wobei das Layout aus einer Anzahl von Polygonmustern mit einer vorbestimmten geometrischen Beziehung relativ zueinander besteht, wobei das Verfahren Folgendes umfasst:

    - Bereitstellen eines anfänglichen Satzes von Beleuchtungsbedingungen;

    - Bereitstellen mehrerer Polygonmuster (1, 20, 30, 40) aus der Anzahl von Polygonmustern (2,3; 20,21; 30,31; 40,41), die Beleuchtungsbedingungen erfordern, die für die Schaltungsfunktionalität kritisch sind;

    - Berechnen einer lokalen Kostenzahl für jedes Polygonmuster von mehreren Polygonmustern (2,3; 20,21; 30,31; 40,41) für den anfänglichen Satz von Beleuchtungsbedingungen, wobei ein Differenzmaß von wenigstens einer kritischen Dimension zwischen dem Polygonmuster und einem übertragenen Polygonmuster als Funktion der Beleuchtungsbedingung definiert wird;

    - Aggregieren der lokalen Kostenzahlen für jedes Polygonmuster der mehreren Polygonmustern (2,3; 20,21; 30,31; 40,41); und

    - Variieren der Beleuchtungsbedingungen, um einen optimalen Satz von Beleuchtungsbedingungen mit einer optimierten aggregierten Kostenzahl auszuwählen, wobei das Verfahren ferner Folgendes umfasst:

    - Identifizieren der mehreren Polygonmuster (2,3; 20,21; 30,31; 40,41) als vordefinierte komplexe Schaltungselemente (1, 20, 30, 40) und wobei die lokalen Kostenzahlen als Funktionen von Kostenzahlen der Schaltungselemente ausgedrückt werden, die den identifizierten komplexen Schaltungselementen (1, 20, 30, 40) einzeln zugeordnet sind, um die Absicht der Schaltungskonstruktion auszudrücken.


     
    2. Verfahren nach Anspruch 1, ferner umfassend das Auswählen mehrerer Hotspot-Bereiche (1) in dem Layout einer integrierten Schaltung, um die mehreren Polygonmuster aus der Anzahl von Polygonmustern (2,3; 20,21; 30,31; 40,41) als ausgewählte Anzahl von Hotspot-Bereichen (1) bereitzustellen, wobei die Hotspot-Bereiche die Beleuchtungsbedingungen erfordern, die für die Schaltungsfunktionalität kritisch sind, und nach einem Kritikalitätsmaß eingestuft werden.
     
    3. Verfahren nach Anspruch 1, ferner umfassend das Anpassen der Polygonmuster an einen vordefinierten Satz von Schaltungselementen, und das Auswählen einer lokalen Funktion von Kostenzahlen relativ zu einem angepassten Schaltungselement (1, 20, 30, 31, 32, 40, 44, 45) für jedes Polygonmuster der mehreren Polygonmustern.
     
    4. Verfahren nach Anspruch 3, wobei das Anpassen das Bestimmen des Vorhandenseins des Polygonmusters in einer vordefinierten gestapelten Schichtkonfiguration (40, 44, 45) umfasst.
     
    5. Verfahren nach Anspruch 1, wobei die mehreren Polygonmuster bereitgestellt werden, die einer komplexen Indikatorschicht der Schaltungselemente zugeordnet sind, die komplexe Schaltungselemente in den Polygonmustern angibt; und wobei die Funktionen von Kostenzahlen der Schaltungselemente basierend auf der komplexen Indikatorschicht der Schaltungselemente berechnet werden.
     
    6. Verfahren nach Anspruch 1, wobei die lokale Funktion von Kostenzahlen mehr als quadratisch ansteigt, wenn ein Polygonmuster außerhalb eines vorbestimmten Zielbereichs übertragen wird.
     
    7. Verfahren nach Anspruch 1, wobei die lokale Funktion von Kostenzahlen konstant ist, wenn ein Polygonmuster innerhalb eines vorbestimmten geometrischen Bereichs übertragen wird.
     
    8. Verfahren nach Anspruch 1, wobei die lokale Funktion von Kostenzahlen exponentielle Funktionen und/oder diskontinuierliche Funktionen sind.
     
    9. Verfahren nach Anspruch 1, wobei die lokale Kostenzahl eine druckbezogene vorhergesagte Ausbeute; einen vorhergesagten Leistungswert der elektrischen Schaltung; eine Qualität von Durchkontaktierungen, die mehrere leitende Schichten in der Konstruktion verbinden, eine Qualität von elektrischen Elementen in dem Schaltungslayout und/oder eine Elektromigrationsempfindlichkeit darstellt.
     
    10. Verfahren nach Anspruch 1, wobei die mehreren Polygonmuster durch Speichern von Eck- und Kantenkoordinaten der Polygonmuster bereitgestellt werden.
     
    11. Computerprogrammprodukt, umfassend Programmcodeabschnitte zum Durchführen von Schritten eines Verfahrens nach einem der Ansprüche 1 bis 8, wenn es auf einer programmierbaren Vorrichtung ausgeführt wird.
     
    12. Herstellungsgegenstand mit einem computerverwendbaren Medium mit computerlesbaren Anweisungen zum Bereitstellen des Zugriffs auf auf diesem Computer verfügbare Ressourcen, wobei die computerlesbaren Anweisungen ein Bewirken umfassen, dass der Computer die Schritte eines Verfahrens durchführt, wie in einem der Ansprüche 1 bis 8 beansprucht.
     
    13. Ein System (1200) zum Auswählen eines Satzes von Beleuchtungsbedingungen einer lithografischen Vorrichtung für ein Layout einer integrierten Schaltung, das auf ein Zielsubstrat übertragen werden soll, wobei das Layout aus einer Anzahl von Polygonmustern besteht, die eine vorbestimmte geometrische Beziehung relativ zueinander aufweisen, wobei das System aus Folgendem besteht:

    - eine Eingabe (1201) zum Empfangen eines anfänglichen Satzes von Beleuchtungsbedingungen und zum Empfangen mehrerer Polygonmuster aus der Anzahl von Polygonmustern, die Beleuchtungsbedingungen erfordern, die für die Schaltungsfunktionalität kritisch sind;

    - eine Verarbeitungsschaltung (1202), die angeordnet ist, um

    o mehrere Polygonmuster als vordefinierte komplexe Schaltungselemente zu identifizieren;

    o für den anfänglichen Satz von Beleuchtungsbedingungen eine lokale Kostenzahl für jedes Polygonmuster aus mehreren Polygonmustern zu berechnen, wobei ein Differenzmaß von wenigstens einer kritischen Dimension zwischen dem Polygonmuster und einem übertragenen Polygonmuster als Funktion der Beleuchtungsbedingung definiert wird; wobei die lokale Kostenzahl als eine Funktion von Kostenzahlen der Schaltungselemente ausgedrückt wird, die dem identifizierten komplexen Schaltungselement einzeln zugeordnet ist, um die Absicht der Konstruktion der Schaltungselemente auszudrücken;

    ∘ für jedes Polygonmuster die lokalen Kostenzahlen zu aggregieren; und

    - die Beleuchtungsbedingungen zu variieren, um einen optimalen Satz von Beleuchtungsbedingungen mit einer optimierten aggregierten Kostenzahl auszuwählen; und

    - eine Ausgabe (1204) zum Ausgeben des optimalen Satzes von Beleuchtungsbedingungen.


     
    14. System nach Anspruch 11, wobei die Verarbeitungsschaltung angeordnet ist, um die Hotspot-Schaltungsfunktionalität durch Anpassen einer Hotspot-Geometrie an einen Satz vorbestimmter Funktionsschaltungsstrukturen (1203) zu identifizieren; und wobei die Funktionen von lokalen Kostenzahlen nach vorbestimmten Klassen klassifiziert werden, die der identifizierten Hotspot-Schaltungsfunktionalität zugeordnet sind.
     
    15. System nach Anspruch 11, wobei die Eingabe eine Eingabe von Konstruktionlayoutdaten (1211) umfasst; und wobei die Verarbeitungsschaltung (1202) so angeordnet ist, dass sie die Konstruktionlayoutdaten empfängt, um eine Funktion von lokalen Kostenzahlen als Antwort auf die Konstruktionlayoutdaten eines Polygonmusters auszuwählen.
     


    Revendications

    1. Méthode de sélection d'un ensemble de conditions d'éclairage d'un appareil lithographique, dans un processus de transfert d'une disposition de circuit intégré vers un substrat cible, la disposition étant constituée d'un certain nombre de motifs polygonaux ayant une relation géométrique prédéterminée les uns par rapport aux autres, la méthode comprend les étapes consistant à :

    - fournir un ensemble initial de conditions d'éclairage ;

    - fournir une pluralité de motifs polygonaux (1, 20, 30, 40) à partir du certain nombre de motifs polygonaux (2, 3 ; 20, 21 ; 30, 31 ; 40, 41) nécessitant des conditions d'éclairage critiques pour une fonctionnalité de circuit ;

    - calculer pour l'ensemble initial de conditions d'éclairage un certain nombre de coût local pour chaque motif polygonal de la pluralité de motifs polygonaux (2, 3 ; 20, 21 ; 30, 31 ; 40, 41), définissant une mesure de différence d'au moins une dimension critique entre le motif polygonal et un motif polygonal transféré en fonction de la condition d'éclairage ;

    - agréger pour chaque motif polygonal de la pluralité de motifs polygonaux (2,3 ; 20,21 ; 30,31 ; 40,41) les certains nombres de coût local ; et

    - faire varier les conditions d'éclairage de manière à sélectionner un ensemble optimal de conditions d'éclairage ayant un nombre de coût agrégé optimisé, dans laquelle la méthode comprenant en outre l'étape consistant à :

    - identifier la pluralité de motifs polygonaux (2, 3 ; 20, 21 ; 30, 31 ; 40, 41) comme éléments de circuit complexes prédéfinis (1, 20, 30, 40) et dans laquelle les nombres de coût sont exprimés comme fonctions de nombre de coût d'élément de circuit qui sont associés individuellement auxdits éléments de circuit complexes identifiés (1, 20, 30, 40), de façon à exprimer le but de la conception de circuit.


     
    2. Méthode selon la revendication 1, comprenant en outre la sélection d'une pluralité de régions de points d'accès (1) dans la disposition de circuit intégré de façon à fournir la pluralité de motifs polygonaux à partir du nombre de motifs polygonaux (2,3 ; 20,21 ; 30,31 ; 40,41) en tant que nombre sélectionné de régions de points d'accès (1), les régions de points d'accès nécessitant des conditions d'éclairage critiques pour une fonctionnalité du circuit et classées selon une mesure de criticité.
     
    3. Méthode selon la revendication 1, comprenant en outre l'appariement des motifs polygonaux à un ensemble prédéfini d'éléments de circuit, et la sélection pour chaque motif polygonal de la pluralité de motifs polygonaux d'une fonction de nombre de coût local par rapport à un élément de circuit apparié (1, 20, 30, 31, 32, 40, 44, 45).
     
    4. Méthode selon la revendication 3, dans laquelle l'appariement comprend la détermination de la présence du motif polygonal dans une disposition de couches empilées prédéfinie (40, 44, 45).
     
    5. Méthode selon la revendication 1, dans laquelle la pluralité de motifs polygonaux est fournie associée à une couche d'indicateur d'éléments de circuit complexes indiquant des éléments de circuit complexes dans les motifs polygonaux ; et dans laquelle les fonctions de nombre de coût d'élément de circuit sont calculées sur la base de ladite couche d'indicateur d'éléments de circuit complexes.
     
    6. Méthode selon la revendication 1, dans laquelle la fonction de nombre de coût local augmente de façon plus que quadratique lorsqu'un motif polygonal est transféré à l'extérieur d'une région cible prédéterminée.
     
    7. Méthode selon la revendication 1, dans laquelle la fonction de nombre de coût local est constante lorsqu'un motif polygonal est transféré dans une région géométrique prédéterminée.
     
    8. Méthode selon la revendication 1, dans laquelle les fonctions de nombre de coût local sont des fonctions exponentielles et/ou des fonctions discontinues.
     
    9. Méthode selon la revendication 1, dans laquelle ledit nombre de coût local représente un rendement prévu lié à une impression ; une valeur de performance de circuit électrique prévue ; une qualité de traversées connectant de multiples couches conductrices dans la conception, une qualité d'éléments électriques dans la disposition de circuit, et/ou une sensibilité à l'électro-migration.
     
    10. Méthode selon la revendication 1, dans laquelle ladite pluralité de motifs polygonaux est fournie en stockant des coordonnées de coin et de bord des motifs polygonaux.
     
    11. Produit de programme informatique, comprenant des parties de code de programme pour exécuter les étapes d'une méthode selon l'une quelconque des revendications 1 à 8, lorsqu'il est exécuté sur un appareil programmable.
     
    12. Article de fabrication avec un support utilisable par ordinateur contenant des instructions lisibles par ordinateur pour fournir un accès à des ressources disponibles sur cet ordinateur, l'ordinateur comprenant des instructions lisibles par ordinateur pour amener l'ordinateur à exécuter les étapes d'une méthode selon l'une quelconque des revendications 1 à 8.
     
    13. Système (1200) pour sélectionner un ensemble de conditions d'éclairage d'un appareil lithographique pour une disposition de circuit intégré à transférer sur un substrat cible, la disposition comprenant un certain nombre de motifs polygonaux ayant une relation géométrique prédéterminée les uns par rapport aux autres, le système comprenant :

    - une entrée (1201) pour recevoir un ensemble initial de conditions d'éclairage et pour recevoir une pluralité de motifs polygonaux à partir du nombre de motifs polygonaux nécessitant des conditions d'éclairage critiques pour une fonctionnalité de circuit

    - un circuit de traitement (1202) agencé pour

    ∘ identifier une pluralité de motifs polygonaux en tant qu'éléments de circuit complexes prédéfinis ;

    ∘ calculer pour l'ensemble initial de conditions d'éclairage un nombre de coût local pour chaque motif polygonal de la pluralité de motifs polygonaux, définissant une mesure de différence d'au moins une dimension critique entre le motif polygonal et un motif polygonal transféré en fonction de la condition d'éclairage ; dans lequel le nombre de coût local est exprimé sous la forme d'une fonction de nombre de coût d'élément de circuit qui est individuellement associée audit élément de circuit complexe identifié, de façon à exprimer l'intention de conception d'élément de circuit ;

    ∘ agréger pour chaque motif polygonal les nombres de coût local ; et

    ∘ faire varier les conditions d'éclairage de façon à sélectionner un ensemble optimal de conditions d'éclairage ayant un nombre de coût agrégé optimisé ; et

    - une sortie (1204) pour délivrer en sortie ledit ensemble optimal de conditions d'éclairage.


     
    14. Système selon la revendication 11, dans lequel le circuit de traitement est agencé pour identifier la fonctionnalité de circuit de points d'accès en faisant correspondre une géométrie de points d'accès avec un ensemble de structures de circuit fonctionnel prédéterminées (1203) ; et dans lequel lesdites fonctions de nombre de coût local sont classées selon des classes prédéterminées associées à la fonctionnalité de circuit de points d'accès identifiée.
     
    15. Système selon la revendication 11, l'entrée comprenant une entrée de données de disposition de conception (1211) ; et dans lequel le circuit de traitement (1202) est agencé pour recevoir les données de disposition de conception afin de sélectionner une fonction de nombre de coût local en réponse aux données de disposition de conception d'un motif polygonal.
     




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    REFERENCES CITED IN THE DESCRIPTION



    This list of references cited by the applicant is for the reader's convenience only. It does not form part of the European patent document. Even though great care has been taken in compiling the references, errors or omissions cannot be excluded and the EPO disclaims all liability in this regard.

    Patent documents cited in the description