Field of the invention
[0001] The present disclosure is related to the production of metal-insulator-metal capacitor (MIMCAP) structures for use in semiconductor devices. The main application is the use of MIMCAPs in random-access memory such as DRAM devices.
Background of the invention
[0002] The DRAM 3X nm node will require MIMcaps with low leakage at an equivalent oxide thickness (EOT) of 0.4 nm or lower, deposited with highly conformal atomic layer deposition (ALD) processes for compatibility with large aspect ratio structures. Hafnium- or zirconium-based dielectrics with a dielectric constant (k) lower than 40 used currently in production are incapable of meeting this requirement, and expected to be scalable only to EOT higher than 0.6 nm. The only ALD high-k dielectric films which have shown promising results for scaling below 0.6 nm are strontium titanium oxides (STO) and Al-doped rutile titanium oxide grown on Ru-based bottom electrode (BE). However, according to previously reported data for MIMcap with ALD grown dielectrics, leakage increased to values higher than 10
-4 A/cm
2 when scaling EOT to 0.4 nm, raising a serious concern on the possibility of continuing DRAM scaling towards the 3X node.
[0003] Document
US2009/297696A1 relates to the deposition of conductive titanium oxide films by atomic layer deposition processes. Amorphous doped titanium oxide films are deposited by ALD processes comprising titanium oxide deposition cycles and dopant oxide deposition cycles and are subsequently annealed to produce a conductive crystalline anatase film. Doped titanium oxide films may also be deposited by first depositing a doped titanium nitride thin film by ALD processes comprising titanimn nitride deposition cycles and dopant nitride deposition cycles and subsequently oxidizing the nitride film to form a doped titanium oxide film. The doped titanium oxide films may be used, for example, in capacitor structures.
[0004] In document
EP2166562A2, a method is disclosed for manufacturing Sr
xTi
yO
3 based metal-insulator-metal (MIM) capacitors using a low temperature Atomic Layer Deposition (ALD) process. Preferably TiN is used to form the bottom electrode. The Sr/Ti ratio in the Sr
xTi
yO
3 dielectric layer of the capacitor can be varied to tune the electric properties of the capacitor. The dielectric constant and the leakage current of the Sr
xTi
yO
3 dielectric layer decrease monotonously with the Sr content of this Sr
xTi
yO
3 dielectric layer. By increasing the Sr content at the interface between the Sr
xTi
yO
3 dielectric layer and the TiN bottom electrode, the interfacial equivalent-oxide thickness (EOT) can be further reduced.
[0005] Document
US2010/0052024A1 describes a capacitor insulating film including strontium, titanium, and oxygen. The capacitor insulating film has a ratio of a spectrum intensity of crystal face of the capacitor.
[0006] Document
EP1130655A2 describes a capacitor structure comprising a bottom electrode, an insulator and a top electrode, and a method for manufacturing the same. The bottom and top electrodes preferably include a metal portion and a conducting oxygen-containing metal portion. In one embodiment, a layer of ruthenium is deposited to form a portion of the bottom electrode. Prior to deposition of the insulator, the ruthenium is annealed in an oxygen-containing environment. The insulator is then deposited on the oxygen-containing ruthenium layer. Formation of the top electrode includes depositing a first metal on the insulator, annealing the first metal and then depositing a second metal. The first and second metals may be ruthenium.
[0007] Document
WO2010/141668A2 is related to methods of forming a strontium titanate (SrTiO
3) film using atomic layer deposition (ALD). More particularly, the method includes forming a plurality of titanium oxide (TiO
2) unit films using ALD and forming a plurality of strontium oxide (SrO) unit films using ALD. The combined thickness of the TiO
2 and SrO unit films is less than approximately 5 Ǻngströms. The TiO
2 and SrO units films are then annealed to form a strontium titanate layer.
Summary of the invention
[0008] The present invention is related to a method and devices as disclosed in the appended claims. The invention is thus related to a method for producing a stack of layers on a semiconductor substrate, as disclosed in appended claim 1.
[0009] According to an embodiment of the method of the invention, said sub-stack of layers is produced by the following steps :
- By atomic layer deposition, depositing on said first conductive layer an intermediate layer of TiO2,
- By atomic layer deposition, depositing on said intermediate TiO2 layer, a layer of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization.
[0010] According to another embodiment, said sub-stack of layers is produced by the following steps :
- By atomic layer deposition, depositing on said first conductive layer, a layer of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization,
- By atomic layer deposition, depositing on said layer of dielectric material, said layer of TiO2.F
[0011] In the method of the invention, a sequence of alternating TiO
2 layers and dielectric layers or vice versa may be deposited by atomic layer deposition on said first conductive layer.
According to an embodiment, the crystallized dielectric layer has a ratio Sr/(Sr+Ti) higher than 50% and lower than 65%.
[0012] According to a preferred embodiment, the ratio Sr/(Sr+Ti) of said metastable STO layer is between 51% and 65%.
[0013] According to a preferred embodiment, said thermal treatment is a thermal anneal at a temperature lower than or equal to 600°C in an inert atmosphere.
[0014] According to an embodiment, said first conductive layer comprises at least at its top surface a material that stores excess oxygen, creating a reservoir of oxygen, and resulting in release of oxygen from the first conductive layer towards the dielectric during said heat treatment.
[0015] Furthermore, said second conductive layer may comprise at least at its bottom surface a material that stores excess oxygen, creating a reservoir of oxygen, and resulting in release of oxygen from the second conductive layer towards the dielectric during a subsequent heat treatment.
[0016] According to the invention, said material that stores excess oxygen is ruthenium oxide.
Brief description of the drawings
[0017] All drawings are intended to illustrate some aspects and embodiments of the present disclosure. The drawings described are only schematic and are non-limiting. In the formula TiO
x used in the drawings, the value of x is 2.
Fig. 1 illustrates schematically the process flow (top) and the MIMCap stack (bottom) fabricated in a 300 mm manufacturing line, using the stack engineering of the invention with controlled Ru oxidation and interfacial TiO2 layer.
Fig. 2 represents the controlled Ru oxidation process, showing evolution of Ru and RuOx thicknesses as determined by XRR (X-ray reflectivity). Smooth films are obtained without large RuOx crystals or surface roughening.
Fig. 3 (a) shows schematically the STO ALD deposition; (b) STO composition control by varying the Sr to Ti pulse ratio.
Fig. 4 shows the properties (permittivity, band gap and lattice parameter) of metastable perovskite STO films as a function of Sr content.
Fig. 5 shows (a) CV characteristics and (b) capacitance vs. area characteristics of TiN/Ru/RuOx/TiO2/STO/TiN MIMCaps, showing well behaved CVs with good area scaling. Layer thicknesses and extracted EOT values are shown in the legend on top.
Fig. 6 shows (a) EOT vs deposited STO thickness for a stack with 0.5 nm TiO2 interfacial layer; and (b) EOT vs deposited TiO2 thickness for stack with 8 nm STO. Symbols correspond to measured data and the solid line to calculations assuming mixing of the TiO2 and STO layers during crystallization (resulting in higher Ti-content STO and higher k-value).
Fig. 7 shows (top) cross section TEM images after crystallization anneal and TiN top electrode (TE) processing of MIMCap stacks; and (bottom) SEM top view images after crystallization anneal for: (a) TiN/Ru/RuOx/TiO2/STO deposited stack with 0.5 nm TiO2 and (b) TiN/Ru/RuOx/STO deposited stack (without TiO2). No differences in microstructure are observed between the two stacks despite the significant reduction in EOT obtained with the TiO2 layer.
Fig. 8 shows the X-ray diffraction pattern of TiN/Ru/RuOx/TiO2/Sr-rich STO stacks after crystallization anneal, for varying TiO2 thickness. The peak position of STO shifts with TiO2 thickness indicating a change in lattice parameter. The vertical line corresponds to the position of the bulk stoichiometric STO (110) diffraction.
Fig. 9 shows (a) STO lattice parameter extracted from XRD data in Fig. 8 vs. TiO2 thickness; (b) resulting STO composition as calculated (using correlations in Fig. 4) from the measured lattice parameter shift or by assuming intermixing of the TiO2 and Sr-rich STO layers, (c) k-values corresponding to the calculated compositions (using correlations in Fig. 4). EOTs estimated using mixing model fit well with measured values (Fig. 6).
Fig. 10 shows the leakage/area vs. voltage V for TiN/Ru/RuOx/TiO2/Sr-rich STO/TiN MIMcaps of different areas fabricated with 0.5 nm TiO2. Excellent area scaling is observed.
Fig. 11 shows leakage density vs. voltage V for TiN/Ru/RuOx/TiO2/Sr-rich STO/TiN MIMcaps. Positive voltages correspond to electron injection from the bottom RuOx electrode and negative polarity to electrons injection from the top TiN electrode. Leakage becomes more asymmetric for thinner EOT values.
Fig 12 shows the area leakage density vs EOT (top: ±1V, bottom: 0.8V), comparing Ru/RuOx/TiO2/STO/TiN stacks (this disclosure) to best literature data (benchmark) showing significant improvement.
Fig. 13 shows a schematic cross-section of the capacitor stack after dielectric deposition (a), crystallization anneal (b), TiN deposition and etch (completed capacitor) (c).
Fig. 14 shows a) EOT vs. deposited TiO2 thickness and corresponding dielectric constant (symbols correspond to measured data and solid line to calculations assuming mixing of the TiO2 and STO layers during crystallization); b) XRD patterns after crystallization anneal for varying deposited TiO2 thickness.
Fig. 15 shows Jg vs voltage (V) of completed MIM capacitors comparing the same deposited dielectric stack on various BE (a), and for optimal stacks on RuOx BE (b) .
Fig. 16 shows Jg vs. EOT at 1.0 V (a), 0.8 V (b) and -1.0 V (c), comparing results of this disclosure with literature benchmarks.
Detailed description of the invention
[0018] The present invention is related to a MIM capacitor with improved performance with respect to the state of the art. More specifically, it is related to a MIM capacitor suitable to be used in advanced DRAM devices such as DRAM of 3X nm node having a leakage of 10
-6A/cm
2 or lower for sub-0.5nm EOT.
[0019] The invention is related to a metal-insulator-metal capacitor comprising :
- A bottom electrode,
- On said bottom electrode a dielectric layer comprising or consisting of a dielectric material having a cubic perovskite structure,
- On said dielectric layer, a top electrode,
wherein the k-value of said dielectric layer is between 50 and 100 and the EOT of the MIM capacitor is between 0.35nm and 0.55nm.
[0020] According to a preferred embodiment, the bottom electrode consists of or comprises on its surface a metal layer or a metal layer covered by a layer of an oxide of said metal. In a MIMCAP according to the invention, said metal can be titanium nitride, ruthenium or any other metal suitable to form a bottom electrode. Preferably a metal is used of which the oxide has metallic characteristics so as not to contribute to the EOT. An example of such a metal is ruthenium (Ru). Said electrode therefore preferably consists of or comprises on its top surface a Ru layer or a Ru layer covered by ruthenium oxide. Possibly the bottom electrode comprises a stack of metal layers, e.g. a layer of TiN is first deposited on the substrate, and the Ru layer is deposited onto the TiN layer.
[0021] In a MIMCAP according to the invention, the dielectric layer may consist of a Sr-rich Strontium-Titanium oxide (STO), i.e. an Sr-Ti oxide (general formula Sr
xTi
yO
z) wherein the Sr/Ti ratio x/y is higher than 1, i.e. Sr/(Sr+Ti) is higher than 50%. Preferably in a MIMCAP according to the invention, the Sr/(Sr+Ti) ratio of the crystallized material, referred herein below as final Sr/(Sr+Ti) ratio is higher than 50% and lower than 65%, more preferably between 55% and 62% and even more preferably between 58% and 61%. Sr-rich STO layers (e.g. Sr/(Sr+Ti) at about 62%) have better leakage properties than stoichiometric STO films. This is due to the formation of large STO grains (with a grain size larger than 500 nm) with nano-cracks and star-shape patterns (as observed by SEM) in crystallization of stoichiometric films, while small grain size (grain size of about 50 nm) crack-free films are obtained upon crystallization of Sr-rich STO. So far in the prior art however, it was not possible to obtain a MIMcap with a Sr-rich STO dielectric layer that had a k-value of more than 50 combined with EOT lower than 0.4nm. A MIMcap according to the invention has a dielectric layer with a k-value between 50 and 100 and has an EOT between 0.35nm and 0.55nm. This is achieved by performing the method of the invention as described hereafter.
[0022] The invention is thus equally related to a method for producing a stack of layers on a semiconductor substrate, suitable for producing a MIMCAP as described above, the method comprising the steps of :
- Providing a substrate,
- producing on said substrate a first conductive layer, preferably a metal layer, or a metal layer covered by an oxide of said metal,
- producing a sub-stack of layers by ALD on said first conductive layer, at least one of said layers of the sub-stack being a TiO2 layer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers,
- subjecting the substrate including said sub-stack of layers to a heat treatment to thereby obtain a crystallized dielectric layer on the first conductive layer,
- producing a second electrically conductive layer on said crystallized dielectric layer.
The first and second conductive layers can themselves consist of a stack of conductive layers. Alternatively, the second conductive layer may be produced on the sub-stack of layers as described above, and the heat treatment applied to the substrate including the sub-stack and the second conductive layer.
[0023] In the context of the present disclosure and without being bound by theory, it is understood that upon subjecting the sub-stack to a heat treatment, an intermixing takes place and a dielectric layer with a cubic perovskite structure is formed. The at least one TiO
2 layer intermixes with the other layers to thereby form a dielectric layer between the first and second conductive layer. The TiO
2 layer increases the Ti-content of the dielectric layer while not affecting its microstructure. This allows obtaining a MIMcap with superior quality in terms of the k-value, leakage and EOT. Said intermixing results in a uniform STO layer with higher Ti content and consequently higher k-value. The final STO composition of a fully intermixed stack depends on the deposited thicknesses of the various layers in the sub-stack.
[0024] According to one embodiment, the method of the invention comprises the steps of :
- Providing a substrate,
- producing on said substrate a first conductive layer, preferably a metal layer, or a first metal layer covered by an oxide of said metal,
- By atomic layer deposition, depositing on said first conductive layer an intermediate layer of TiO2,
- By atomic layer deposition, depositing on said TiO2 layer, a layer of a dielectric material, to thereby obtain a sub-stack of a TiO2 layer and a second dielectric layer, said dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of the stack formed of said TiO2 layer and said second dielectric layer,
- subjecting the substrate including said sub-stack to a heat treatment to thereby obtain a crystallized dielectric layer,
- producing a second conductive layer on said crystallized dielectric layer.
[0025] In alternative embodiments said second dielectric layer is deposited first, overlying and in contact with said first conductive layer. The TiO
2 layer is deposited second, overlying and in contact with the second dielectric layer and underlying the second conductive layer.
[0026] Yet in other embodiments sub-layers of the TiO
2 layer and sub-layers of the second dielectric layer are formed alternately.
[0027] The second dielectric layer can be a Sr-rich STO. According to another embodiment, the sub-stack may comprise, besides the one or more TiO
2 layers, layers of a material which in itself does not form a perovskite phase upon crystallization, preferably combined in the sub-stack with layers that do form such a phase upon crystallization. For example, the sub-stack may contain one or more layers of SrO and one or more layers of STO. The layer of SrO in itself does not form a perovskite phase upon crystallization, but the combined stack of SrO and STO does form such a phase. The function of the SrO is then to control the final composition of the cubic perovskite phase.
[0028] According to a preferred embodiment, the thermal treatment is a rapid thermal process (RTP) anneal in N
2 or other inert ambient at a temperature lower than or equal to about 600°C. Preferably the thermal anneal is performed after depositing said sub-stack of layers, and before forming the second conductive layer.
[0029] During or after the ALD of the sub-stack, dopants may be added to the dielectric layer, according to known doping methods. The dopants can be chosen from the group consisting of: Sr, Ti, Ta, Al, Hf, Gd, Zr, Sc, Dy.
[0030] According to a preferred embodiment described hereafter in more detail, the dielectric layer that is present between the first and second conductive layers after the heat treatment step, is a Sr-rich STO layer. The Sr-rich STO layer is formed upon applying a thermal treatment to a stack of dielectric layers consisting of and arranged in random order from bottom to top : at least one TiO
2 layer, at least one sub-layer of metastable phase STO and possibly at least one layer of strontium oxide (SrO). The Sr/(Sr+Ti) final ratio is the Sr/(Sr+Ti) ratio after annealing. A metastable phase STO layer is a layer that is either Sr rich or Ti rich. A Ti-rich STO layer is a layer wherein the ratio Sr/Sr+Ti is lower than 50%, preferably between 40% and 49%. In that case, the use of one or more SrO layers in the sub-stack is required so that the final dielectric layer is a Sr-rich STO (ratio Sr/Sr+Ti higher than 50%).
[0031] The metastable phase STO may be formed by ALD deposition of a STO material with the Sr/(Sr+Ti) ratio between 51% and 65%. More preferably the Sr/(Sr+Ti) ratio of the as-deposited metastable phase is between 55% and 65%, even more preferably between 58% and 62%.
[0032] In the embodiments wherein a STO metastable phase with less than 58% Sr/(Sr+Ti) is deposited, a layer of SrO is deposited either underlying and/or overlying the STO, such that upon a thermal treatment the final Sr/(Sr+Ti) ratio is reached. Preferably, the thickness of the SrO layer is lower or equal to 2nm.
[0033] Alternatively, a more homogeneous distribution can be obtained by alternating sub-layers of metastable STO with sub-layers of SrO. Preferably, the total thickness of the different SrO sub-layers is lower or equal to 2nm.
[0034] In the embodiments wherein a STO metastable phase with more than 55% Sr/(Sr+Ti) is deposited, said layer of TiO
2 can be deposited either underlying and/or overlying the STO, such that upon a thermal treatment the targeted Sr/(Sr+Ti) ratio is reached. Preferably, the thickness of the TiO
2 layer is lower or equal to 2nm.
[0035] Alternatively, a homogeneous distribution can be obtained by alternating sub-layers of metastable STO with sub-layers of TiO
2. Preferably, the total thickness of the different TiO
2 sub-layers is lower or equal to 2nm.
[0036] The top electrode made of a second conductive layer may be a Ru or a TiN layer or any other suitable layer.
[0037] In prior art MIMcaps, the bottom electrode scavenges (takes/captures) oxygen from the dielectric during the dielectric crystallization anneal, resulting in defects in the dielectric associated with oxygen deficiency (e.g. oxygen vacancies), which increase the trap density in the dielectric and thus the leakage in the capacitor.
[0038] According to a preferred embodiment of the present invention, a bottom electrode is used which, on the contrary to the above mentioned scavenging mechanism, stores excess oxygen (at least at the top surface of the bottom electrode) which can be released to the dielectric during the crystallization anneal, thus "healing" the defects and reducing the leakage. The bottom electrode behaves as a reservoir of oxygen which is released to the dielectric during the crystallization anneal, thus healing the defects and reducing the leakage.
[0039] An example of this type of electrodes is oxidized Ru. In the embodiments of the low pressure oxidized Ru electrode (i.e. first conductive layer with a ruthenium oxide layer on top), excess oxygen is stored that is then released to the STO during crystallization anneal. Other noble metals or near noble metals or their oxides (preferably obtained by an oxidizing anneal) could function in the same way. Illustrative examples of such materials suitable to form the bottom electrode are: Pt, IrO
x and any mixtures or combinations thereof.
[0040] Similarly, for the top electrode (second conductive layer), materials that are deposited in an oxidizing ambient and/or with processes that result in excess oxygen in the conductive layer, or at least at the bottom surface of the top electrode, are preferred. This prevents scavenging from the top electrode during further processing, and may even reverse the effect resulting in additional oxygen incorporation, i.e. further "healing" of the dielectric during subsequent processing, in the region of the dielectric in the vicinity of the top electrode.
[0041] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. When it is stated in this description that a layer is produced 'on' another layer, this preferably means that the layer is on and in contact with said other layer, though it is not excluded that intermediate layers are present between the two layers. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.
[0042] The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways, and is therefore not limited to the embodiments disclosed. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being re-defined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated.
Examples - test results
[0043] In a first series of experiments, MIM capacitors were fabricated in a 300 mm line. The flow sequence and a schematic cross-section of the MIMcap stack are shown in Fig. 1.
[0044] Ruthenium films with a thickness of 5 nm were deposited by ALD with excellent smooth surfaces (lower than 0.2 nm RMS by AFM) on 10 nm TiN. Some wafers were left without Ru, i.e. with TiN bottom electrode (BE), for comparison.
[0045] A controlled oxidation process as shown in Fig. 2 was applied to the wafers with Ru BE, resulting in ultrathin, controlled oxidation of the surface forming a 1 nm ruthenium oxide (hereafter called 'RuOx') layer with no penalty in roughness (i.e. maintaining a value lower than 0.2 nm RMS by AFM). This controlled oxidation is obtained by subjecting the Ru bottom electrode layer to a low-pressure atmosphere consisting of O
2 or consisting of a mixture of O
2 and one or more inert gases such as N
2. The pressure or partial pressure of O
2 is between 1mTorr and 10 Torr (i.e. between 0.13Pa and 1333.22Pa). The temperature during oxidation is between 200°C and 450°C. The oxidation time is between lmin and 30min, with lower oxidation times being applicable for higher temperatures.
[0046] Previously reported oxidation processes result in either formation of large RuOx crystals or significant roughening of the film surface, both unacceptable for DRAM MIMcap manufacturing.
[0047] A thin TiO
2 interfacial layer with a thickness of 0.5 or 1 nm, was then grown by ALD at 250°C with Ti(OCH
3)
4 and H
2O as oxidant. Some wafers were kept without the TiO
2 interfacial layer for comparison.
[0048] STO films with a thickness of 7 to 9 nm were then deposited by ALD at 250°C using Sr(t-Bu
3Cp)
2 and Ti(OCH
3)
4 precursors and H
2O as oxidant. Good composition control over a large Sr/Ti range is obtained by adjusting the Sr to Ti pulse ratio as shown in Fig. 3.
[0049] Films were crystallized by rapid thermal processing (RTP) annealing in N
2 at a temperature lower or equal to 600°C. The properties of crystallized STO films depend on the composition, as shown in Fig. 4 for films without TiO
2 interface layer, with k-value decreasing and lattice parameter increasing with increasing Sr. Only a small change is observed in band gap value.
[0050] After crystallization and top electrode (TE) processing (TiN patterned by reactive ion etching RIE), films were characterized electrically. EOT values were extracted from CV measurements as shown in Fig. 5.
[0051] Well behaved CVs and excellent area scaling was found. EOT increases with increasing deposited STO thickness as shown in Fig. 6(a). The apparent k-value extracted from the slope of this plot (for TiO
2=0.5 nm), k about 85, is higher than expected for Sr-rich STO (without the TiO
2 layer (see fig. 4), the obtained k-value is about 65 at Sr/(Sr+Ti)=62%).
[0052] An even more important observation, however, is that EOT was found to decrease with increasing deposited interfacial TiO
2 thickness for the same STO thickness as shown in Fig. 6(b).
[0053] TEM characterization of MIM stacks after the crystallization anneal, and TiN TE processing with and without 0.5 nm TiO
2 interfacial layer showed no observable difference as shown in Fig. 7(a).
[0054] In both cases, grain size remains small (smaller than/equal to 50 nm). Similarly, no difference was observed by top view SEM analysis between stacks with and without 0.5 nm interfacial TiO
2 after crystallization anneal as shown in Fig. 7(b).
[0055] XRD analysis, however, revealed STO peak shifts correlated to the deposited interfacial TiO
2 thickness as shown in Fig. 8. This indicates that the composition of the STO films after crystallization changes with TiO
2 thickness, and can be understood in terms of the intermixing of TiO
2 and STO layers during crystallization anneal as shown in Fig. 9.
[0056] Due to the intermixing, the resulting crystallized films have higher Ti content than the deposited STO films, and in consequence a higher k-value and lower EOT as shown in Figs. 9 and 6. However, the films keep the favorable microstructure of the Sr-rich films.
[0057] IV characteristics showed excellent area scaling as represented in Fig. 10. Typical leakage density vs. voltage(V) plots are shown in Fig. 11. As EOT decreases, leakage becomes more asymmetric, with lower leakage obtained in positive polarity corresponding to injection from RuOx. This is attributed to the higher work function (WF) of RuOx compared to the TiN top electrode.
[0058] Jg-EOT plots are shown in Fig. 12, where data according to the invention are compared to best literature data for benchmarking. It is observed that the addition of TiO
2 layer results in a large decrease in EOT without much penalty in leakage. Low leakage values of Jg of 10
-6 A/cm
2 and 10
-8 A/cm
2 are achieved for EOT of 0.4 nm and 0.5 nm, respectively at 0.8V. These values are compared favorably with the state of the art MIMcaps with ALD grown high-k dielectrics, representing more than 100 x Jg reduction at 0.4 nm EOT.
[0059] As described earlier, the use of RuOx as bottom electrode instead of TiN or Ru provides a great advantage for leakage reduction. In this way leakage is reduced in both polarities for capacitors with TiN top electrodes. The improvement is due to the impact of the bottom electrode on STO dielectric quality, i.e. trap distribution, due to differences in oxygen scavenging during crystallization anneal.
[0060] In a further set of experiments, Sr-rich STO films (7-10nm) were deposited on thin (0, 0.5, 1nm) TiO
2 layers on various bottom electrodes: TiN, Ru, RuO
x. The RuO
x bottom electrode was formed by low pressure oxidation of Ru at 250°C, resulting in a thin (1 Nm) RuO
2 layer on top of the Ru film. Both dielectrics were deposited by ALD, using Sr(
tBu
3Cp)
2 and Ti(OMe)
4 as metal precursors and H
2O as oxidizer, at 250°C. As deposited STO films are amorphous with k value < 20. In order to achieve higher k value the STO films were crystallized into the perovskite phase by rapid thermal processing (RTP) at 600°C in N
2 for 60s. For electrical characterization, TiN top electrodes were then deposited and patterned, forming MIM capacitors.
[0061] Fig. 13(a) shows the schematic cross section of a sample with RuO
x bottom electrode and TiO
2/Sr-rich STO dielectric stack, after dielectric deposition.
[0062] Fig. 14(a) shows the EOT as function of deposited TiO
2 thickness for MIM capacitors with RuO
x bottom electrodes and 9 nm (deposited) Sr-rich STO. A strong decrease in EOT is observed with increasing TiO
2 thickness. X-ray diffraction (XRD) patterns of the same dielectric stacks on RuOx, taken after crystallization anneal showed crystalline peaks corresponding to metastable perovskite STO, with no evidence of crystalline TiO
2 peaks. The 2-theta position of the STO (110) XRD peak is seen in Fig. 14(b) to increase with increasing TiO
2 layer thickness, indicating a corresponding decrease in lattice parameter. Both effects, the decrease in EOT and the decrease in lattice parameter can be explained by intermixing of the TiO
2 and Sr-rich STO layers during the crystallization anneal, resulting in a uniform STO layer with higher Ti content and consequently higher k-value (shown schematically in Fig. 13).
[0063] The final STO composition of a fully intermixed stack depends on the deposited thicknesses of both STO and TiO
2 layers, and varies in the range of Sr/(Sr+Ti)∼54-64% for the stacks explored in this set of experiments. The EOT of a fully intermixed layer can be calculated based on the known deposited Ti and Sr areal atomic concentrations as determined by Rutherford Backscattering Spectrometry (RBS), film thickness and densities as extracted from X-ray reflectivity analysis (XRR) and reported k-value dependence on STO Sr content. An excellent agreement is obtained between experimental EOT vs. TiO
2 thickness values and those calculated assuming full intermixing of the layers for all stacks studied (shown for stacks with 9 nm deposited STO thickness in Fig. 14(a)). Furthermore, the corresponding lattice parameters determined from the XRD spectra in Fig. 14(b) are also in good agreement with those expected for the calculated compositions of intermixed films (not shown), considering the lattice parameter-composition relation previously reported. Scanning electron microscope (SEM) studies performed after crystallization anneal as well as TEM studies performed after completion of the MIM structure showed no visible impact of the TiO
2 layer on the microstructure of the STO films, which maintained the small grain size characteristic microstructure of Sr-rich films, which is favorable for low leakage.
[0064] Jg-V plots for a 0.5 nm TiO
2/8 nm STO deposited stack (resulting in EOT=0.45 nm), and Jg-EOT plots for all stacks in this embodiment, comparing TiN, Ru and RuO
x bottom electrodes are shown in Figs 15 (a) and Fig. 16 respectively. EOT trends are similar for all bottom electrodes, and consistent with TiO
2/STO intermixing during anneal. Slightly lower EOTs obtained in some cases on TiN bottom electrode (BE) may be attributed to slight (unintentional) oxidation of the TiN, which results in additional incorporation of some Ti into STO (i.e intermixing of native oxide on TiN with STO). Considering the Jg-EOT behaviour at +1V (Fig. 16 (a)), it becomes apparent that TiN and Ru BE follow the same trendline. Comparing to results for deposited stoichiometric STO on TiN (1A/cm
2 (IV) at 0.5 nm EOT), it shows 4 orders of magnitude Jg improvement (to 10
-4 A/cm
2 (IV) at EOT=0.5nm) for TiN/STO/TiN MIM capacitors with the films obtained by intermixing TiO
2/STO in this embodiment, attributed to their better microstructure.
[0065] The largest improvement in leakage, however, was obtained when changing the bottom electrode from TiN or Ru to RuO
x (Figs. 15 and Fig 16). As shown in Fig. 16 (a), at +1V (e-injection from BE), MIM capacitors with deposited TiO
2/STO dielectric stacks and RuOx bottom electrode result in more than 3 orders of magnitude Jg reduction at the same EOT compared to the same dielectric stacks on TiN or Ru bottom electrodes (e.g. at 0.50 nm EOT: from 10
-4 A/cm
2 for 0.5 nm TiO
2/9 nm STO on TiN or Ru BE to 10
-7 A/cm
2 on RuO
x BE). Figure 15 (b) shows the comparison of the JG (EOT) trend lines at +0.8V obtained from the stacks of the disclosure (RuOx/1nmTiO
2/STO/TiN - crosses, RuOx/0.5nm TiO
2/STO/TiN - full symbols) with benchmark literature data (RuOx/Al doped Rutile TiO
2/Pt - stars, and Ru/STO/Pt), showing more than 2 orders of magnitude Jg reduction at 0.45 nm EOT with RuOx/TiO
2/STO stacks. The leakage at 0.45 nm EOT improves from 10
-5 A/cm
2 obtained for Al-doped Rutile TiO
2 to 10
-7 A/cm
2 with RuOx/0.5nm TiO
2/STO/TiN and can be reduced further to ∼3x10
-8 A/cm
2 when increasing the TiO
2 thickness from 0.5 to 1nm.
[0066] Remarkably, an improvement in Jg-EOT with RuOx bottom electrode (compared to TiN or Ru BE) is also observed for negative polarity, i.e. for e-injection from the top TiN electrode (Fig. 15 and 16 (c)). This is an indication of an effect of the BE on the dielectric itself. It is apparent that the leakage in Sr-rich STO films is not controlled by injection barriers from the electrode, but dominated by trap-assisted conduction, with trap energies at ∼ 0.8 eV below the STO conduction band edge, independently of the BE. These observations suggest that the Jg improvement with RuOx BE is likely not related to work function effects, but rather to a change in the trap density distribution within the STO film. A decrease in trap density in the vicinity of the RuOx BE would be consistent with the improvement in leakage being larger for e-injection from this electrode. In order to explain this effect, we consider scavenging effects during crystallization anneal, and associate traps in STO with oxygen deficiency. It is reasonable to assume that oxygen may be scavenged from the STO film to the electrode, for TiN or Ru electrodes. For the case of the Ru electrode oxidized at low temperature and low pressure, however, we note that this leads to formation of RuO
2 as well as subsurface oxygen species, and that oxygen from this surface oxidation can be released towards the STO during the STO crystallization anneal. Thus, we propose that the improvement in STO dielectric quality in the vicinity of the BE, with the oxidized Ru BE, is due to elimination or even reversal of oxygen scavenging by the BE during crystallization anneal, resulting in a lower trap density in STO in vicinity of the BE.
[0067] ALD deposited TiO
2/Sr-rich STO stacks intermix during crystallization anneal to form a perovskite STO dielectric with tailored (optimized) properties, including k-value tuned (by layer thicknesses) in the 50-100 range and small grain-size, crack-free microstructure, enabling to form capacitors with EOT in the 0.35-0.55 nm range with good electrical properties. Further, the use of this stack approach in combination with oxidized Ru BE results in low leakage capacitors even at aggressively scaled EOTs, with significant leakage reduction compared to TiN or Ru BE. Leakage improvement for both polarities, larger for e-injection from oxidized Ru, is attributed to reduction in trap density in STO in the vicinity of the oxidized Ru BE, in terms attributed to elimination or reversal of oxygen scavenging from the STO to the BE with RuOx BE. As shown, J
G of 10
-7 A/cm2 (at Jg=0.8V) at 0.4nm EOT was obtained, making the RuOx/TiO
2/STO/TiN stack a top candidate for future (i.e. 3X and further up to 1X) DRAM technology nodes.
1. Verfahren zum Herstellen eines Stapels von Lagen auf einem Halbleitersubstrat, wobei das Verfahren die Schritte umfasst:
• Bereitstellen eines Substrats,
• Herstellen einer ersten elektrisch leitfähigen Lage auf dem besagten Substrat,
• Herstellen eines Teilstapels von Lagen auf der besagten leitfähigen Lage mittels Atomlagenabscheidung, wobei zumindest eine der besagten Lagen des Teilstapels eine TiO2-Lage ist, wobei die eine andere oder die mehreren anderen Lagen des Teilstapels Lagen aus einem dielektrischen Material sind, mit einer Zusammensetzung die dazu geeignet ist, bei Kristallisation des Teilstapels von Lagen eine Kubischer-Perowskit-Phase zu bilden,
und es weiter umfasst:
• Unterziehen des Substrats, das den besagten Teilstapel von Lagen beinhaltet, einer Wärmebehandlung, um den Teilstapel von Lagen zu kristallisieren, so dass eine kristallisierte dielektrische Lage mit einer Kubischer-Perowskit-Struktur auf der besagten ersten leitfähigen Lage erhalten wird, indem die eine oder mehreren TiO2-Lagen vollständig mit der einen anderen Lage oder den mehreren anderen Lagen des Teilstapels vermischt werden,
• Herstellen einer zweiten elektrisch leitfähigen Lage auf der besagten kristallisierten dielektrischen Lage.
oder:
• Herstellen einer zweiten elektrisch leitfähigen Lage auf dem besagten Teilstapel von Lagen,
• Unterziehen des Substrats, das den besagten Teilstapel von Lagen und die besagte zweite leitfähige Lage beinhaltet, einer Wärmebehandlung, um den Teilstapel von Lagen zu kristallisieren, so dass eine kristallisierte dielektrische Lage mit einer Kubischer-Perowskit-Struktur auf der besagten ersten leitfähigen Lage erhalten wird, indem die eine oder mehreren TiO2-Lagen vollständig mit der einen anderen Lage oder den mehreren anderen Lagen des Teilstapels vermischt werden.
wobei:
- die eine oder mehreren Lagen aus einem dielektrischen Material sind mit einer Zusammensetzung die dazu geeignet ist, bei Kristallisation des Teilstapels von Lagen eine Kubischer-Perowskit-Phase zu bilden:
∘ eine oder mehrere Lagen aus strontiumreichem Strontiumtitanoxid STO in metastabiler Phase, wobei das Verhältnis von Sr/(Sr + Ti) höher als 50 % ist, und möglicherweise eine oder mehrere Lagen aus Strontiumoxid SrO
oder
∘ eine oder mehrere Lagen aus titanreichem Strontiumtitanoxid STO in metastabiler Phase, wobei das Verhältnis von Sr/(Sr + Ti) niedriger als 50 % ist, und eine oder mehrere Lagen aus Strontiumoxid SrO
- die kristallisierte dielektrische Lage mit einer Kubischer-Perowskit-Struktur eine Lage aus strontiumreichem Strontiumtitanoxid STO ist, wobei das Verhältnis Sr/(Sr + Ti) höher als 50 % ist.
2. Verfahren nach Anspruch 1, wobei der besagten Teilstapel von Lagen mit den folgenden Schritten hergestellt wird:
• durch Atomlagenabscheidung, Abscheiden der besagten Lage aus TiO2 auf der besagten ersten leitfähigen Lage,
• durch Atomlagenabscheidung, Abscheiden der besagten Lage aus einem dielektrischen Material mit einer Zusammensetzung, die dazu geeignet ist, bei Kristallisation eine Kubischer-Perowskit-Phase zu bilden, auf der besagten TiO2-Zwischenlage.
3. Verfahren nach Anspruch 1, wobei der besagten Teilstapel von Lagen mit den folgenden Schritten hergestellt wird:
• durch Atomlagenabscheidung, Abscheiden der besagten Lage aus einem dielektrischen Material mit einer Zusammensetzung die dazu geeignet ist, bei Kristallisation eine Kubischer-Perowskit-Phase zu bilden, auf der besagten ersten leitfähigen Lage.
• durch Atomlagenabscheidung, Abscheiden der besagten Lage aus TiO2 auf der besagten Lage aus dielektrischem Material.
4. Verfahren nach einem der vorstehenden Ansprüche, wobei eine Folge von abwechselnden TiO2-Lagen und Lagen aus einem dielektrischen Material oder umgekehrt durch Atomlagenabscheidung auf der besagten ersten leitfähigen Lage abgeschieden wird, um den besagten Teilstapel von Lagen zu bilden.
5. Verfahren nach einem der vorstehenden Ansprüche, wobei das Verhältnis Sr/(Sr + Ti) der besagten metastabilen STO Lage zwischen 51 % und 65 % beträgt.
6. Verfahren nach einem der vorstehenden Ansprüche, wobei die besagte Wärmebehandlung ein Wärmeglühen bei einer Temperatur von weniger als oder gleich 600 °C unter Inertatmosphäre ist.
7. Verfahren nach einem der vorstehenden Ansprüche, wobei die besagte erste leitfähige Lage zumindest auf ihrer Deckfläche ein Material umfasst, das überschüssigen Sauerstoff speichert, wodurch ein Sauerstoffreservoir gebildet wird und Sauerstoff aus der besagten ersten leitfähigen Lage während der Wärmebehandlung hin zum Dielektrikum freigesetzt wird, wobei das besagten Material, das überschüssigen Sauerstoff speichert, Rutheniumoxid ist.
8. Verfahren nach einem der vorstehenden Ansprüche, wobei die besagte zweite leitfähige Lage zumindest auf ihrer Unterseite ein Material umfasst, das überschüssigen Sauerstoff speichert, wodurch ein Sauerstoffreservoir gebildet wird und Sauerstoff aus der besagten zweiten leitfähigen Lage während einer darauffolgenden Wärmebehandlung hin zum Dielektrikum freigesetzt wird, wobei das besagten Material, das überschüssigen Sauerstoff speichert, Rutheniumoxid ist.