(19)
(11)EP 2 437 073 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
25.03.2020 Bulletin 2020/13

(21)Application number: 11181290.5

(22)Date of filing:  14.09.2011
(51)International Patent Classification (IPC): 
G01R 19/02(2006.01)
G01R 19/04(2006.01)

(54)

RMS and envelope detector

Effektivwert und Hüllkurvendetektor

RMS et détecteur d'enveloppe


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 17.09.2010 US 383820 P

(43)Date of publication of application:
04.04.2012 Bulletin 2012/14

(73)Proprietor: Hittite Microwave LLC
Chelmsford, MA 01824 (US)

(72)Inventors:
  • Eken, Yalcin Alper
    Istanbul (TR)
  • Tokmak, Savas
    Istanbul (TR)
  • Celik, Abdullah
    Istanbul (TR)

(74)Representative: Wardle, Callum Tarn et al
Withers & Rogers LLP 4 More London Riverside
London SE1 2AU
London SE1 2AU (GB)


(56)References cited: : 
EP-A1- 1 595 331
US-A- 5 815 039
JP-A- H11 250 168
US-A1- 2010 097 143
  
  • "800 MHz to 3800 MHz Crest Factor Detector Preliminary Technical Data", , 20 April 2008 (2008-04-20), XP055273596, Retrieved from the Internet: URL:http://www.digchip.com/datasheets/down load_datasheet.php?id=1386144&part-number= ADL5502 [retrieved on 2016-05-19]
  • "General Description Features Functional Diagram Typical Applications", , 10 July 2008 (2008-07-10), XP055273640, Retrieved from the Internet: URL:http://shpat.com/docs/hittite/hmc614lp 4.pdf [retrieved on 2016-05-19]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Cross Reference to Related Application



[0001] This application claims priority from U.S. Provisional Patent Application Serial No. 61/383,820, filed on September 17, 2010, entitled RMS AND ENVELOPE DETECTOR, which is hereby incorporated by reference.

Background



[0002] The present application relates generally to root mean square (RMS) detectors and envelope detectors.

[0003] There are many applications in which it is desirable to measure the average power level of a radio frequency (RF) signal. For example, power measurement and control of RF signals in both the transmitting and receiving chains of modern wireless communications systems, such as cellular telephone networks, may be essential. To efficiently use the available bandwidth, the transmitted signals in these systems are modulated using complex modulation schemes such as Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), or Worldwide Interoperability for Microwave Access (WiMAX). These complex modulated signals have a time varying crest factor, which is defined as the peak to average power ratio of the signal. Intolerable errors can result if conventional power detectors using diode detection or successive amplification are used to measure the signal power.

[0004] Another challenge in modern wireless communication systems is improving the power efficiency of power amplifiers used in the transmit chain. Efficient use of power amplifiers is important in mobile communications systems. Improved power efficiency can provide significant benefits including lower overall operating costs. Improving the power efficiency of power amplifiers is especially difficult when high-crest factor signals (having a peak power of 10+dB more than the average power) are transmitted since the transmitter should be put in a deep back-off mode (very low average power output) to handle the linearity requirements for peak signal levels. To improve power efficiency, it is known to apply envelope tracking to the power amplifier input signal, and to use the detected envelope to vary the amplifier operation. For supplying power to the power amplifier, a variable power supply is utilized in an envelope tracking system. The input signal envelope power levels are monitored using an envelope detector, and the power that is supplied to the power amplifier is varied based on the monitored envelope levels. In particular, the supply voltage supplied to the power amplifier is varied so as to be just sufficient to reproduce the power level required by the amplifier at a given instant of time. Accordingly, at low envelope power levels, a low supply voltage is provided to the amplifier, and the full supply voltage is only provided when the maximum output envelope power is required, i.e., at the output power peaks.

[0005] RMS power detectors can precisely measure RF power independent of the modulation type (signal shape or crest-factor). Accurate RMS calculation of these complex modulation schemes requires long integration times to include the time-varying envelope in the measurement. Thus, commercially available RMS power detectors are generally not capable of providing the envelope level of the modulated signals.

[0006] Therefore, for transmitter systems, it is desirable to have a power detector that provides both average power information and input voltage envelope information.

[0007] US 2010/0097143 A1 describes an RF detector configured to provide two outputs, one being a function of the true RMS power level of an RF input signal, and the other being a function of the instantaneous/peak power of the RF input signal, normalized to the average power level. The RF detector includes a variable gain detection subsystem including a single detector or detector array that provides a representation of the power level of the RF input signal. The detector or detector array is common to both the RMS power detection channel and the instantaneous/peak power detection channel of the RF detector. A method of RF detection includes providing representations of the RF input signal at different gain levels, selecting one or more of the representations, and averaging the selected signals. The gain levels of the selected representations is adjusted to provide information about the average power level of the RF input signal.

[0008] "Analog Devices: Preliminary Technical Data ADL5502: 800 MHz to 3800 MHz Crest Factor Detector" describes a mean-responding power detector in combination with an envelope detector to accurately determine the crest factor of a modulated signal.

Brief Summary of the Disclosure



[0009] A power detector in accordance with a first embodiment of the disclosure is defined in claim 1 and a power detector in accordance with a second embodiment of the disclosure is defined in claim 2. A method of detecting power of an RF signal in accordance with the first embodiment of the disclosure is defined in claim 8 and a method of detecting power of an RF signal in accordance with the second embodiment of the disclosure is defined in claim 9.

[0010] The power detector may include a gain or attenuation element. The logarithmic RMS detector receives an RF input signal and detects the average power level of the RF input signal. The gain or attenuation element also receives the RF input signal and generates an amplified or attenuated version of the RF input signal. The linear envelope detector receives the amplified or attenuated version of the RF input signal and detects the voltage envelope of the RF input signal, wherein the gain or attenuation element can generate a selected amplified or attenuated version of the RF input signal to shift the operating range of the envelope detector to higher or lower power levels.

[0011] The method of detecting power of an RF input signal may further comprise generating an amplified or attenuated version of the RF input signal; and detecting the voltage envelope of the RF input signal using the amplified or attenuated version of the RF input signal, wherein the amplified or attenuated version of the RF input signal is selectively generated to shift the operating range of the envelope detector to higher or lower power levels.

[0012] The logarithmic RMS detector may include a series of gain or attenuation stages that progressively amplify or attenuate the RF input signal. The logarithmic RMS detector may also include a plurality of mean square detectors, at least some of which are driven with amplified or attenuated versions of the RF input signal from the series of gain or attenuation stages. The envelope detector may be selectively coupled to an RF input for receiving the RF input signal or to one of a plurality of gain or attenuation taps of the series of gain or attenuation stages of the RMS detector for receiving an amplified or attenuated version of the RF input signal to shift the operating range of the envelope detector.

[0013] The method of detecting power may comprise the steps of progressively amplifying or attenuating an RF input signal to generate a plurality of amplified or attenuated versions of the RF input signal; detecting the average power level of the RF input signal using a logarithmic RMS detector including a plurality of mean square detectors, at least some of which are driven with the plurality of amplified or attenuated versions of the RF input signal; and detecting the voltage envelope of the RF input signal using a linear envelope detector receiving the RF input signal or one of the plurality of amplified or attenuated versions of the RF input signal selected to shift the operating range of the envelope detector.

[0014] The linear envelope detector for detecting the voltage envelope of an RF input signal may comprise a plurality of bipolar triple-tail cells. Each triple-tail cell includes two differential transistors and a center transistor. In each triple-tail cell, each of the transistors has a common emitter node coupled to a current source generating a tail-current. The collectors of the differential transistors of each triple-tail cell are coupled together to form an output of the envelope detector. In each triple-tail cell, a differential input voltage is applied between the bases of the differential transistors with a DC voltage component, and an input voltage with only a DC voltage component is applied to the base of the center transistor.

[0015] The linear envelope detector for detecting the voltage envelope of an RF input signal may comprise a plurality of bipolar triple-tail cells. Each triple-tail cell includes two differential transistors and a center transistor. In each triple-tail cell, each of the transistors has a common emitter node coupled to a current source generating a tail-current. The collectors of the differential transistors of each triple-tail cell are coupled together to form an output of the envelope detector. In each triple-tail cell, a first signal is applied between the bases of a first one of the two differential transistors and the center transistor and a second signal is applied between the bases of a second one of the differential transistors and the center transistor, wherein the first and the second signals form a differential signal.

[0016] The linear envelope detector for detecting the voltage envelope of an RF input signal may comprise a plurality of bipolar triple-tail cells. Each triple-tail cell includes two differential transistors and a center transistor. In each triple-tail cell, each of the transistors has a common emitter node coupled to a current source generating a tail-current. The collectors of the differential transistors of each triple-tail cell are coupled together to form an output of the envelope detector. In each triple-tail cell, a differential input voltage is applied between the bases of the differential transistors with a DC voltage component, and an input voltage with a parasitic RF component is applied to the base of the center transistor.

[0017] Various embodiments of the invention are provided in the following detailed description. As will be realized, the invention is capable of other and different embodiments, and its several details may be capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not in a restrictive or limiting sense, with the scope of the application being indicated in the claims.

Brief Description of the Drawings



[0018] 

FIG. 1 is a schematic diagram of a prior art RMS and envelope detector.

FIG. 2 is a schematic diagram of another prior art RMS and envelope detector.

FIG. 3 is a schematic diagram of another prior art RMS and envelope detector.

FIG. 4 is a schematic diagram of an RMS and envelope detector in accordance with one or more embodiments.

FIG. 5 is a schematic diagram of an RMS and envelope detector in accordance with one or more further embodiments.

FIG. 6 is a schematic diagram of an RMS and envelope detector in accordance with one or more further embodiments.

FIG. 7 is a schematic diagram of an envelope detector core structure in accordance with one or more embodiments.

FIG. 8 is a graph illustrating exemplary output-input characteristics of triple-tail cells.



[0019] Like or identical reference numbers are used to identify common or similar elements.

Detailed Description



[0020] FIG. 1 is a schematic block diagram illustrating a prior art RMS and envelope detector 100, which uses two separate chips 102, 104 to detect the average power and the envelope of the signal of interest in parallel. This parallel processing RF detector technique disadvantageously requires an RF coupler at the input to drive both the average power detection channel and the envelope detection channel. In addition, such a multi-chip implementation can suffer from part-to-part variations, which can occur in integrated circuits and cause intolerable measurement mismatches between the RMS detector 102 and the envelope detector 104. Discrete implementation of RMS and envelope detection also generally requires a larger board area to accommodate both chips and required interface circuitry such as an input coupler.

[0021] FIG. 2 is a block diagram of a prior art single package power detector 200 providing both the envelope and RMS power information. The RF input is provided to separate RMS detector and envelope detector blocks 202, 204 through a DC decoupling capacitor 206. The RMS detector 202 is of linear type (Vout ∼ Sqrt(Mean(Vin2))), meaning that the output voltage changes exponentially for dB changes in the input power. For these type of detectors, especially at lower power levels (e.g., less than -10dBm), the detected voltage level is very sensitive to mismatches and environmental variations such as temperature, and this limits the minimum detectable signal levels to about -15dBm. The envelope detector 204 also has similar limitations, resulting in a detectable input power range of about -15dBm to 10dBm for both detectors. Although the simplicity of this approach may result in a smaller package size and lower power dissipation, the prior art detector 200 is only useful for a limited level of input signals. Also, a linear RMS detector output is usually not preferable in power control applications because of larger reading errors for low input power levels.

[0022] FIG. 3 illustrates another prior art power detector 300 providing both envelope and RMS power information. The detector 300 uses a servo feedback type RMS detection architecture for high dynamic range operation. The detector can detect signal levels down to -70dBm, giving it a significantly higher dynamic range than linear type RMS detectors.

[0023] The envelope detection channel receives its input from an internal point of the servo feedback loop and this buffered internal point provides the power envelope of the input signal that is normalized to the average power level of the input signal. This architecture provides a high dynamic range for both RMS and envelope detection (the envelope detection dynamic range is equivalent to the RMS detection range -- more than 70dB possible) with exceptional repeatability (over temperature and process variations) as well as exceptional matching between the RMS power reading and power envelope reading. Most envelope tracking applications, however, require the envelope detector to track the voltage envelope of the input signal instead of the power envelope, and this type of architecture may accordingly not be suitable because it tracks the power envelope.

[0024] FIG. 4 is a block diagram illustrating a single package power detector 400 providing both envelope and RMS power information in accordance with one or more embodiments of the invention. An RF input is coupled to separate RMS detector and envelope detector blocks 402, 404, which process the input signal separately. The RMS detector 402 and the envelope detector 404 are provided in a single package 406 and preferably on a single die.

[0025] The RMS detector 402 is a logarithmic type (Vout ∼ Log(Mean(Vin2))) RMS detector, in which the output voltage changes linearly for dB changes in the input power. Logarithmic RMS detectors provide significantly larger input dynamic ranges compared to linear RMS detector types. They are especially useful for power/gain control applications because they have linear-in-dB characteristics and provide higher accuracy at low power levels (e.g., detection down to -70dBm is possible).

[0026] With direct coupling of the RF input signal to the envelope detector, the envelope detection dynamic range is lower (limited to about -15dBm at low power end and +10dBm at the top end).

[0027] FIG. 5 is a block diagram of an RMS and envelope detector 500 in accordance with one or more further embodiments. The detector 500 is similar to the detector 400 shown in FIG. 4, and further includes a gain/attenuation block 502. In the FIG. 5 embodiment, the RF input is coupled to the gain/attenuation block 502 to provide amplification/attenuation to the input signal. The output of the gain/attenuation block is coupled to the envelope detector 404. The operating range of the envelope detector 404 (the range of input signals to which the envelope detector accurately responds) can be shifted to lower or higher power levels. For example, for a gain of 20dB in the gain/attenuation block 502, the envelope detector 404 can detect RF signals from about -35dBm to -10dBm.

[0028] FIG. 6 is a block diagram of an RMS and envelope detector 600 in accordance with one or more further embodiments of the invention. In this embodiment, an envelope detector core 602 is coupled to one of a plurality of gain/attenuation taps 604 of an RMS detector 606.

[0029] In this embodiment, the RMS detector 606 includes a plurality of mean square detectors, some of which are driven with amplified or attenuated versions of an RF input signal to obtain a wider range of mean square power detection than a single mean square detector. The amplified or attenuated versions of the RF input signal are obtained by using a series of gain or attenuation operations that progressively amplify or attenuate the RF input signal using amplifiers 608 or attenuators 610.

[0030] The operating range of the envelope detector 602 (the range of input signals that the envelope detector accurately responds to) can be shifted to lower or higher power levels similar to the FIG. 5 embodiment. However, in the FIG. 6 embodiment, there is no need for additional amplification/attenuation because the amplified/attenuated taps of RMS detector 606 can be used to supply the needed gain/attenuation. For gain/attenuation separation of 7dB, the envelope detector operation range can be shifted in 7dB steps. For example, if the envelope detector 602 is coupled to the 3rd gain tap of the architecture (21dB gain from input), the envelope detector 602 can detect RF signals from -36dBm to -11dBm assuming that the envelope detector has 25dB detection range.

[0031] FIG. 7 schematically illustrates an envelope detector core structure 700 that is used for envelope detection in the various RMS and envelope detectors in accordance with one or more embodiments. The detector comprises a plurality of bipolar triple-tail cells (indicated in the FIG. 7 example as the 1st stage and 2nd stage). Each triple-tail cell includes three emitter-coupled npn bipolar transistors (Q1, Q2, Q3 in the first stage, Q4, Q5, Q6 in the second stage) and a current source coupled to the common-emitter generating a tail-current Idc1, Idc2. The transistors Q1 and Q3 of the first stage form a differential pair with emitter areas equal to each other (Ae). The transistors Q4 and Q6 of the second stage form a differential pair with emitter areas equal to each other (Ce). The transistors Q2 and Q5 may have different emitter areas (Be and De, respectively) than their respective differential pairs. The ratios B/A or D/C may be unity, or may be greater or less than unity. The collectors of the transistors Q1 and Q3 of the first stage are coupled together forming the output terminal of an envelope detector core stage, while the collector of Q2 is coupled to an AC ground. Similarly, the collectors of the transistors Q4 and Q6 of the second stage are coupled together forming the output terminal of an envelope detector core stage, while the collector of Q5 is coupled to an AC ground.

[0032] In this configuration, a differential input voltage Vinp=INP-INN is applied between the bases of the transistors Q1, Q3 and Q4, Q6 with a dc voltage component denoted as "DC". The bases of the center transistors Q2 and Q5 receive only the dc component "DC". In an alternative embodiment, the center transistors may receive a parasitic RF component. In a further embodiment, one of the transistors in the differential pair Q1, Q3 or Q4, Q6 can receive a DC voltage at its base and the other two transistors (one of Q1, Q3 and also Q2, or one of Q4, Q6 and also Q5) can receive input signals that effectively generate a differential voltage across base inputs of Q1-Q2=Q4-Q5 (= Vinp/2) and Q3-Q2=Q6-Q5 (= -Vinp/2).

[0033] In the embodiment illustrated in FIG. 7, two types of triple-tail cells are used in the envelope detector core (1st stage=type-1, 2nd stage=type-2). The type-2 stage uses two emitter degeneration resistors R2 that are coupled between the emitter of the differential pair transistors Q4, Q6 and the common emitter node (which is coupled to the current source). The degeneration resistors linearize the output-input transfer curve of the stage for mid and high level input signals when used with a proper D/C ratio (preferably D/C >> 1 in the current embodiment). The type-1 stage, on the other hand, uses a single emitter degeneration resistor R1 that is coupled between the emitter of the center transistor Q2 and the common emitter node. The degeneration resistor linearizes the output-input transfer curve of the combined structure (including both type-1 and type-2 stages) for lower input signal levels with a proper B/A ratio (preferably B/A < 1 in the current embodiment). In summary, emitter degeneration resistors R1 and R2 expand the linear operating input voltage range of the envelope detector core. FIG. 8 shows an example of the output-input characteristics of the type-1 and type-2 stages as well as the combined structure. As shown, the type-2 stage provides approximately linear characteristics for input signal levels of Vinp > 150mV, while the combined structure provides approximately linear characteristics for input signal levels of Vinp > 50mV, resulting in a significant improvement in the dynamic range.

[0034] It should be noted that additional Type-2 stages can be provided in parallel with different degeneration values and D/C ratios to further increase the dynamic range for higher signal levels.


Claims

1. A power detector (400, 500, 600), comprising:

a logarithmic RMS detector (402, 606) configured to:

receive an RF input signal (RFin); and

detect the average power level of the RF input signal; and

a linear envelope detector (404, 602), configured to:
detect the voltage envelope of the RF input signal;

wherein the linear envelope detector comprises:
a plurality of bipolar triple-tail cells, each triple-tail cell including two differential transistors (Q1 and Q3, Q4 and Q6) and a center transistor (Q2, Q5), and

wherein in each triple-tail cell, each of the transistors has a common emitter node coupled to a current source configured to generate a tail-current (Idc1, Idc2), each triple-tail cell being configured to receive a differential input voltage between the bases of the differential transistors with a DC voltage component, and either a) an input voltage with a DC voltage component, or b) a parasitic RF component, on the base of the center transistor,

wherein the collectors of the differential transistors of the triple-tail cells are all coupled together to an output terminal of the linear envelope detector; and

wherein the logarithmic RMS detector and the envelope detector are integrated in a single package.


 
2. A power detector (400, 500, 600), comprising:

a logarithmic RMS detector (402, 606) configured to:

receive an RF input signal (RFin); and

detect the average power level of the RF input signal; and

a linear envelope detector (404, 602), configured to:
detect the voltage envelope of the RF input signal;

wherein the linear envelope detector comprises:
a plurality of bipolar triple-tail cells, each triple-tail cell including two differential transistors (Q1 and Q3, Q4 and Q6) and a center transistor (Q2, Q5), and

wherein in each triple-tail cell, each of the transistors has a common emitter node coupled to a current source configured to generate a tail-current (Idc1, Idc2), each triple-tail cell being configured to receive a first signal between the bases of a first one of the two differential transistors and the center transistor and a second signal between the bases of a second one of the differential transistors and the center transistor, wherein the first and the second signals form a differential signal;

wherein the collectors of the differential transistors of the triple-tail cells are all coupled together to an output terminal of the linear envelope detector; and

wherein the logarithmic RMS detector and the envelope detector are integrated in a single package.


 
3. The power detector of claim 1 or claim 2, wherein the RMS detector and the envelope detector are integrated on a single die.
 
4. The power detector of any of claims 1 to 3, further comprising a gain or attenuation element (502) configured to:

receive the RF input signal; and

generate an amplified or attenuated version of the RF input signal; and

wherein the linear envelope detector is configured to receive the amplified or attenuated version of the RF input signal and detect the voltage envelope of the RF input signal, wherein the gain or attenuation element is configured to generate a selected amplified or attenuated version of the RF input signal to shift the operating range of the envelope detector to higher or lower power levels.
 
5. The power detector of any of claims 1 to 3, wherein the logarithmic RMS detector includes a series of gain or attenuation stages (608, 610) configured to progressively amplify or attenuate the RF input signal, and the logarithmic RMS detector also includes a plurality of mean square detectors, at least some of which are driven with amplified or attenuated versions of the RF input signal from the series of gain or attenuation stages; and
wherein the linear envelope detector is selectively coupled to an RF input for receiving the RF input signal or to one of a plurality of gain or attenuation taps (604) of the series of gain or attenuation stages of the RMS detector for receiving an amplified or attenuated version of the RF input signal to shift the operating range of the envelope detector.
 
6. The power detector of any preceding claim, wherein at least one of the triple-tail cells further comprise an emitter degeneration resistor (R2) coupled between the emitter of each of the two differential transistors and the common emitter node.
 
7. The power detector of claim 6, wherein at least one of the triple-tail cells different from triple-tail cells with an emitter degeneration resistor on the differential transistors further comprises an emitter degeneration resistor (R1) coupled between the emitter of the center transistor and the common emitter node.
 
8. A method of detecting power of an RF input signal (RFin), comprising the steps of:

detecting the average power level of the RF input signal using a logarithmic RMS detector (402, 606);

detecting the voltage envelope of the RF input signal using a linear envelope detector (404, 602);

wherein the linear envelope detector comprises a plurality of bipolar triple-tail cells, each triple-tail cell including two differential transistors (Q1 and Q3, Q4 and Q6) and a center transistor (Q2, Q5), and

wherein in each triple-tail cell, each of the transistors has a common emitter node coupled to a current source generating a tail-current (Idc1, Idc2), a differential input voltage is applied between the bases of the differential transistors with a DC voltage component, and either a) an input voltage with a DC voltage component, or b) a parasitic RF component, is applied to the base of the center transistor, and

wherein the collectors of the differential transistors of the triple-tail cells are all coupled together to an output terminal of the linear envelope detector, and

wherein the logarithmic RMS detector and the envelope detector are integrated in a single package.


 
9. A method of detecting power of an RF input signal (RFin), comprising the steps of:

detecting the average power level of the RF input signal using a logarithmic RMS detector (402, 606);

detecting the voltage envelope of the RF input signal using a linear envelope detector (404, 602);

wherein the linear envelope detector comprises a plurality of bipolar triple-tail cells, each triple-tail cell including two differential transistors (Q1 and Q3, Q4 and Q6) and a center transistor (Q2, Q5), and

wherein in each triple-tail cell, each of the transistors has a common emitter node coupled to a current source generating a tail-current (Idc1, Idc2), a first signal is applied between the bases of a first one of the two differential transistors and the center transistor and a second signal is applied between the bases of a second one of the differential transistors and the center transistor, wherein the first and the second signals form a differential signal, and

wherein the collectors of the differential transistors of the triple-tail cells are all coupled together to an output terminal of the linear envelope detector, and

wherein the logarithmic RMS detector and the envelope detector are integrated in a single package.


 
10. The method of claim 8 or claim 9 wherein the RMS detector and the envelope detector are integrated on a single die.
 
11. A method of any of claims 8 to 10, further comprising generating an amplified or attenuated version of the RF input signal; and
wherein detecting the voltage envelope of the RF input signal comprises using the amplified or attenuated version of the RF input signal, wherein the amplified or attenuated version of the RF input signal is selectively generated to shift the operating range of the envelope detector to higher or lower power levels.
 
12. The method of claim 11, wherein a gain or attenuation element (502) is used for generating the amplified or attenuated version of the RF input signal, and wherein a linear envelope detector is used for detecting the voltage envelope of the RF input signal.
 
13. A method of any of claims 8 to 10, further comprising progressively amplifying or attenuating an RF input signal to generate a plurality of amplified or attenuated versions of the RF input signal;
wherein detecting the average power level of the RF input signal comprises using a logarithmic RMS detector including a plurality of mean square detectors, at least some of which are driven with the plurality of amplified or attenuated versions of the RF input signal; and
wherein detecting the voltage envelope of the RF input signal using a linear envelope detector comprises receiving the RF input signal or one of the plurality of amplified or attenuated versions of the RF input signal selected to shift the operating range of the envelope detector.
 


Ansprüche

1. Leistungsdetektor (400, 500, 600), der Folgendes umfasst:

einen logarithmischen RMS-Detektor (402, 606), der konfiguriert ist, die folgenden Schritte auszuführen:

Empfangen eines HF-Eingangssignals (HFin); und

Detektieren des gemittelten Leistungspegels des HF-Eingangssignals; und

einen linearen Hüllkurvendetektor (402, 602), der konfiguriert ist, die folgenden Schritte auszuführen:
Detektieren der Spannungshüllkurve des HF-Eingangssignals;

wobei der lineare Hüllkurvendetektor Folgendes umfasst:
mehrere bipolare dreigeteilte Zellen, wobei jede dreigeteilte Zelle zwei Differentialtransistoren (Q1 und Q3, Q4 und Q6) und einen zentralen Transistor (Q2, Q5) umfasst, und

wobei in jeder dreigeteilten Zelle jeder der Transistoren einen gemeinsamen Emitterknoten aufweist, der mit einer Stromquelle gekoppelt ist, die konfiguriert ist, einen geteilten Strom (Idc1, Idc2) zu erzeugen, wobei jede dreigeteilte Zelle konfiguriert ist, eine Differentialeingangsspannung zwischen den Basen der Differentialtransistoren mit einer Gleichspannungskomponente und entweder a) eine Eingangsspannung mit einer Gleichspannungskomponente oder b) eine parasitäre HF-Komponente an der Basis des zentralen Transistors zu empfangen,

wobei die Kollektoren der Differentialtransistoren der dreigeteilten Zellen alle miteinander mit einem Ausgangsanschluss des linearen Hüllkurvendetektors gekoppelt sind; und

wobei der logarithmische RMS-Detektor und der Hüllkurven-Detektor in einer einzigen Einheit integriert sind.


 
2. Leistungsdetektor (400, 500, 600), der Folgendes umfasst:

einen logarithmischen RMS-Detektor (402, 606), der konfiguriert ist, die folgenden Schritte auszuführen:

Empfangen eines HF-Eingangssignals (HFin); und

Detektieren des gemittelten Leistungspegels des HF-Eingangssignals; und

einen linearen Hüllkurvendetektor (404, 602), der konfiguriert ist, die folgenden Schritte auszuführen:
Detektieren der Spannungshüllkurve des HF-Eingangssignals;

wobei der lineare Hüllkurvendetektor Folgendes umfasst:
mehrere bipolare dreigeteilte Zellen, wobei jede dreigeteilte Zelle zwei Differentialtransistoren (Q1 und Q3, Q4 und Q6) und einen zentralen Transistor (Q2, Q5) umfasst, und

wobei in jeder dreigeteilten Zelle jeder der Transistoren einen gemeinsamen Emitterknoten aufweist, der mit einer Stromquelle gekoppelt ist, die konfiguriert ist, einen geteilten Strom (Idc1, Idc2) zu erzeugen, wobei jede dreigeteilte Zelle konfiguriert ist, ein erstes Signal zwischen den Basen eines ersten der zwei Differentialtransistoren und des zentralen Transistors und ein zweites Signal zwischen den Basen eines zweiten der zwei Differentialtransistoren und des zentralen Transistors zu empfangen, wobei das erste und das zweite Signal ein Differentialsignal bilden;

wobei die Kollektoren der Differentialtransistoren der dreigeteilten Zellen alle miteinander mit einem Ausgangsanschluss des linearen Hüllkurvendetektors gekoppelt sind; und

wobei der logarithmische RMS-Detektor und der Hüllkurven-Detektor in einer einzigen Einheit integriert sind.


 
3. Leistungsdetektor nach Anspruch 1 oder Anspruch 2, wobei der RMS-Detektor und der Hüllkurven-Detektor auf einem einzigen Chip integriert sind.
 
4. Leistungsdetektor nach einem der Ansprüche 1 bis 3, der ferner ein Verstärkungs- oder Dämpfungselement (502) umfasst, das konfiguriert ist, die folgenden Schritte auszuführen:

Empfangen des HF-Eingangssignals; und

Erzeugen einer verstärkten oder gedämpften Version des HF-Eingangssignals; und

wobei der lineare Hüllkurvendetektor konfiguriert ist, die verstärkte oder gedämpfte Version des HF-Eingangssignals zu empfangen und die Spannungshüllkurve des HF-Eingangssignals zu detektieren, wobei das Verstärkungs- oder Dämpfungselement konfiguriert ist, eine ausgewählte verstärkte oder gedämpfte Version des HF-Eingangssignals zu erzeugen, um den Arbeitsbereich des Hüllkurvendetektors zu höheren oder niedrigeren Leistungspegeln zu verschieben.
 
5. Leistungsdetektor nach einem der Ansprüche 1 bis 3, wobei der logarithmische RMS-Detektor eine Reihe von Dämpfungs- oder Verstärkungsstufen (608, 610) umfasst, die konfiguriert sind, das HF-Eingangssignal schrittweise zu verstärken oder zu dämpfen, und wobei der logarithmische RMS-Detektor außerdem mehrere Detektoren für ein mittleres Fehlerquadrat umfasst, wovon wenigstens einige mit verstärkten oder gedämpften Versionen des HF-Eingangssignals aus der Reihe von Verstärkungs- oder Dämpfungsstufen angesteuert werden; und
wobei der lineare Hüllkurvendetektor wahlweise mit einem HF-Eingang zum Empfangen des HF-Eingangssignals oder mit einem von mehreren Verstärkungs- oder Dämpfungs-Abgriffen (604) der Reihe von Verstärkungs- oder Dämpfungsstufen des RMS-Detektors gekoppelt ist, um eine verstärkte oder gedämpfte Version des HF-Eingangssignals zu empfangen, um so den Arbeitsbereich des Hüllkurvendetektors zu verschieben.
 
6. Leistungsdetektor nach einem der vorhergehenden Ansprüche, wobei wenigstens eine der dreigeteilten Zellen ferner einen Emitter-Gegenkopplungswiderstand (R2) umfasst, der zwischen dem Emitter jedes der zwei Differentialtransistoren und dem gemeinsamen Emitterknoten angeschlossen ist.
 
7. Leistungsdetektor nach Anspruch 6, wobei wenigstens eine der dreigeteilten Zellen, die sich von dreigeteilten Zellen mit einem Emitter-Gegenkopplungswiderstand an dem Differentialtransistor unterscheidet, ferner einen Emitter-Gegenkopplungswiderstand (R1) umfasst, der zwischen dem Emitter des zentralen Transistors und dem gemeinsamen Emitterknoten angeschlossen ist.
 
8. Verfahren zum Detektieren einer Leistung eines HF-Eingangssignals (HFin), wobei das Verfahren die folgenden Schritte umfasst:

Detektieren eines gemittelten Leistungspegels des HF-Eingangssignals unter Verwendung eines logarithmischen RMS-Detektors (402, 606);

Detektieren der Spannungshüllkurve des HF-Eingangssignals unter Verwendung eines linearen Hüllkurvendetektors (404; 602);

wobei der lineare Hüllkurvendetektor mehrere bipolare dreigeteilte Zellen umfasst, wobei jede dreigeteilte Zelle zwei Differentialtransistoren (Q1 und Q3, Q4 und Q6) und einen zentralen Transistor (Q2, Q5) umfasst, und

wobei in jeder dreigeteilten Zelle jeder der Transistoren einen gemeinsamen Emitterknoten aufweist, der mit einer Stromquelle gekoppelt ist, die einen geteilten Strom (Idc1, Idc2) erzeugt, wobei eine Differentialeingangsspannung zwischen den Basen der Differentialtransistoren mit einer Gleichspannungskomponente angelegt wird und entweder a) eine Eingangsspannung mit einer Gleichspannungskomponente oder b) eine parasitäre HF-Komponente an die Basis des zentralen Transistors angelegt wird, und

wobei die Kollektoren der Differentialtransistoren der dreigeteilten Zellen alle miteinander mit einem Ausgangsanschluss des linearen Hüllkurvendetektors gekoppelt sind; und

wobei der logarithmischen RMS-Detektor und der Hüllkurven-Detektor in einer einzigen Einheit integriert sind.


 
9. Verfahren zum Detektieren der Leistung eines HF-Eingangssignals (HFin), wobei das Verfahren die folgenden Schritte umfasst:

Detektieren des gemittelten Leistungspegels des HF-Eingangssignals unter Verwendung eines logarithmischen RMS-Detektors (402, 606);

Detektieren der Spannungshüllkurve des HF-Eingangssignals unter Verwendung eines linearen Hüllkurvendetektors (404; 602);

wobei der lineare Hüllkurvendetektor mehrere bipolare dreigeteilte Zellen umfasst, wobei jede dreigeteilte Zelle zwei Differentialtransistoren (Q1 und Q3, Q4 und Q6) und einen zentralen Transistor (Q2, Q5) umfasst, und

wobei in jeder dreigeteilten Zelle jeder der Transistoren einen gemeinsamen Emitterknoten aufweist, der mit einer Stromquelle gekoppelt ist, die einen geteilten Strom (Idc1, Idc2) erzeugt, wobei ein erstes Signal zwischen den Basen eines ersten der zwei Differentialtransistoren und des zentralen Transistors angelegt wird und ein zweites Signal zwischen den Basen eines zweiten der Differentialtransistoren und des zentralen Transistors angelegt wird, wobei das erste und das zweite Signal ein Differentialsignal bilden, und

wobei die Kollektoren der Differentialtransistoren der dreigeteilten Zellen alle miteinander mit einem Ausgangsanschluss des linearen Hüllkurvendetektors gekoppelt sind; und

wobei der logarithmische RMS-Detektor und der Hüllkurven-Detektor in einer einzigen Einheit integriert sind.


 
10. Verfahren nach Anspruch 8 oder Anspruch 9, wobei der RMS-Detektor und der Hüllkurven-Detektor auf einem einzigen Chip integriert sind.
 
11. Verfahren nach einem der Ansprüche 8 bis 10, das ferner das Erzeugen einer verstärkten oder gedämpften Version des HF-Eingangssignals umfasst; und
wobei das Detektieren der Spannungshüllkurve des HF-Eingangssignals das Verwenden der verstärkten oder gedämpften Version des HF-Eingangssignals umfasst, wobei die verstärkte oder gedämpfte Version des HF-Eingangssignals wahlweise erzeugt wird, um den Arbeitsbereich des Hüllkurvendetektors zu höheren oder niedrigeren Leistungspegeln zu verschieben.
 
12. Verfahren nach Anspruch 11, wobei ein Verstärkungs- oder Dämpfungselement (502) verwendet wird, um die verstärkte oder gedämpfte Version des HF-Eingangssignals zu erzeugen, und wobei ein linearer Hüllkurvendetektor zum Detektieren der Spannungshüllkurve des HF-Eingangssignals verwendet wird.
 
13. Verfahren nach einem der Ansprüche 8 bis 10, das ferner das schrittweise Verstärken oder Dämpfen eines HF-Eingangssignals umfasst, um mehrere verstärkte oder gedämpfte Versionen des HF-Eingangssignals zu erzeugen;
wobei das Detektieren des gemittelten Leistungspegels des HF-Eingangssignals das Verwenden eines logarithmischen RMS-Detektors umfasst, der mehrere Detektoren für ein mittleres Fehlerquadrat umfasst, wovon wenigstens einige mit den mehreren verstärkten oder gedämpften Versionen des HF-Eingangssignals angesteuert werden; und
wobei das Detektieren der Spannungshüllkurve des HF-Eingangssignals unter Verwendung des linearen Hüllkurvendetektors das Empfangen des HF-Eingangssignals oder eines der mehreren verstärkten oder gedämpften Versionen des HF-Eingangssignals umfasst, das ausgewählt wird, um den Arbeitsbereich des Hüllkurvendetektors zu verschieben.
 


Revendications

1. Détecteur de puissance (400, 500, 600), comprenant :

- un détecteur RMS logarithmique (402, 606) configuré pour :

• recevoir un signal d'entrée RF (RFin) ; et

• détecter le niveau de puissance moyen du signal d'entrée RF ; et

- un détecteur d'enveloppe linéaire (404, 602), configuré pour :

• détecter l'enveloppe de tension du signal d'entrée RF ;

dans lequel le détecteur d'enveloppe linéaire comprend :

une pluralité de cellules bipolaires à triple queue, chaque cellule à triple queue comportant deux transistors différentiels (Q1 et Q3, Q4 et Q6) et un transistor central (Q2, Q5), et

dans lequel dans chaque cellule à triple queue, chacun des transistors a un nœud à émetteur commun couplé à une source de courant configurée pour générer un courant de queue (ldc1, ldc2), chaque cellule à triple queue étant configurée pour recevoir une tension d'entrée différentielle entre les bases des transistors différentiels présentant une composante de tension CC, et soit a) une tension d'entrée présentant une composante de tension CC, soit b) une composante RF parasite, sur la base du transistor central,

dans lequel les collecteurs des transistors différentiels des cellules à triple queue sont tous couplés conjointement à une borne de sortie du détecteur d'enveloppe linéaire ; et

dans lequel le détecteur RMS logarithmique et le détecteur d'enveloppe sont intégrés dans un seul boîtier.


 
2. Détecteur de puissance (400, 500, 600), comprenant :

- un détecteur RMS logarithmique (402, 606) configuré pour :

• recevoir un signal d'entrée RF (RFin) ; et

• détecter le niveau de puissance moyen du signal d'entrée RF ; et

- un détecteur d'enveloppe linéaire (404, 602), configuré pour :

• détecter l'enveloppe de tension du signal d'entrée RF ;

dans lequel le détecteur d'enveloppe linéaire comprend :

une pluralité de cellules bipolaires à triple queue, chaque cellule à triple queue comportant deux transistors différentiels (Q1 et Q3, Q4 et Q6) et un transistor central (Q2, Q5), et

dans lequel dans chaque cellule à triple queue, chacun des transistors a un nœud à émetteur commun couplé à une source de courant configurée pour générer un courant de queue (ldc1, ldc2), chaque cellule à triple queue étant configurée pour recevoir un premier signal entre les bases d'un premier des deux transistors différentiels et le transistor central et un second signal entre les bases d'un second des transistors différentiels et le transistor central, dans lequel les premier et second signaux forment un signal différentiel ;

dans lequel les collecteurs des transistors différentiels des cellules à triple queue sont tous couplés conjointement à une borne de sortie du détecteur d'enveloppe linéaire ; et

dans lequel le détecteur RMS logarithmique et le détecteur d'enveloppe sont intégrés dans un seul boîtier.


 
3. Détecteur de puissance selon la revendication 1 ou la revendication 2, dans lequel le détecteur RMS et le détecteur d'enveloppe sont intégrés sur une seule puce.
 
4. Détecteur de puissance selon l'une quelconque des revendications 1 à 3, comprenant en outre un élément de gain ou d'atténuation (502) configuré pour :

- recevoir le signal d'entrée RF ; et

- générer une version amplifiée ou atténuée du signal d'entrée RF ; et

dans lequel le détecteur d'enveloppe linéaire est configuré pour recevoir la version amplifiée ou atténuée du signal d'entrée RF et détecter l'enveloppe de tension du signal d'entrée RF, dans lequel l'élément de gain ou d'atténuation est configuré pour générer une version amplifiée ou atténuée sélectionnée du signal d'entrée RF pour décaler la plage de fonctionnement du détecteur d'enveloppe vers des niveaux de puissance supérieurs ou inférieurs.
 
5. Détecteur de puissance selon l'une quelconque des revendications 1 à 3, dans lequel le détecteur RMS logarithmique comporte une série d'étages de gain ou d'atténuation (608, 610) configurés pour progressivement amplifier ou atténuer le signal d'entrée RF, et le détecteur RMS logarithmique comporte également une pluralité de détecteurs de moyenne quadratique, dont au moins certains sont entraînés avec des versions amplifiées ou atténuées du signal d'entrée RF à partir de la série d'étages de gain ou d'atténuation ; et
dans lequel le détecteur d'enveloppe linéaire est sélectivement couplé à une entrée RF pour recevoir le signal d'entrée RF ou à l'un parmi une pluralité de dérivateurs de gain ou d'atténuation (604) de la série d'étages de gain ou d'atténuation du détecteur RMS pour recevoir une version amplifiée ou atténuée du signal d'entrée RF pour décaler la plage de fonctionnement du détecteur d'enveloppe.
 
6. Détecteur de puissance selon l'une quelconque des revendications précédentes, dans lequel au moins l'une des cellules à triple queue comprend en outre une résistance de contre-réaction d'émetteur (R2) couplée entre l'émetteur de chacun des deux transistors différentiels et le nœud à émetteur commun.
 
7. Détecteur de puissance selon la revendication 6, dans lequel au moins l'une des cellules à triple queue différentes des cellules à triple queue présentant une résistance de contre-réaction d'émetteur sur les transistors différentiels comprend en outre une résistance de contre-réaction d'émetteur (R1) couplée entre l'émetteur du transistor central et le nœud à émetteur commun.
 
8. Procédé de détection de puissance d'un signal d'entrée RF (RFin), comprenant les étapes de :

- détection du niveau de puissance moyen du signal d'entrée RF en utilisant un détecteur RMS logarithmique (402, 606) ;

- détection de l'enveloppe de tension du signal d'entrée RF en utilisant un détecteur d'enveloppe linéaire (404, 602) ;

dans lequel le détecteur d'enveloppe linéaire comprend une pluralité de cellules bipolaires à triple queue, chaque cellule à triple queue comportant deux transistors différentiels (Q1 et Q3, Q4 et Q6) et un transistor central (Q2, Q5), et
dans lequel dans chaque cellule à triple queue, chacun des transistors a un nœud à émetteur commun couplé à une source de courant générant un courant de queue (ldcl, ldc2), une tension d'entrée différentielle est appliquée entre les bases des transistors différentiels présentant une composante de tension CC, et soit a) une tension d'entrée présentant une composante de tension CC, soit b) une composante RF parasite, est appliquée à la base du transistor central, et
dans lequel les collecteurs des transistors différentiels des cellules à triple queue sont tous couplés conjointement à une borne de sortie du détecteur d'enveloppe linéaire, et
dans lequel le détecteur RMS logarithmique et le détecteur d'enveloppe sont intégrés dans un seul boîtier.
 
9. Procédé de détection de puissance d'un signal d'entrée RF (RFin), comprenant les étapes de :

- détection du niveau de puissance moyen du signal d'entrée RF en utilisant un détecteur RMS logarithmique (402, 606) ;

- détection de l'enveloppe de tension du signal d'entrée RF en utilisant un détecteur d'enveloppe linéaire (404, 602) ;

dans lequel le détecteur d'enveloppe linéaire comprend une pluralité de cellules bipolaires à triple queue, chaque cellule à triple queue comportant deux transistors différentiels (Q1 et Q3, Q4 et Q6) et un transistor central (Q2, Q5), et
dans lequel dans chaque cellule à triple queue, chacun des transistors a un nœud à émetteur commun couplé à une source de courant générant un courant de queue (ldcl, ldc2), un premier signal est appliqué entre les bases d'un premier des deux transistors différentiels et le transistor central et un second signal est appliqué entre les bases d'un second des transistors différentiels et le transistor central, dans lequel les premier et second signaux forment un signal différentiel, et
dans lequel les collecteurs des transistors différentiels des cellules à triple queue sont tous couplés conjointement à une borne de sortie du détecteur d'enveloppe linéaire, et
dans lequel le détecteur RMS logarithmique et le détecteur d'enveloppe sont intégrés dans un seul boîtier.
 
10. Procédé selon la revendication 8 ou la revendication 9 dans lequel le détecteur RMS et le détecteur d'enveloppe sont intégrés sur une seule puce.
 
11. Procédé selon l'une quelconque des revendications 8 à 10, comprenant en outre la génération d'une version amplifiée ou atténuée du signal d'entrée RF ; et
dans lequel la détection de l'enveloppe de tension du signal d'entrée RF comprend l'utilisation de la version amplifiée ou atténuée du signal d'entrée RF, dans lequel la version amplifiée ou atténuée du signal d'entrée RF est sélectivement générée pour décaler la plage de fonctionnement du détecteur d'enveloppe vers des niveaux de puissance supérieurs ou inférieurs.
 
12. Procédé selon la revendication 11, dans lequel un élément de gain ou d'atténuation (502) est utilisé pour générer la version amplifiée ou atténuée du signal d'entrée RF, et dans lequel un détecteur d'enveloppe linéaire est utilisé pour détecter l'enveloppe de tension du signal d'entrée RF.
 
13. Procédé selon l'une quelconque des revendications 8 à 10, comprenant en outre l'amplification ou l'atténuation progressive d'un signal d'entrée RF pour générer une pluralité de versions amplifiées ou atténuées du signal d'entrée RF ;
dans lequel la détection du niveau de puissance moyen du signal d'entrée RF comprend l'utilisation d'un détecteur RMS logarithmique comportant une pluralité de détecteurs de moyenne quadratique, dont au moins certains sont entraînés avec la pluralité de versions amplifiées ou atténuées du signal d'entrée RF ; et
dans lequel la détection de l'enveloppe de tension du signal d'entrée RF en utilisant un détecteur d'enveloppe linéaire comprend la réception du signal d'entrée RF ou de l'une de la pluralité de versions amplifiées ou atténuées du signal d'entrée RF sélectionnée pour décaler la plage de fonctionnement du détecteur d'enveloppe.
 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description




Non-patent literature cited in the description