(19)
(11)EP 2 529 481 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
03.09.2014 Bulletin 2014/36

(21)Application number: 11702543.7

(22)Date of filing:  19.01.2011
(51)Int. Cl.: 
H03F 1/30  (2006.01)
H03F 3/45  (2006.01)
(86)International application number:
PCT/US2011/021704
(87)International publication number:
WO 2011/094101 (04.08.2011 Gazette  2011/31)

(54)

INSTRUMENTATION AMPLIFIER CALIBRATION METHOD, SYSTEM AND APPARATUS

KALIBRIERUNGSVERFAHREN, -SYSTEM UND -VORRICHTUNG FÜR EINEN INSTRUMENTIERUNGSVERSTÄRKER

PROCÉDÉ, SYSTÈME ET APPAREIL D'ÉTALONNAGE D'AMPLIFICATEUR D'INSTRUMENTATION


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 27.10.2010 US 913066
26.01.2010 US 298371 P

(43)Date of publication of application:
05.12.2012 Bulletin 2012/49

(73)Proprietor: Microchip Technology Incorporated
Chandler, AZ 85224-6199 (US)

(72)Inventors:
  • NOLAN, James, B.
    Chandler AZ 85248 (US)
  • BLAKE, Kumen
    Gilbert AZ 85233 (US)

(74)Representative: Grubert, Andreas et al
King & Spalding International LLP 125 Old Broad Street
London EC2N 1AR
London EC2N 1AR (GB)


(56)References cited: : 
US-A- 6 141 169
US-B1- 7 368 968
US-A1- 2008 224 768
US-B1- 7 541 857
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description

    TECHNICAL FIELD



    [0001] The present disclosure relates to integrated circuit instrumentation amplifiers, and more particularly, to calibration of integrated circuit instrumentation amplifiers.

    BACKGROUND



    [0002] Integrated circuits are becoming far more sophisticated while continuing to drop in price. Combinations of both analog and digital functions fabricated on an integrated circuit die, or packaged in a multi-chip package (MCP), are becoming more prevalent and are further increasing the usefulness and reducing the cost of consumer and industrial products. The combination of a microcontroller, and analog and digital circuit functions on an integrated circuit die or in an MCP has also expanded the useful range of applications. Consumer and commercial products, such as, for example, but not limited to, appliances, telecommunications devices, automobiles, security systems, full-house instant hot water heaters, thermostats and the like, are being controlled by integrated circuit microcontrollers. Analog inputs for receiving sensor information and analog outputs for controlling functions are necessary for the application of these microcontrollers. Heretofore separate and discrete analog-to-digital and digital-to-analog interfaces were used to connect the digital microcontroller to the outside analog world.

    [0003] Analog input devices such as an analog-to-digital converter (ADC) in conjunction with a separate operational amplifier (op-amp) were used to convert a time-varying analog signal into digital representations thereof for coupling to digital inputs and use thereof by the microcontroller. Voltage and current levels were also detected by discrete integrated circuit voltage comparators that changed a digital output state when a certain analog value was present on the input of the comparator.

    [0004] The operational amplifier (and comparator) is generally a differential input (inverting and non-inverting inputs) analog device, and the circuit of the op-amp has inherent direct current (DC) input offset voltage that causes the output of the op-amp to be nonzero with a zero input voltage between the differential inputs (e.g., inputs connected together). Many applications require an op-amp with a very small input offset voltage. To achieve a small input offset voltage, normally a calibration step in the production of the op-amp is required. This calibration step takes time during manufacturing/testing of the op-amp, and is therefore generally expensive to perform. The calibration is typically performed at one operating point (e.g., temperature, common mode voltage, etc.) such that changes in operating environment, e.g., temperature, voltage, etc., are not compensated for in the manufacturing/testing thereof. Technology has now advance to the point where the analog input and output devices can be fabricated on the same integrated circuit die on which the digital microcontroller, and its support logic and memories are also fabricated. This creates an additional problem in that the equipment used to test the digital microcontroller functions is not capable of performing on-line calibration of analog functions efficiently. Therefore, additional testing equipment and testing steps are required at the time of manufacture. Also the test mode logic and interfacing/multiplexing circuits become more complicated, especially if the number pins (external connections) of integrated circuit package are few in number.

    [0005] An instrumentation amplifier has sources of error, including offset error, gain error, and circuit parasitics that limit performance thereof. Calibration of the instrumentation amplifier is desirable to reduce these errors, making the instrumentation amplifier suitable for a broader range of applications. An example for offset correction control for an amplifier is given in US 6 141 169.

    SUMMARY



    [0006] Therefore there is a need to be able to automatically reduce offset and gain errors of an analog input device, e.g., an instrumentation amplifier. It is also desirable that an analog input device may be calibrated in an end user system application to meet the desired specifications and operating parameters over all operating conditions such as temperature, voltage, current, speed, power, pressure, humidity, etc., that may be encountered during normal operation and any changes thereof, and can be mass-produced to reduce overall product costs. These and other objects can be achieved by an instrumentation amplifier and/or method as defined in the independent claims. Further enhancements are characterized in the dependent claims.

    [0007] The analog input device may be fabricated on an integrated circuit having both analog and digital functions (e.g., a mixed-signal device). The analog input device may include, but is not limited to, a differential or single-ended input operational amplifier, a comparator, a programmable gain amplifier (PGA), an instrumentation amplifier (INA), low noise amplifier, etc. An example of a mixed-signal device having offset voltage calibration is described in commonly owned United States Patent No. 6,459,335; entitled "Auto-Calibration Circuit to Minimize Input Offset Voltage in an Integrated Circuit Analog Input Device," by Hartono Darmawaskita, Layton Eagar and Miguel Moreno; and is hereby incorporated by reference herein for all purposes.

    [0008] This need may be satisfied, according to the teachings of this disclosure, with an apparatus and method for auto-calibration of both gain and offset of the analog circuits when requested by a user and/or the occurrence of an event(s). The user may invoke an auto-calibration of gain and/or offset on demand through an auto-calibration (ACAL) input to the mixed-signal integrated circuit. A reference voltage (VCAL) calibration input may be used for auto-calibration of the mixed-signal integrated circuit to a user-supplied common-mode voltage reference. Auto-calibration of gain and/or offset of the mixed-signal integrated circuit device may also be initiated upon the occurrence of any one or more of the following events, such as for example but not limited to: 1) detection of auto-calibration data corruption, e.g., parity checking of auto-calibration data values digitally stored in the mixed-signal integrated circuit; 2) an internal timer that causes a calibration request after a programmable timeout period, 3) change in the internal integrated circuit die temperature as determined by a temperature sensor, and 4) change in the power supply and/or internal supply voltage(s) from internal regulator(s) (e.g., bias network).

    [0009] In addition, a user may compensate with calibration of the gain and/or offset of the analog circuits to compensate for variations in the end system, including operating point, e.g., power supply, common-mode, etc.; environmental changes, e.g., temperature, humidity, etc.; and also to compensate for component drift over time, e.g., aging effects, etc.

    [0010] During gain adjustment calibration a reference voltage, VCAL, is applied to an input of the analog device and the output of the analog device is compared to the reference voltage, VCAL, with a voltage comparator. A digital control circuit is used to apply a digital word to the gain adjustment circuit for determining a digital value representative of the required gain adjustment calibration. During offset calibration the differential inputs of the analog device are shorted together and also connected to a reference voltage, e.g., VCAL. The output of the analog device is compared to the reference voltage, VCAL, with the voltage comparator. The digital control circuit applies a digital word to the input offset compensation circuit for determining a digital value representative of the required input offset compensation. A linear search or binary search of various digital values of the digital word may be used by the digital control circuit to accomplish both gain and offset calibration.

    [0011] A voltage comparator compares the output of the analog input device and a voltage reference. When the output of the analog input device is equal to or greater than the voltage reference, the comparator output switches from a first logic level to a second logic level. The output of the comparator is connected to the digital control circuit and signals the digital control circuit by changing its output logic level.

    [0012] The voltage reference may be programmable for selecting a desired voltage value to be applied to the analog input device and comparator inputs during the gain and/or offset calibration cycle(s). This allows the ability to vary the voltage reference so as to facilitate calibration at the common mode voltage which is very close to that of the application of use. The appropriate voltage reference value may be written to a control register associated with the voltage reference circuit before initiating the auto calibration of the analog input device. Different voltage reference values may be used for different analog input devices during gain and/or input offset voltage compensation calibration thereof.

    [0013] Fuse links, programmable read only memory, etc. may be used to control compensation switches for the gain and input offset adjustments. However, a preferred way to accomplish gain adjustment and/or input offset voltage compensation circuit of the analog input device is to use at least one storage register or memory that retains the digital value(s) used to control switches for connecting constant current sources and sinks in the differential analog input circuits necessary to compensating the gain and/or input offset voltage of the INA. The storage register(s) may be volatile or nonvolatile depending upon the application desired. Therefore, no factory calibration during manufacture and/or testing is required, programmable fuse link trimming may be eliminated, and end user application flexibility increased.

    [0014] A plurality of analog input devices may have their gains and/or input offsets calibrated by multiplexing the digital control circuit and comparator between each of the plurality of analog input devices. Thus circuits and die area are reduced, saving costs and improving reliability of a mixed-signal integrated circuit device.

    [0015] According to a specific example embodiment of this disclosure, an instrumentation amplifier having gain and offset calibration using constant current sources and sinks comprises: a first transconductance stage having positive and negative voltage inputs, and positive and negative current outputs; a second transconductance stage having positive and negative voltage inputs, and positive and negative current outputs; a trans-impedance amplifier having positive and negative current inputs and a voltage output; the positive current outputs of the first and second transconductance stages and the positive current input of the trans-impedance amplifier are coupled together; the negative current outputs of the first and second transconductance stages and the negative current input of the trans-impedance amplifier are coupled together; a first plurality of constant current sources; a first plurality of switches, wherein the first plurality of switches selectably couple certain ones of the first plurality of constant current sources to the first transconductance stage; a second plurality of constant current sources; a second plurality of switches, wherein the second plurality of switches selectably couple certain ones of the second plurality of constant current sources to the second transconductance stage; a third plurality of constant current sinks; a third plurality of switches, wherein the third plurality of switches selectably connect certain ones of the third plurality of constant current sinks to the positive current outputs of the first and second transconductance stages; a fourth plurality of constant current sinks; and a fourth plurality of switches, wherein the fourth plurality of switches selectably couple certain ones of the fourth plurality of constant current sinks to the negative current outputs of the first and second transconductance stages; whereby gain adjustment of the instrumentation amplifier is provided by selectably coupling the certain ones of the first and second plurality of constant current sources to the first and second transconductance stages, respectively; and whereby input offset adjustment of the instrumentation amplifier is provided by selectably coupling the certain ones of the third and fourth plurality of constant current sinks to the positive current outputs and the negative current outputs, respectively, of the first and second transconductance stages.

    [0016] According to another specific example embodiment of this disclosure, a method for calibrating gain and offset of an instrumentation amplifier using constant current sources and sinks comprises the steps of: adjusting gain of an instrumentation amplifier by selectably coupling certain ones of a plurality of constant current sources to first and second transconduction stages of the instrumentation amplifier; and adjusting offset of the instrumentation amplifier by selectably coupling certain ones of a plurality of constant current sinks to positive and negative outputs of the first and second transconduction stages of the instrumentation amplifier. coupling a positive input of the instrumentation amplifier to a first gain setting resistor network and a negative input of the instrumentation amplifier to a power source common; coupling a feedback input of the instrumentation amplifier to a second gain setting resistor network and a reference input of the instrumentation amplifier to the power source common, wherein the first and second gain setting resistor networks are substantially the same; comparing an output voltage of the instrumentation amplifier to the reference voltage; and selectably coupling certain ones of the plurality of constant current sources to the first and second transconduction stages of the instrumentation amplifier until the output voltage from the instrumentation amplifier is substantially the same as the reference voltage. The step of adjusting the offset of the instrumentation amplifier comprises the steps of: coupling positive and negative inputs of the instrumentation amplifier to a reference voltage; coupling a feedback input of the instrumentation amplifier to a gain setting resistor network and a reference input of the instrumentation amplifier to the reference voltage; comparing an output voltage of the instrumentation amplifier to a reference voltage; and selectably coupling certain ones of the plurality of constant current sinks to the positive and negative outputs of the first and second transconduction stages of the instrumentation amplifier until the output voltage from the instrumentation amplifier is substantially the same as the reference voltage. The step of adjusting the gain occurs before the step of adjusting the offset because the gain adjustment may affect offset, but not vice versa.

    BRIEF DESCRIPTION OF THE DRAWINGS



    [0017] A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:

    Figure 1 illustrates a schematic block diagram of a basic architecture for an instrumentation amplifier (INA);

    Figure 2 illustrates a schematic diagram of a circuit for trimming gain and offset for the INA of Figure 1, according to a specific example embodiment of this disclosure;

    Figure 3 illustrates a schematic circuit diagram of a switching arrangement for gain calibration of the INA of Figure 1, according to the teachings of this disclosure;

    Figure 4 illustrates a schematic circuit diagram of a switching arrangement for offset calibration of the INA of Figure 1, according to the teachings of this disclosure; and

    Figure 5 illustrates a schematic block circuit diagram of a digital calibration circuit used in combination with the circuits shown in Figures 2-4, according to the teachings of this disclosure.



    [0018] While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.

    DETAILED DESCRIPTION



    [0019] Referring now to the drawings, the details of example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

    [0020] Referring to Figure 1, depicted is a schematic block diagram of a basic architecture for an instrumentation amplifier (INA). An instrumentation amplifier (INA) 102 having indirect current feedback comprises a first transconductance stage 104, a second transconductance stage 110, a trans-impedance amplifier 108, and a summing node 106. The output current, I1, from the first transconductance stage 104 is added in the summing node 106, and the output current, I2, from the second transconductance stage 110 is subtracted in the summing node 106. The difference current output from the summing node 106 is applied to the trans-impedance amplifier 108 which converts this current input to a voltage output. The current summing operation provides for indirect current feedback. Ideally, the two output currents from the transconductance stages 104 and 110 should sum to zero, I1 - I2 = 0. Gain of the INA 102 is determined by the resistors 112 and 114 according to the formula:


    where G is the gain of the INA 102, GM1 is the gain of the first transconductance stage 104, GM2 is the gain of the second transconductance stage 110, RF is the resistance value of the resistor 112, and RG is the resistance value of the resistor 114.

    [0021] Referring to Figure 2, depicted is a schematic diagram of a circuit for trimming gain and offset for the INA of Figure 1, according to a specific example embodiment of this disclosure. The first transconductance stage 104 comprises transistors 260 and 264 connected as a differential input pair, a degeneration resistor 262, a plurality of constant current sources 230 and 232, and a plurality of switches 236 and 238 associated with the plurality of constant current sources 230 and 232, respectively. The second transconductance stage 110 comprises transistors 266 and 270 connected as a differential input pair, a degeneration resistor 268, a plurality of constant current sources 240 and 242, and a plurality of switches 246 and 248 associated with the plurality of constant current sources 240 and 242, respectively. Both of the transconductance stages 104 and 110 share a plurality of constant current sinks 234 and 244, and a plurality of switches 252 and 224 associated with the plurality of constant current sinks 234 and 244, respectively. The plurality of constant current sinks 234 and 244 are used to trim the offset of the INA 102. The plurality of constant current sinks 234 for offset trimming are associated with a positive (+) current rail of a load to the trans-impedance amplifier 108, and the plurality of constant current sinks 244 for offset trimming are associated with a negative (-) current rail of the load to the trans-impedance amplifier 108. The transistors 260, 264, 266 and 270 may be for example, but not limited to, metal oxide semiconductor field effect transistors (MOSFETs), e.g., either P-channel or N-channel.

    [0022] The gain of the INA 102 is adjusted by changing the tail constant current sources 230 and 232 for the transconductance stage 104, and/or the tail constant current sources 240 and 242 for the transconductance stage 110.

    [0023] Offset trimming is accomplished by adjusting the plurality of constant current sinks 234 and 244 on either side (+ and -) of the differential pair load. An advantage of trimming offset at the differential pair load is that it does not affect the gain of the INA 102. Therefore, preferably the gain of the INA 102 may be adjusted first then the offset thereof trimmed to substantially zero. Thereby any additional offset introduced by the gain adjustment may be compensated for during the offset trimming operation.

    [0024] Referring to Figure 3, depicted is a schematic circuit diagram of a switching arrangement for gain calibration of the INA of Figure 1, according to the teachings of this disclosure. Calibration switches 356-364 are shown connected in position "b" and gain/offset calibration switches 372a and 372b are shown connected in position "c" for gain calibration. For normal operation of the INA 102 the calibration switches 356-364 would be connected in position "a". The positions of the gain/offset calibration switches 372a and 372b are irrelevant during normal operation of the INA 102.

    [0025] During gain calibration, when the calibration switches 356-364 are in position "b" and the gain/offset calibration switches 372a and 372b are in position "c", the positive input of the INA 102 is connected to the junction of an internal feedback resistor 112a (RF) and an internal gain setting resistor 114a (RG). The other end of the internal feedback resistor 112a (RF) is connected to the reference voltage 370, VCAL, from the calibration voltage reference 354, and the other end of the internal gain setting resistor 114a (RG) 114a is connected to a common reference potential 374, e.g., ground. A negative input of the INA 102 is connected to the common reference potential 374, e.g., ground; the external nodes 116 (OUT), 118 (IN+), 120 (IN-), 122 (FB) and 124 (REF) are disconnected from the INA 102. The reference input 380 of the INA 102 is connected to the common reference potential 374, e.g., ground. The feedback input 382 of the INA 102 is connected to the to the junction of an internal feedback resistor 112 (RF) and an internal gain setting resistor 114 (RG).

    [0026] The internal gain setting resistors 114 and 114a (RG), and the internal feedback resistors 112 and 112a (RF) are connected to the INA 102 during the gain calibration operation. The internal gain setting resistors 114 and 114a (RG), and the internal feedback resistors 112 and 112a (RF) configure the INA 102 to have high gain for more accurate gain calibration. The internal gain setting resistors 114 and 114a (RG) are matched to have substantially the same resistances. Similarly, the internal feedback resistors 112 and 112a (RF) are matched to have substantially the same resistances. Thus, the INA 102 output will be approximately the same voltage value as the reference voltage 370, VCAL.

    [0027] The output node 116 is disconnected from the output of the INA 102 so that the output of the INA 102 can be connected to a positive input of a comparator 352 (a tri-state output of the INA 102 may serve the same purpose). The reference voltage, VCAL, from the calibration voltage reference 354 may be, for example but is not limited to, about half way between the supply voltage, VDD (not shown) and the common reference potential 374.

    [0028] The gain of the INA 102 is calibrated when the voltage at the positive input of the comparator 352 is substantially the same value as the reference voltage, VCAL, at the negative input of the comparator 352. The output of the comparator 352 will be at either a logic one (high) or a logic zero (low) depending on whether the voltage on the positive input is greater than, or less than or equal to the calibration voltage. The comparator 352 output 368 may be coupled to a successive approximation register (SAR) in Figure 5, and is part of a successive approximation analog-to-digital converter (ADC) used in determining which ones of the plurality of constant current sources 230, 232, 240 and/or 242 will be connected in the INA 102 circuit (Figure 2) as more fully described herein for the digital calibration circuits shown in Figures 2 and 5.

    [0029] Preferably the gain calibration may be performed first since gain adjustment does not substantially affect offset, however, if any offset of the INA 102 is introduced during selection of the gain setting constant current sources 230, 232, 240 and/or 242 (Figure 2), then during offset calibration the gain setting induced offset will be substantially canceled out.

    [0030] Referring to Figure 4, depicted is a schematic circuit diagram of a switching arrangement for offset calibration of the INA of Figure 1, according to the teachings of this disclosure. Calibration switches 356-364 are shown connected in position "b" and gain/offset calibration switches 372a and 372b are shown connected in position "d" for offset calibration. For normal operation of the INA 102 the calibration switches 356-364 would be connected in position "a". The positions of the gain/offset calibration switches 372a and 372b are irrelevant during normal operation of the INA 102.

    [0031] During offset calibration, when the calibration switches 356-364 are in position "b" and the gain/offset calibration switches 372a and 372b are in position "d", the differential inputs of the INA 102 are connected to the calibration voltage reference 354. The reference voltage 370, VCAL, from the calibration voltage reference 354 may be, for example but is not limited to, about half way between the supply voltage, VDD (not shown) and the common reference potential 374. The external nodes 116 (OUT), 118 (IN+), 120 (IN-), 122 (FB) and 124 (REF) are disconnected from the INA 102, wherein an internal gain setting resistor 114 (RG) and an internal feedback resistor 112 (RF) are used in the INA 102 during the offset calibration operation. The internal gain setting resistor 114 (RG) and the internal feedback resistor 112 (RF) configure the operation of the INA 102 to have high gain for a more accurate offset calibration. The output node 116 is disconnected from the output of the INA 102 so that the output of the INA 102 can be connected to a positive input of a comparator 352 (a tri-state output of the INA 102 may serve the same purpose). A negative input of the comparator 352 is connected to the calibration voltage reference 354 (e.g., reference voltage 370).

    [0032] Preferably it is desired that when the differential inputs of the INA 102 are connected together and to the reference voltage 370, VCAL, the output of the INA 102 should be approximately equal to the reference voltage 370, VCAL. This output condition will give the most equal (best) range between positive and negative swings of the output as a function of the differential input voltage during normal operation thereof. The output of the comparator 352 will be at either a logic one (high) or a logic zero (low) depending on whether the voltage on the positive input is greater than, or less than or equal to the calibration voltage. The comparator 352 output 368 may be coupled to a successive approximation register (SAR) in Figure 5, and is part of a successive approximation analog-to-digital converter (ADC) used in determining which ones of the plurality of constant current sinks 234 and/or 244 will be connected in the INA 102 circuit (Figure 2) as more fully described herein for the digital calibration circuits shown in Figures 2 and 5.

    [0033] Referring to Figure 5, depicted is a schematic block circuit diagram of a digital calibration circuit used in combination with the circuits shown in Figures 2-4, according to the teachings of this disclosure. A digital calibration circuit, generally represented by the numeral 500, comprises a timer 502, a calibrate logic state machine 504, a successive approximation register (SAR) 506, a gain trim register 510, a gain trim register parity detection circuit 512, an offset trim register 514, an offset trim register parity detection circuit 516, an OR gate 508 for logically indicating an error from either one of the trim register parity detection circuits 512 and 514, a power-on-reset (POR) 530, and a clock oscillator 524.

    [0034] According to the teachings of this disclosure, whenever parity checking of the trim register contents detects a parity error therein, a self auto-calibration cycle may be initiated. This may be implemented by using the gain trim register parity detection circuit 512 to detect a parity error in the trim data contents of the gain trim register 510. When a parity error is detected, the gain trim register parity detection circuit 512 asserts a parity error detected signal and the POR 530 will initiate the start of a new self auto-calibration cycle. Likewise when a parity error is detected in the offset trim register 514, the offset trim register parity detection circuit 516 asserts a parity error detected signal and the POR 530 will initiate the start of a new self auto-calibration cycle. An OR gate 508 may be used to combine parity error detected signals from the gain trim register parity detection circuit 512 or the offset trim register parity detection circuit 516. Other logic combinations may be implemented instead of the OR gate 508 and is contemplated herein.

    [0035] During a self auto-calibration cycle, the parity bit may be automatically determined by the calibrate logic state machine 504 and stored in a parity bit location of the trim register 510 or 514. In this example, there is one parity bit for each trim register 510 and 514. If a parity error occurs (during normal operation of the INA 102), a power-on-reset from the POR 530 is forced and a new auto-calibration cycle takes place. This is important because the trim register contents may be stored in volatile registers (memory), and the trim data contained therein may be corrupted during a power glitch. Also a soft data error may occur from cosmic radiation, e.g., space applications. Therefore, parity checking of the trim registers 510 and 514 contents provide some protection against corruption of gain and offset trim value data storage in a volatile memory configuration. On the other hand, the trim register contents may be stored in non-volatile memory, and a parity bit and parity checking may not be needed in a non-volatile memory configuration. It is contemplated and within the scope of this disclosure that trim data may be stored in volatile and/or non-volatile memory, with or without a parity bit and parity checking.

    [0036] An auto-calibration may also be initiated by toggling a user programmed auto-calibration input, ACAL. This feature avoids having to power down the mixed signal integrated circuit device to re-calibrate the INA 102 therein. It also saves time because the delay time is much shorter than if a complete power-up is required (e.g., approximately 1 millisecond versus 150 milliseconds). At power-up, the delay is much longer because the timer time-out is designed to wait for system power supplies to settle (stabilize). If a calibration is initiated by the auto-calibration input, ACAL, such a long delay is not required.

    [0037] Having the ACAL calibration input makes it easy for an applications program, e.g., a control signal from a microcontroller to cause a self auto-calibration by toggling a logic level to the ACAL calibration input. The microcontroller and/or circuits within a self auto-calibration integrated circuit device (not shown) could invoke a self auto-calibration, according to the teachings of this disclosure, based upon any change in a system conditions, e.g., power supply voltage, temperature, and/or at fixed time-intervals.

    [0038] While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and function, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only.


    Claims

    1. An instrumentation amplifier having gain and offset calibration using constant current sources and sinks, comprising:

    a first transconductance stage (260, 262, 264) having positive and negative voltage inputs, and positive and negative current outputs;

    a second transconductance stage (266, 268, 270) having positive and negative voltage inputs, and positive and negative current outputs;

    a trans-impedance amplifier (108) having positive and negative current inputs and a voltage output;

    the positive current outputs of the first and second transconductance stages (260, 262, 264; 266, 268, 270) and the positive current input of the trans-impedance amplifier (108) are coupled together;

    the negative current outputs of the first and second transconductance stages (260, 262, 264; 266, 268, 270) and the negative current input of the trans-impedance amplifier (108) are coupled together;

    a first plurality of constant current sources (230, 232);

    a first plurality of switches (236, 238), wherein the first plurality of switches (236, 238) selectably couple certain ones of the first plurality of constant current sources (230, 232) to the first transconductance stage;

    a second plurality of constant current sources (240, 242);

    a second plurality of switches (246, 248), wherein the second plurality of switches (246, 248) selectably couple certain ones of the second plurality of constant current sources (240, 242) to the second transconductance stage (110);

    a third plurality of constant current sinks (244);

    a third plurality of switches (254), wherein the third plurality of switches (254) selectably connect certain ones of the third plurality of constant current sinks (244) to the positive current outputs of the first and second transconductance stages (104, 110);

    a fourth plurality of constant current sinks (234); and

    a fourth plurality of switches (252), wherein the fourth plurality of switches (252) selectably couple certain ones of the fourth plurality of constant current sinks (244) to the negative current outputs of the first and second transconductance stages (260, 262, 264; 266, 268, 270);

    whereby gain adjustment of the instrumentation amplifier is provided by selectably coupling the certain ones of the first and second plurality of constant current sources (230, 232, 240, 242) to the first and second transconductance stages (260, 262, 264; 266, 268, 270), respectively; and

    whereby input offset adjustment of the instrumentation amplifier is provided by selectably coupling the certain ones of the third and fourth plurality of constant current sinks (234, 244) to the positive current outputs and the negative current outputs, respectively, of the first and second transconductance stages (260, 262, 264; 266, 268, 270).


     
    2. The instrumentation amplifier according to claim 1, wherein the first transconductance stage (260, 262, 264) and/or the second transconductance stage (266, 268, 270) each comprise:

    a first metal oxide field effect transistor (MOSFET) (264; 270) having a source, gate and drain;

    a second MOSFET (260; 266) having a source, gate and drain;

    wherein the sources of the first and second MOSFETs (264, 260; 270, 266) are selectably coupled to the certain ones of the first or second plurality of constant current sources (230, 232; 242, 240);

    wherein the drain of the first MOSFET (264; 270) is the positive current output of the respective transconductance stage (260, 262, 264; 266, 268, 270); and

    wherein the drain of the second MOSFET (260; 266) is the negative current output of the respective transconductance stage (260, 262, 264; 266, 268, 270).


     
    3. The instrumentation amplifier according to claim 2, wherein the first and second MOSFETs (264, 260; 270, 266) are P-channel MOSFETs.
     
    4. The instrumentation amplifier according to claim 2, wherein the first and second MOSFETs (264, 260; 270, 266) are N-channel MOSFETs.
     
    5. The instrumentation amplifier according to one of the preceding claims, wherein the first, second, third and fourth plurality of switches comprise transistors.
     
    6. The instrumentation amplifier according to one of the preceding claims, wherein the instrumentation amplifier (102) is fabricated on an integrated circuit die.
     
    7. The instrumentation amplifier according to one of the preceding claims 1-5, wherein a plurality of instrumentation amplifiers (102) are fabricated on an integrated circuit die.
     
    8. The instrumentation amplifier according to one of the preceding claims, further comprising an auto-calibration circuit for calibrating gain and offset of the instrumentation amplifier (102).
     
    9. The instrumentation amplifier according to claim 8, wherein the auto-calibration circuit comprises:

    a voltage reference (354) providing a reference voltage;

    a voltage comparator (352) having first and second analog inputs and a digital output, the first analog input is coupled to a voltage from the output of the trans-impedance amplifier (108) and the second analog input is coupled to the reference voltage from the voltage reference (354), wherein when the voltage on the first analog input is greater than the reference voltage on the second analog input the digital output is at a first logic level, and when the voltage on the first analog input is less than or equal to the reference voltage on the second analog input, the digital output is at a second logic level;

    a successive approximation register (SAR) (506) having a digital input coupled to the digital output of the voltage comparator (352) and outputs coupled to the first, second, third and fourth plurality of switches (236, 238, 246, 248, 252, 254); and

    calibration logic (504),

    wherein when the positive input of the first transconduction stage (260, 262, 264) is coupled to the reference voltage (354), and the first and second transconduction stages (260, 262, 264; 266, 268, 270)are configured to provide a desired gain of the instrumentation amplifier (102) the calibration logic controls the first and second plurality of switches (236, 238, 246, 248) to selectably couple the certain ones of the first and second plurality of constant current sources (230, 232, 240, 242) so as to calibrate the gain of the instrumentation amplifier (102), and

    wherein when the positive and negative inputs of the first transconduction stage (260, 262, 264) are coupled together and to a reference voltage (354), and the positive and negative inputs of the second transconduction stage (266, 268, 270) are configured to provide a desired gain of the instrumentation amplifier (102) the calibration logic (504) controls the third and fourth plurality of switches (252, 254) to selectably couple the certain ones of the third and fourth plurality of constant current sinks (234, 244) so as to calibrate the input offset of the instrumentation amplifier (102).


     
    10. The instrumentation amplifier according to claim 9, further comprising a plurality of registers (510, 512, 514) coupled between the SAR (506) and the first, second, third and fourth plurality of switches (236, 238, 246, 248, 252, 254), respectively, for storing auto-calibration values from the SAR (506).
     
    11. The instrumentation amplifier according to claim 10, further comprising parity checking (516) of the plurality of registers (510, 512, 514).
     
    12. A method for calibrating gain and offset of an instrumentation amplifier using constant current sources and sinks, wherein the instrumentation amplifier (102) comprises first and second transconductance stages (260, 262, 264; 266, 268, 270) and a trans-impedance amplifier (108) , wherein the outputs of the first and second transconductance stages (260, 262, 264; 266, 268, 270) and the input of the trans-impedance amplifier (108) are coupled together, said method comprising the steps of:

    adjusting gain of an instrumentation amplifier (102) by selectably coupling certain ones of a plurality of constant current sources (230, 232, 240, 242) to the first and second transconduction stages (260, 264; 266, 270) of the instrumentation amplifier (102); and

    adjusting offset of the instrumentation amplifier (102) by selectably coupling certain ones of a plurality of constant current sinks (234, 244) to positive and negative outputs of the first and second transconduction stages (260, 262, 264; 266, 268, 270) of the instrumentation amplifier (102).


     
    13. The method according to claim 12, wherein the step of adjusting the gain of the instrumentation amplifier (102) comprises the steps of:

    coupling a positive input of the instrumentation amplifier (102) to a first gain setting resistor network (112a, 114a) and a negative input of the instrumentation amplifier to a power source common (374);

    coupling a feedback input (382) of the instrumentation amplifier (102) to a second gain setting resistor network (112, 114) and a reference input (380) of the instrumentation amplifier (102) to the power source common (374), wherein the first and second gain setting resistor networks (112, 114, 112a, 114a) are substantially the same in value;

    comparing an output voltage of the instrumentation amplifier (102) to a reference voltage (354); and

    selectably coupling certain ones of the plurality of constant current sources (230, 232, 240, 242) to the first and second transconduction stages (260, 262, 264; 266, 268, 270) of the instrumentation amplifier (102) until the output voltage from the instrumentation amplifier (102) is substantially the same as the reference voltage (354).


     
    14. The method according to claim 12 or 13, wherein the step of adjusting the offset of the instrumentation amplifier (102) comprises the steps of:

    coupling positive and negative inputs of the instrumentation amplifier (102) to a reference voltage (354);

    coupling a feedback input (382) of the instrumentation amplifier (102) to a gain setting resistor network (112, 114) and a reference input (380) of the instrumentation amplifier (102) to the reference voltage (354);

    comparing an output voltage of the instrumentation amplifier (102) to the reference voltage (354); and

    selectably coupling certain ones of the plurality of constant current sinks (234, 244) to the positive and negative outputs of the first and second transconduction stages (260, 262, 264; 266, 268, 270) of the instrumentation amplifier (102) until the output voltage from the instrumentation amplifier (102) is substantially the same as the reference voltage (354).


     
    15. The method according to one of the preceding claims 12-14, wherein the step of adjusting the gain occurs before the step of adjusting the offset.
     


    Ansprüche

    1. Instrumentierungsverstärker mit Gain- und Offset-Kalibrierung unter Verwendung von Konstantstromquellen und -senken, der aufweist:

    eine erste Transkonduktanzstufe (260, 262, 264), die positive und negative Spannungseingänge und positive und negative Stromausgänge aufweist;

    eine zweite Transkonduktanzstufe (266, 268, 270), die positive und negative Spannungseingänge und positive und negative Stromausgänge aufweist;

    einen Transimpedanzverstärker (108) mit positiven und negativen Stromeingängen und einem Spannungsausgang;

    die positiven Stromausgänge der ersten und zweiten Transkonduktanzstufen (260, 262, 264, 266, 268, 270) und der positive Stromeingang des Transimpedanzverstärkers (108) sind miteinander gekoppelt;

    die negativen Stromausgänge der ersten und zweiten Transkonduktanzstufen (260, 262, 264, 266, 268, 270) und der negative Stromeingang des Transimpedanzverstärkers (108) sind miteinander gekoppelt;

    eine erste Vielzahl von Konstantstromquellen (230, 232);

    eine erste Vielzahl von Schaltern (236, 238), wobei die erste Vielzahl von Schaltern (236, 238) wählbar bestimmte der ersten Vielzahl von Konstantstromquellen (230, 232) mit der ersten Transkonduktanzstufe koppelt;

    eine zweite Vielzahl von Konstantstromquellen (240, 242);

    eine zweite Vielzahl von Schaltern (246, 248), wobei die zweite Vielzahl von Schaltern (246, 248) wählbar bestimmte der zweiten Vielzahl von Konstantstromquellen (240, 242) mit der zweiten Transkonduktanzstufe (110) koppelt;

    eine dritte Vielzahl von Konstantstromsenken (244);

    eine dritte Vielzahl von Schaltern (254), wobei die dritte Vielzahl von Schaltern (254) wählbar bestimmte der dritten Vielzahl von Konstantstromsenken (244) mit den positiven Stromausgängen der ersten und zweiten Transkonduktanzstufen (104, 110) verbindet;

    eine vierte Vielzahl von Konstantstromsenken (234); und

    eine vierte Vielzahl von Schaltern (252), wobei die vierte Vielzahl von Schaltern (252) wählbar bestimmte der vierten Vielzahl von Konstantstromsenken (244) mit den negativen Stromausgängen der ersten und zweiten Transkonduktanzstufen koppelt;

    wobei die Verstärkungseinstellung des Instrumentierungsverstärkers durch wählbares Koppeln der bestimmten der ersten und zweiten Vielzahl von Konstantstromquellen (230, 232, 240, 242) mit den ersten beziehungsweise zweiten Transkonduktanzstufen (260, 262, 264, 266, 268, 270) bereitgestellt wird; und

    wobei der Eingangs-Offset-Abgleich des Instrumentierungsverstärkers durch wählbares Koppeln der bestimmten der dritten und vierten Vielzahl von Konstantstromsenken (234, 244) mit den positiven Stromausgängen beziehungsweise den negativen Stromausgängen der ersten und zweiten Transkonduktanzstufen (260, 262, 264, 266, 268, 270) bereitgestellt wird.


     
    2. Instrumentierungsverstärker nach Anspruch 1, wobei die erste Transkonduktanzstufe (260, 262, 264) und/oder die zweite Transkonduktanzstufe (266, 268, 270) jeweils aufweisen:

    einen ersten Metalloxid-Feldeffekttransistor (MOSFET) (264; 270), der einen Source-Anschluss, einen Gate-Anschluss und einen Drain-Anschluss aufweist;

    einen zweiten MOSFET (260, 266), der einen Source-Anschluss, einen Gate-Anschluss und einen Drain-Anschluss aufweist;

    wobei die Source-Anschlüsse der ersten und zweiten MOSFETs (264, 260; 270, 266) wählbar mit den bestimmten der ersten oder zweiten Vielzahl von Konstantstromquellen (230, 232; 242, 240) gekoppelt sind;

    wobei der Drain-Anschluss des ersten MOSFET (264; 270) der positive Stromausgang der entsprechenden Transkonduktanzstufe (260, 262, 264; 266, 268, 270) ist; und

    wobei der Drain-Anschluss des zweiten MOSFET (260; 266) der negative Stromausgang der entsprechenden Transkonduktanzstufe (260, 262, 264; 266, 268, 270) ist.


     
    3. Instrumentierungsverstärker gemäß Anspruch 2, wobei die ersten und zweiten MOSFETs (264, 260; 270, 266) p-Kanal-MOSFETs sind.
     
    4. Instrumentierungsverstärker gemäß Anspruch 2, wobei die ersten und zweiten MOSFETs (264, 260; 270, 266) n-Kanal-MOSFETs sind.
     
    5. Instrumentierungsverstärker gemäß einem der vorherigen Ansprüche, wobei die erste, zweite, dritte und vierte Vielzahl von Schaltern Transistoren aufweist.
     
    6. Instrumentierungsverstärker gemäß einem der vorherigen Ansprüche, wobei der Instrumentierungsverstärker (102) auf einem integrierten Schaltungschip hergestellt ist.
     
    7. Instrumentierungsverstärker gemäß einem der vorherigen Ansprüche 1 bis 5, wobei eine Vielzahl von Instrumentierungsverstärkern (102) auf einem integrierten Schaltungschip hergestellt ist.
     
    8. Instrumentierungsverstärker gemäß einem der vorherigen Ansprüche, der weiterhin eine Autokalibrierungsschaltung zum Kalibrieren von Verstärkung und Offset des Instrumentierungsverstärkers (102) aufweist.
     
    9. Instrumentierungsverstärker gemäß Anspruch 8, wobei die Autokalibrierungsschaltung aufweist:

    eine Spannungsreferenz (354), die eine Referenzspannung bereitstellt;

    einen Spannungskomparator (352), der erste und zweite analoge Eingänge und einen digitalen Ausgang aufweist, wobei der erste analoge Eingang mit einer Spannung von dem Ausgang des Transimpedanzverstärkers (108) gekoppelt ist und der zweite analoge Eingang mit der Referenzspannung von der Spannungsreferenz (354) gekoppelt ist, wobei, wenn die Spannung an dem ersten analogen Eingang größer ist als die Referenzspannung an dem zweiten analogen Eingang, das digitale Ausgangssignal einen ersten Logikpegel aufweist, und wenn die Spannung am ersten analogen Eingang kleiner als oder gleich der Referenzspannung an dem zweiten analogen Eingang ist, der digitale Ausgang einen zweiten logischen Pegel aufweist;

    ein Register für sukzessive Approximation (SAR) (506), das einen digitalen Eingang aufweist, der mit dem digitalen Ausgang des Spannungskomparators (352) gekoppelt ist und Ausgänge aufweist, die mit der ersten, zweiten, dritten und vierten Vielzahl von Schaltern (236, 238, 246, 248, 252, 254) gekoppelt ist; und

    eine Kalibrierungslogik (504),

    wobei, wenn der positive Eingang der ersten Transkonduktanzstufe (260, 262, 264) mit der Referenzspannung (354) gekoppelt ist, und die ersten und zweiten Transkonduktanzstufen (260, 262, 264; 266, 268, 270) konfiguriert sind, um eine erwünschte Verstärkung des Instrumentierungsverstärkers (102) bereitzustellen, die Kalibrierungslogik die erste und die zweite Vielzahl von Schaltern (236, 238, 246, 248) steuert, um wählbar die bestimmten der ersten und zweiten Vielzahl von Konstantstromquellen (230, 232, 240, 242) zu koppeln, um so die Verstärkung des Instrumentierungsverstärkers (102) zu kalibrieren, und

    wobei, wenn die positiven und negativen Eingänge der ersten Transkonduktanzstufe (260, 262, 264) miteinander und mit einer Referenzspannung (354) gekoppelt sind, und die positiven und negativen Eingänge der zweiten Transkonduktanzstufe (266, 268, 270) konfiguriert sind, um eine erwünschte Verstärkung des Instrumentierungsverstärkers (102) bereitzustellen, die Kalibrierungslogik (504) die dritte und vierte Vielzahl von Schaltern (252, 254) steuert, um wählbar die bestimmten der dritten und vierten Vielzahl von Konstantstromsenken (234, 244) zu koppeln, um so den Eingangs-Offset des Instrumentierungsverstärkers (102) zu kalibrieren.


     
    10. Instrumentierungsverstärker gemäß Anspruch 9, der weiterhin eine Vielzahl von Registern (510, 512, 514) aufweist, die zwischen dem SAR (506) und der ersten, zweiten, dritten beziehungsweise vierten Vielzahl von Schaltern (236, 238, 246, 248, 252, 254) gekoppelt sind, um Autokalibrierungswerte von dem SAR (506) zu speichern.
     
    11. Instrumentierungsverstärker gemäß Anspruch 10, der weiterhin Paritätsprüfung (516) der Vielzahl von Registern (510, 512, 514) aufweist.
     
    12. Verfahren zum Kalibrieren von Verstärkung und Offset eines Instrumentierungsverstärkers unter Verwendung von Konstantstromquellen und -senken, wobei der Instrumentierungsverstärker (102) erste und zweite Transkonduktanzstufen (260, 262, 264; 266, 268, 270) und einen Transimpedanzverstärker (108) aufweist, wobei die Ausgänge der ersten und zweiten Transkonduktanzstufen (260, 262, 264; 266, 268, 270) und der Eingang des Transimpedanzverstärkers (108) miteinander gekoppelt sind, wobei das Verfahren die folgenden Schritte aufweist:

    Einstellen der Verstärkung eines Instrumentierungsverstärkers (102) durch wählbares Koppeln bestimmter einer Vielzahl von Konstantstromquellen (230, 232, 240, 242) mit den ersten und zweiten Transkonduktanzstufen (260, 264; 266, 270) des Instrumentierungsverstärkers (102); und

    Einstellen des Offset des Instrumentierungsverstärkers (102) durch wählbares Koppeln bestimmter von einer Vielzahl von Konstantstromsenken (234, 244) mit positiven und negativen Ausgängen der ersten und zweiten Transkonduktanzstufen (260, 264; 266, 270) des Instrumentierungsverstärkers (102).


     
    13. Verfahren gemäß Anspruch 12, wobei der Schritt des Einstellens der Verstärkung des Instrumentierungsverstärkers (102) die folgenden Schritte aufweist:

    Koppeln eines positiven Eingangs des Instrumentierungsverstärkers (102) mit einem ersten Verstärkungseinstellungswiderstandsnetzwerk (112a, 114a) und eines negativen Eingangs des Instrumentierungsverstärkers mit einer gemeinsamen Leitung (374) einer Stromquelle;

    Koppeln eines Rückkopplungseingangs (382) des Instrumentierungsverstärkers (102) mit einem zweiten Verstärkungseinstellungswiderstandsnetzwerk (112, 114) und eines Referenzeingangs (380) des Instrumentierungsverstärkers (102) mit der gemeinsamen Leitung (374) der Stromquelle, wobei die ersten und zweiten Verstärkungseinstellungswiderstandsnetzwerke (112, 114, 112a, 114a) im Wesentlichen den gleichen Wert aufweisen;

    Vergleichen einer Ausgangsspannung des Instrumentierungsverstärkers (102) mit einer Referenzspannung (354); und

    wählbares Koppeln bestimmter der Vielzahl von Konstantstromquellen (230, 232, 240, 242) mit den ersten und zweiten Transkonduktanzstufen (260, 262, 264; 266, 268, 270) des Instrumentierungsverstärkers (102), bis die Ausgangsspannung des Instrumentierungsverstärkers (102) im Wesentlichen die gleiche ist wie die Referenzspannung (354).


     
    14. Verfahren gemäß Anspruch 12 oder 13, wobei der Schritt des Einstellens des Offset des Instrumentierungsverstärkers (102) die folgenden Schritte aufweist:

    Koppeln positiver und negativer Eingänge des Instrumentierungsverstärkers (102) mit einer Referenzspannung (354);

    Koppeln eines Rückkopplungseingangs (382) des Instrumentierungsverstärkers (102) mit einem Verstärkungseinstellungswiderstandsnetzwerk (112, 114) und eines Referenzeingangs (380) des Instrumentierungsverstärkers (102) mit der Referenzspannung (354);

    Vergleichen einer Ausgangsspannung des Instrumentierungsverstärkers (102) mit der Referenzspannung (354); und

    wählbares Koppeln bestimmter der Vielzahl von Konstantstromsenken (234, 244) mit den positiven und negativen Ausgängen der ersten und zweiten Transkonduktanzstufen (260, 262, 264; 266, 268, 270) des Instrumentierungsverstärkers (102), bis die Ausgangsspannung des Instrumentierungsverstärkers (102) im Wesentlichen die gleiche ist wie die Referenzspannung (354).


     
    15. Verfahren gemäß einem der vorherigen Ansprüche 12 bis 14, wobei der Schritt des Einstellens der Verstärkung vor dem Schritt des Einstellens des Offset stattfindet.
     


    Revendications

    1. Amplificateur d'instrumentation dont le gain et le décalage sont étalonnés en utilisant des sources et des consommateurs de courant constant, comprenant :

    un premier étage de transconductance (260, 262, 264) comportant des entrées de tension positive et négative, et des sorties de courant positive et négative ;

    un deuxième étage de transconductance (266, 268, 270) comportant des entrées de tension positive et négative, et des sorties de courant positive et négative ;

    un amplificateur à transimpédance (108) ayant des entrées de courant positive et négative et une sortie de tension ;

    les sorties de courant positives des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) et l'entrée de courant positive de l'amplificateur à transimpédance (108) sont couplées les unes aux autres ;

    les sorties de courant négatives des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) et l'entrée de courant négative de l'amplificateur à transimpédance (108) sont couplées les unes aux autres ;

    une première pluralité de sources de courant constant (230, 232) ;

    une première pluralité de commutateurs (236, 238), dans lequel la première pluralité de commutateurs (236, 238) couplent de manière sélectionnable certaines de la première pluralité de sources de courant constant (230, 232) au premier étage de transconductance ;

    une deuxième pluralité de sources de courant constant (240, 242) ;

    une deuxième pluralité de commutateurs (246, 248), dans lequel la deuxième pluralité de commutateurs (246, 248) couplent de manière sélectionnable certaines de la deuxième pluralité de sources de courant constant (240, 242) au deuxième étage de transconductance (110) ;

    une troisième pluralité de consommateurs de courant constant (244) ;

    une troisième pluralité de commutateurs (254), dans lequel la troisième pluralité de commutateurs (254) connectent de manière sélectionnable certains de la troisième pluralité de consommateurs de courant constant (244) aux sorties de courant positives des premier et deuxième étages de transconductance (104, 110) ;

    une quatrième pluralité de consommateurs de courant constant (234) ; et

    une quatrième pluralité de commutateurs (252), dans lequel la quatrième pluralité de commutateurs (252) couplent de manière sélectionnable certains de la quatrième pluralité de consommateurs de courant constant (244) aux sorties de courant négatives des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) ;

    moyennant quoi un ajustement de gain de l'amplificateur d'instrumentation est réalisé en couplant de manière sélectionnable certaines des première et deuxième pluralités de sources de courant constant (230, 232, 240, 242) aux premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270), respectivement ; et

    moyennant quoi un ajustement de décalage d'entrée de l'amplificateur d'instrumentation est réalisé en couplant de manière sélectionnable certains des troisième et quatrième pluralités de consommateurs de courant constant (234, 244) aux sorties de courant positives et aux sorties de courant négatives, respectivement, des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270).


     
    2. Amplificateur d'instrumentation selon la revendication 1, dans lequel le premier étage de transconductance (260, 262, 264) et/ou le deuxième étage de transconductance (266, 268, 270) comprennent chacun :

    un premier transistor à effet de champ à oxyde métallique (MOSFET) (264 ; 270) comportant une source, une grille et un drain ;

    un deuxième transistor MOSFET (260 ; 266) comportant une source, une grille et un drain ;

    dans lequel les sources des premier et deuxième transistors MOSFET (264, 260 ; 270, 266) sont couplées de manière sélectionnable à certaines de la première ou de la deuxième pluralité de sources de courant constant (230, 232 ; 242, 240) ;

    dans lequel le drain du premier transistor MOSFET (264 ; 270) est la sortie de courant positive de l'étage de transconductance (260, 262, 264 ; 266, 268, 270) respectif ; et

    dans lequel le drain du deuxième transistor MOSFET (260 ; 266) est la sortie de courant négative de l'étage de transconductance (260, 262, 264 ; 266, 268, 270) respectif.


     
    3. Amplificateur d'instrumentation selon la revendication 2, dans lequel les premier et deuxième transistors MOSFET (264, 260 ; 270, 266) sont des transistors MOSFET à canal P.
     
    4. Amplificateur d'instrumentation selon la revendication 2, dans lequel les premier et deuxième transistors MOSFET (264, 260 ; 270, 266) sont des transistors MOSFET à canal N.
     
    5. Amplificateur d'instrumentation selon l'une des revendications précédentes, dans lequel les première, deuxième, troisième et quatrième pluralités de commutateurs comprennent des transistors.
     
    6. Amplificateur d'instrumentation selon l'une des revendications précédentes, dans lequel l'amplificateur d'instrumentation (102) est fabriqué sur une puce de circuit intégré.
     
    7. Amplificateur d'instrumentation selon l'une des revendications 1 à 5 précédentes, dans lequel une pluralité d'amplificateurs d'instrumentation (102) sont fabriqués sur une puce de circuit intégré.
     
    8. Amplificateur d'instrumentation selon l'une des revendications précédentes, comprenant en outre un circuit d'auto-étalonnage pour étalonner le gain et le décalage de l'amplificateur d'instrumentation (102).
     
    9. Amplificateur d'instrumentation selon la revendication 8, dans lequel le circuit d'auto-étalonnage comprend :

    une référence de tension (354) fournissant une tension de référence ;

    un comparateur de tensions (352) comportant des première et deuxième entrées analogiques et une sortie numérique, la première entrée analogique étant couplée à une tension provenant de la sortie de l'amplificateur à transimpédance (108) et la deuxième entrée analogique étant couplée à la tension de référence provenant de la référence de tension (354), dans lequel, lorsque la tension sur la première entrée analogique est supérieure à la tension de référence sur la deuxième entrée analogique, la sortie numérique est à un premier niveau logique, et, lorsque la tension sur la première entrée analogique est inférieure ou égale à la tension de référence sur la deuxième entrée analogique, la sortie numérique est à un deuxième niveau logique ;

    un registre d'approximations successives (SAR) (506) comportant une entrée numérique couplée à la sortie numérique du comparateur de tensions (352) et des sorties couplées aux première, deuxième, troisième et quatrième pluralités de commutateurs (236, 238, 246, 248, 252, 254) ; et

    une logique d'étalonnage (504),

    dans lequel lorsque l'entrée positive du premier étage de transconductance (260, 262, 264) est couplée à la tension de référence (354), et que les premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) sont configurés pour obtenir un gain souhaité de l'amplificateur d'instrumentation (102), la logique d'étalonnage commande les première et deuxième pluralités de commutateurs (236, 238, 246, 248) pour coupler de manière sélectionnable certaines des première et deuxième pluralités de sources de courant constant (230, 232, 240, 242) de manière à étalonner le gain de l'amplificateur d'instrumentation (102), et

    dans lequel, lorsque les entrées positive et négative du premier étage de transconductance (260, 262, 264) sont couplées l'une avec l'autre et à une tension de référence (354), et que les entrées positive et négative du deuxième étage de transconductance (266, 268, 270) sont configurées pour obtenir un gain souhaité de l'amplificateur d'instrumentation (102), la logique d'étalonnage (504) commande les troisième et quatrième pluralités de commutateurs (252, 254) pour coupler de manière sélectionnable certains des troisième et quatrième pluralités de consommateurs de courant constant (234, 244) de manière à étalonner le décalage d'entrée de l'amplificateur d'instrumentation (102).


     
    10. Amplificateur d'instrumentation selon la revendication 9, comprenant en outre une pluralité de registres (510, 512, 514) couplés entre le SAR (506) et les première, deuxième, troisième et quatrième pluralités de commutateurs (236, 238, 246, 248, 252, 254), respectivement, pour mémoriser les valeurs d'auto-étalonnage provenant du SAR (506).
     
    11. Amplificateur d'instrumentation selon la revendication 10, comprenant en outre une vérification de parité (516) de la pluralité de registres (510, 512, 514).
     
    12. Procédé pour étalonner le gain et le décalage d'un amplificateur d'instrumentation en utilisant des sources et des consommateurs de courant constant, dans lequel l'amplificateur d'instrumentation (102) comprend des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) et un amplificateur à transimpédance (108), dans lequel les sorties des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) et l'entrée de l'amplificateur à transimpédance (108) sont couplées les unes aux autres, ledit procédé comprenant les étapes :

    d'ajustement du gain d'un amplificateur d'instrumentation (102) en couplant de manière sélectionnable certaines d'une pluralité de sources de courant constant (230, 232, 240, 242) aux premier et deuxième étages de transconductance (260, 264 ; 266, 270) de l'amplificateur d'instrumentation (102) ; et

    d'ajustement du décalage de l'amplificateur d'instrumentation (102) en couplant de manière sélectionnable certains d'une pluralité de consommateurs de courant constant (234, 244) aux sorties positives et négatives des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) de l'amplificateur d'instrumentation (102).


     
    13. Procédé selon la revendication 12, dans lequel l'étape d'ajustement du gain de l'amplificateur d'instrumentation (102) comprend les étapes :

    de couplage d'une entrée positive de l'amplificateur d'instrumentation (102) à un premier réseau de résistances de réglage de gain (112a, 114a) et d'une entrée négative de l'amplificateur d'instrumentation à un élément commun de source de puissance (374) ;

    de couplage d'une entrée de rétroaction (382) de l'amplificateur d'instrumentation (102) à un deuxième réseau de résistances de réglage de gain (112, 114) et d'une entrée de référence (380) de l'amplificateur d'instrumentation (102) à l'élément commun de source de puissance (374), dans lequel les premier et deuxième réseaux de résistances de réglage de gain (112, 114, 112a, 114a) ont des valeurs sensiblement identiques ;

    de comparaison d'une tension de sortie de l'amplificateur d'instrumentation (102) à une tension de référence (354) ; et

    de couplage de manière sélectionnable de certaines de la pluralité de sources de courant constant (230, 232, 240, 242) aux premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) de l'amplificateur d'instrumentation (102) jusqu'à ce que la tension de sortie de l'amplificateur d'instrumentation (102) soit sensiblement identique à la tension de référence (354).


     
    14. Procédé selon la revendication 12 ou 13, dans lequel l'étape d'ajustement du décalage de l'amplificateur d'instrumentation (102) comprend les étapes :

    de couplage des entrées positive et négative de l'amplificateur d'instrumentation (102) à une tension de référence (354) ;

    de couplage d'une entrée de rétroaction (382) de l'amplificateur d'instrumentation (102) à un réseau de résistances de réglage de gain (112, 114) et d'une entrée de référence (380) de l'amplificateur d'instrumentation (102) à la tension de référence (354) ;

    de comparaison d'une tension de sortie de l'amplificateur d'instrumentation (102) à la tension de référence (354) ; et

    de couplage de manière sélectionnable de certains de la pluralité de consommateurs de courant constant (234, 244) aux sorties positives et négatives des premier et deuxième étages de transconductance (260, 262, 264 ; 266, 268, 270) de l'amplificateur d'instrumentation (102) jusqu'à ce que la tension de sortie de l'amplificateur d'instrumentation (102) soit sensiblement identique à la tension de référence (354).


     
    15. Procédé selon l'une des revendications 12 à 14 précédentes, dans lequel l'étape d'ajustement du gain a lieu avant l'étape d'ajustement du décalage.
     




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    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description