UNIVERSAL-VOLTAGE DISCRETE INPUT CIRCUIT

Description

RELATED PATENT APPLICATION

TECHNICAL FIELD

[0001] The present invention relates generally to voltage input circuits for coupling to digital logic circuits, and more particularly, to a universal-voltage discrete input circuit capable of accepting a wide range of input voltages while drawing a low value of current.

BACKGROUND

[0002] Previous designs for discrete voltage input circuits were only capable of accepting inputs over a specific narrow range of voltage levels, and were inaccurate and unreliable over a desired operating temperature range. A different circuit configuration was required for each specific narrow range of voltage levels, and/or jumpers, switches, firmware, etc., was required to reconfigure the input circuit to meet the application voltage requirement.

[0003] Referring to Figure 1, depicted is a schematic diagram of a prior art voltage input circuit for coupling to a digital logic circuit. The circuit shown in Figure 1 allows a narrow range of input voltages to safely drive a logic input of a digital circuit. An input voltage is applied to a series connected first current limiting resistor 102 and zener diode 104. The zener diode 104 is selected to limit a second voltage to a series connected second current limiting resistor 106 and an input light emitting diode (LED) of an optocoupler 108.

[0004] For example, if the zener conduction voltage of the zener diode 104 is selected to be 5.7 volts and a current of 5 milliamperes (ma.) is desired to flow through the LED portion of the isolation circuit 108, a resistance value for the second current limiting resistor 106 may be calculated as follows: R106 = (5.7 volts - 0.7 volts)/5 ma, resulting in a resistance value of 1000 ohms for the second current limiting resistor 106. The input voltage must be greater than 5.7 volts for the zener diode to provide the full 5.7 volts to the second current limiting resistor 106, less input voltage than that will reduce the current through the LED of the optocoupler 108. When the current through the LED of the isolation circuit 108 is reduced significantly, the optocoupler 108 becomes unreliable in transferring the presence of an input voltage to the logic circuit.

[0005] As the input voltage increases, the current through the first current limiting resistor 102 and zener diode 104 will correspondingly increase. This is not desirable since the wattage of both the zener diode 104 and the first current limiting resistor 102 must be sized for a worst case maximum input voltage. Also the current load presented to the source of the input voltage increases. For example, at an input voltage of 10.7 volts and a current through the first current limiting resistor 102 of 10 ma., the resistance necessary for the first current limiting resistor will be 500 ohms. If the input voltage is at 105.7 volts, current flowing through the first current limiting resistor 102 will be 200 ma. and the current through the zener 104 will be 195 ma. At this current value, the first current limiting resistor 102 and the zener 104 must be rated to have a power dissipation of at least 20 watts. Also the input voltage source must be capable of supplying a 20 watt load. This is highly undesirable and therefore limits the range of input voltages that can be safely handled without having to change the value of the first current limiting resistor 102.

[0006] Operating temperature variations will also affect the characteristics of the aforementioned components such that proper operation at a low end voltage will vary with temperature. In addition, higher input voltages and operating temperatures may cause one or more of the aforementioned components to malfunction or fail.

[0007] US 2007/195558 relates to a power supply for AC/DC and DC/DC conversion; US 7161338 relates to a linear voltage regulator for providing an output voltage to a load; US5592071 relates to a synchronous regulator circuit including a transformer having a secondary inductor magnetically coupled to a primary inductor, where the secondary inductor is coupled to control a synchronous power switch; US5023767 relates to a conversion circuit with high efficiency for power supplies that change alternating current to direct current and vice versa, adjusting the voltage supplied automatically for the load; US7715216 relates to a powering circuit of an AC-DC converter, for converting a high AC input voltage into a low DC output voltage to provide a load voltage in a stable DC bias range; and US5909660 relates to a signal conditioning module for sensing multiform field signals and for providing isolated digital signals appropriate for a processing system.

SUMMARY

[0008] Therefore, what is needed is a voltage input circuit that accepts a much wider range of input voltages without increasing current drawn from the input voltage source, and has more stable thermal operating characteristics over a desired temperature range and over the entire range of input voltages. In accordance with the present invention, an apparatus and a method as set forth in claims 1 and 13 are provided. Further embodiments are inter alia disclosed in the dependent claims.

[0009] According to a specific example of this disclosure, an apparatus for controlling a low voltage digital circuit with a voltage source having a wide range of voltage values comprises: a depletion-mode field effect transistor (FET) having a drain, gate and source, wherein the drain thereof is adapted for coupling to the voltage source; an adjustable shunt regulator having an anode, cathode and reference input; a resistor network for providing a reference voltage to the reference input of the adjustable shunt regulator, wherein the reference voltage is representative of a current through the resistor network; and an isolation circuit having an isolated input and an isolated output; wherein the isolated input of the isolation circuit is coupled between the source of the depletion-mode FET and the resistor network, the cathode of the adjustable shunt regulator is coupled to the gate of the depletion-mode FET, and the anode of the adjustable shunt regulator and the resistor network are coupled to a common of the voltage source; whereby the adjustable shunt regulator causes the depletion-mode FET to maintain a substantially constant current drawn from the voltage source over a wide range of input voltages therefrom.

[0010] According to another specific example of this disclosure, an apparatus for controlling a low voltage digital circuit with a voltage source having a wide range of voltage values comprises: a full wave bridge rectifier coupled to a voltage source; a depletion-mode field effect transistor (FET) having a drain, gate and source, wherein the drain thereof is adapted for coupling to the full wave bridge rectifier; an adjustable shunt regulator having an anode, cathode and reference input; a resistor network for providing a reference voltage to the reference input of the adjustable shunt regulator, wherein the reference voltage is representative of a current through the resistor network; and an isolation circuit having an isolated input and an isolated output; wherein the isolated input of the isolation circuit is coupled between the source of the depletion-mode FET and the resistor network, the cathode of the adjustable shunt regulator is coupled to the gate of the depletion-mode FET, and the anode of the adjustable shunt regulator and the resistor network are coupled to the full wave bridge rectifier; whereby the adjustable shunt regulator causes the depletion-mode FET to maintain a substantially constant current drawn over a wide range of input voltages from the voltage source.

[0011] According to yet another specific example of this disclosure, a method of controlling a low voltage digital circuit with a voltage source having a wide range of voltage values comprises the steps of: providing a depletion-mode field effect transistor (FET) having a drain, gate and source, wherein the drain thereof is adapted for coupling to the voltage source; providing an adjustable shunt regulator having an anode, cathode and reference input; providing a reference voltage from a resistor network to the reference input of the adjustable shunt regulator, wherein the reference voltage represents a current through the resistor network; and providing an isolation circuit having an isolated input and an isolated output; coupling the isolated input of the isolation circuit between the source of the depletion-mode FET and the resistor network; coupling the cathode of the adjustable shunt regulator to the gate of the depletion-mode FET; coupling the anode of the adjustable shunt regulator and the resistor network to a common of the voltage source; and maintaining a substantially constant current drawn from the voltage source over a wide range of input voltages therefrom by controlling a gate voltage of the depletion-mode FET with the adjustable shunt regulator.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description, in conjunction with the accompanying drawings briefly described as follows.

Figure 1 illustrates a schematic diagram of a prior art voltage input circuit for coupling to a digital logic circuit;

Figure 2 illustrates a schematic diagram of a universal-voltage discrete input circuit, according to a specific example embodiment of this disclosure;

Figure 3 illustrates a schematic diagram of the universal-voltage discrete input circuit of Figure 2 with the addition of an input status indicator, according to another specific example embodiment of this disclosure; and

Figure 4 illustrates a more detailed schematic diagram of the universal-voltage discrete input circuit of Figure 2 showing input and output auxiliary circuits, and bypass and signal smoothing capacitors, according to the specific example embodiments of this disclosure.

DETAILED DESCRIPTION

[0013] Referring now to the drawings, details of example embodiments of the present invention are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.

[0014] Referring to Figure 2, depicted is a schematic diagram of a universal-voltage discrete input circuit, according to a specific example embodiment of this disclosure. The universal-voltage discrete input circuit, generally represented by the numeral 200, comprises a depletion-mode field effect transistor (FET) 210, an isolation circuit 108 (optocoupler shown for illustrative purposes), biasing resistors 212, 214 and 216, and a low-voltage, adjustable precision shunt regulator 218. The depletion-mode FET 210 is designed to allow current to flow even when there is no gate voltage present, therefore, current will flow from the drain to the source without any voltage on the gate, but can be controlled with a negative voltage applied to the gate of the FET 210 referenced to the source thereof (similar to a triode vacuum tube).

[0015] The isolation circuit 108 has an isolated input and an isolated output, and may be, for example but is not limited to, an optocoupler having a light emitting diode (LED) for the isolated input and a phototransistor for the isolated output, (e.g., Omron G3VM MOS FET relay, an electromechanical relay having a coil for the isolated input and a contact for the isolated output, a transformer coupled digital isolator (e.g., Analog Devices ADUM1402), etc. When sufficient current flows through the isolated input (e.g., LED portion) of the isolation circuit 108, e.g., from about 1 ma. to about 50 ma., the isolated output (e.g., transistor portion) thereof turns on and can drive a digital logic input circuit or other load to be isolated from the switched input voltage source. Isolation between the isolated input (e.g., LED portion) and the isolated output (e.g., transistor portion) of the isolation circuit 108 is very high, e.g., may be greater than 5000 volts DC.

[0016] Series connected resistors 214 and 216 are coupled between an input return of the isolation circuit 108 and a common node of the universal-voltage discrete input circuit 200, and form a voltage divider having a junction therebetween coupled to a reference input 220 of the adjustable precision shunt regulator 218. When current flows through the series connected resistors 214 and 216, a voltage is applied to the reference input 220 of the adjustable precision shunt regulator 218. This voltage may be adjusted by changing the value(s) of either or both of the series connected resistors 214 and 216. The adjustable precision shunt regulator 218 tries to keep a constant voltage across the sense resistor 214 by adjusting the gate voltage of the FET 210. As the gate voltage of the FET 210 is adjusted, the current through the FET 210 (drain to source) changes and the current through the sense resistor 214 changes as well. This action by the adjustable precision shunt regulator 218 provides a substantially constant current through the isolation circuit 108, guaranteeing that sufficient current, but not too much current, is available to turn on the transistor portion of the isolation circuit 108, regardless of input voltage or ambient temperature. In addition, and as an added benefit, input current required from the input voltage source remains at substantially the same current as that which flows through the isolation circuit 108. Resistor 212 is a high resistance value resistor used as a circuit return from the gate to the source of the FET 210 (similar to a grid bias resistor between a grid and a cathode of a vacuum tube triode amplifier).

[0017] The adjustable precision shunt regulator 218 may be, for example but is not limited to, a National Semiconductor LMV431 low-voltage (1.24 V) adjustable precision shunt regulator, and the depletion-mode FET 210 may be, for example but is not limited to, an IXYS high voltage MOSFET IXTP 01N100D having a maximum Vdss of 1000 volts DC and a maximum drain to source current of 100 ma. The input voltage range for operation of the universal-voltage discrete input circuit 200 may be from less than 7 volts to the maximum voltage rating of the depletion-mode FET 210, e.g., 1000 volts DC for the MOSFET IXTP 01N100D device. The current drawn from the input voltage source remains at a constant low value (substantially the same value as the current through the isolated input of the isolation circuit 108). Resistance values may be, for example but are not limited to, resistor 212 = 10,000 ohms, resistor 214 = 1000 ohms and resistor 216 = 430 to 910 ohms.

[0018] Referring to Figure 3, depicted is a schematic diagram of the universal-voltage discrete input circuit of Figure 2 with the addition of an input status indicator, according to another specific example embodiment of this disclosure. The universal-voltage discrete input circuit, generally represented by the numeral 200a, functions substantially the same way as the universal-voltage discrete input circuit 200 of Figure 2, discussed more fully hereinabove, with the addition of an input status indicator 319, e.g., an LED, relay coil, audible alarm, etc. Whenever a voltage input of at least, for example but not limited to, 7 volts is applied the input status indicator 319 will actuate (e.g., light), indicating the presence of an input voltage. When there is substantially no input voltage present, the input status indicator 319 will be off (e.g., dark) and the isolated output of the isolation circuit 108 will be off (e.g., open - high resistance between a transistor emitter and collector thereof or relay contact). The input status indicator 319 is operational whether the logic circuit coupled to the isolated output side of the isolation circuit is active or not. This enables the apparatus shown in Figure 3 to be functional during installation and start-up activities regardless of whether the control/instrumentation side of the logic circuit is powered up or even yet installed. Resistor 326 may optionally be used to bypass current around the status indicator 319 so that more current may flow through the isolated input of the isolation circuit 108 without exceeding the current rating of the status indicator 319.

[0019] Referring to Figure 4, depicted is a more detailed schematic diagram of the universal-voltage discrete input circuit of Figure 2 showing input and output auxiliary circuits, and bypass and signal smoothing capacitors, according to the specific example embodiments of this disclosure. The universal-voltage discrete input circuit, generally represented by the numeral 200b, functions substantially the same way as the universal-voltage discrete input circuit 200 of Figure 2, discussed more fully hereinabove, with the addition of a full wave bridge rectifier 420 that allows the voltage input to be AC or +/-DC, a surge/transient suppressor 422, a pull-up resistor 426 and a current bypass (shunt) resistor 424. Capacitors, C, are shown throughout this circuit implementation and may be used for noise/transient suppression, switching stability and AC waveform smoothing. One having ordinary skill in analog electronic circuit design and the benefit of this disclosure would readily understand the purposes and appropriate values for the capacitors shown in Figure 4.

[0020] The pull-up resistor 426 on the isolated output of the isolation circuit 108 is used to generate a discrete digital logic signal (on or off). When current is flowing through the isolated input of the isolation circuit 108, the isolated output thereof is conducting (on) and a logic LOW is generated. When no current is flowing through the isolated input of the isolation circuit 108, the isolated output thereof is not conducting (off) and a logic high to Vcc is generated through the pull-up resistor 426. Zero-crossing glitches of low-amplitude AC signals may be filtered out with a suitable capacitor across the isolated output of the isolation circuit 108, as shown in Figure 4. The digital logic circuit input is isolated from the input voltage signal up to the voltage isolation rating of the isolation circuit 108, e.g., 5000 volts DC. The shunt resistor 424 may be selected to allow more current to pass through the depletion-mode FET 210 then through the isolated input of the isolation circuit 108.

[0021] Although specific example embodiments of the invention have been described above in detail, the description is merely for purposes of illustration. It should be appreciated, therefore, that many aspects of the invention were described above by way of example only and are not intended as required or essential elements of the invention unless explicitly stated otherwise.

Claims

1. An apparatus (200, 200a, 200b) for controlling a low voltage digital circuit with a voltage source having a wide range of voltage values, said apparatus comprising:

an adjustable shunt regulator (218) having an anode, a cathode a reference input (220);

a resistor network (214, 216) for providing a reference voltage to the reference input (220) of the adjustable shunt regulator (218), wherein the reference voltage is representative of a current through the resistor network (214, 216);

characterized in that the apparatus (200, 200a, 200b) further comprises:

a depletion-mode field effect transistor, FET, (210) having a drain, a gate and a source, wherein the drain thereof is adapted to be coupled to the voltage source;

an isolation circuit (108) having an isolated input and an isolated output; wherein

the isolated input of the isolation circuit (108) is coupled between the source of the depletion-mode FET (210) and the resistor network (214, 216),

the cathode of the adjustable shunt regulator (218) is coupled to the gate of the depletion-mode FET (210),

the anode of the adjustable shunt regulator (218) and the resistor network (214, 216) are configured to be coupled to a common node of the voltage source,

the resistor network comprises a pair of series connected resistors (214, 216) coupled between an input return of the isolation circuit (108) and the common node, the pair of series connected resistors (214, 216) forming a voltage divider

having a junction therebetween coupled to the reference input (220) of the adjustable shunt regulator (218), and
the resistor network comprising a third resistor (212) having a high resistance value, the third resistor (212)

connected between the gate of the depletion-mode FET (210) and the input return of the isolation circuit (108);

whereby the adjustable shunt regulator (218) is configured to cause the depletion-mode FET

(210) to maintain a substantially constant current drawn from the voltage source over a wide range of input voltages therefrom.

2. The apparatus according to claim 1, further comprising a full wave bridge rectifier (420) having an input configured to be coupled to the voltage source, the full wave bridge rectifier (420) further having an output coupled between the drain of the depletion-mode FET (210) and the anode of the adjustable shunt regulator (218), wherein the input voltage from the voltage source is one of alternating current, AC, positive direct current, DC, and negative DC.

3. The apparatus according to claim 1, wherein the wide input voltage range of the voltage source is from less than about seven (7) volts to about 1000 volts.

4. The apparatus according to claim 1, further comprising an indication device (319) for indicating when a voltage from the voltage source is present at the drain of the depletion-mode FET.

5. The apparatus according to claim 4, wherein the indication device (319) is a light emitting diode, LED.

6. The apparatus according to claim 1, wherein the isolation circuit (108) is an optocoupler having a light emitting diode, LED, for the isolated input and a phototransistor for the isolated output.

7. The apparatus according to claim 6, further comprising a pull-up resistor (426) configured to be coupled from the isolated output of the isolation circuit (108) to a digital circuit voltage, wherein the pull-up resistor (426) is used to generate a logic high when the phototransistor is off.

8. The apparatus according to claim 1, wherein the isolation circuit (108) is an electromechanical relay having a coil for the isolated input and a contact for the isolated output.

9. The apparatus according to claim 1, wherein the isolation circuit (108) is a transformer coupled digital isolator.

10. The apparatus according to claim 1, wherein when the input voltage from the voltage source is of a sufficient value the isolated output of the isolation circuit (108) is configured to turn on, otherwise the isolated output is off.

11. The apparatus according to claim 2, further comprising an indication device (319) for indicating when a voltage from the full wave bridge rectifier (420) is present at the drain of the depletion-mode FET (210).

12. The apparatus according to claim 11, wherein the indication device (319) is a light emitting diode, LED.

13. A method of controlling a low voltage digital circuit with a voltage having a wide range of voltage values, said method comprising the steps of:
providing an adjustable shunt regulator having an anode, a cathode and a reference input;
characterized by:

providing a depletion-mode field effect transistor, FET, having a drain, a gate and a source, wherein the drain thereof is adapted for coupling to the voltage source;

providing an isolation circuit having an isolated input and an isolated output;

providing a resistor network (214, 216) comprising a pair of series connected resistors (214, 216) and a third resistor (212), the third resistor (212) having a high resistance value,

coupling the pair of series connected resistors (214, 216) between an input return of the isolation circuit (108) and a common node of the voltage source, the pair of series connected resistors (214, 216) forming a voltage divider having a junction there between coupled to the reference input (220) of the adjustable shunt regulator (218), wherein the reference voltage represents a current through the resistor network;

coupling the third resistor (212) between the gate of the depletion-mode FET (210) and the input return of the isolation circuit (108);

coupling the isolated input of the isolation circuit between the source of the depletion-mode FET and the resistor network;

coupling the cathode of the adjustable shunt regulator to the gate of the depletion-mode FET;

coupling the anode of the adjustable shunt regulator to the common node of the voltage source; and

maintaining a substantially constant current drawn from the voltage source over a wide range of input voltages there from by controlling a gate voltage of the depletion- mode FET with the adjustable shunt regulator.

Ansprüche

1. Vorrichtung (200, 200a, 200b) zum Steuern einer digitalen Niederspannungsschaltung mit einer Spannungsquelle, die einen breiten Bereich von Spannungswerten aufweist, wobei die Vorrichtung umfasst:

einen einstellbaren Nebenschlussregler (218), der eine Anode, eine Kathode und einen Referenzeingang (220) aufweist;

ein Widerstandsnetzwerk (214, 216) zum Bereitstellen einer Referenzspannung an den Referenzeingang (220) des einstellbaren Nebenschlussreglers (218), wobei die Referenzspannung repräsentativ für einen Strom durch das Widerstandsnetzwerk (214, 216) ist; dadurch gekennzeichnet, dass die Vorrichtung (200, 200a, 200b) ferner umfasst:

einen Verarmungsmodus-Feldeffekttransistor, FET, (210), der einen Drain, ein Gate und eine Source aufweist, wobei dessen Drain ausgelegt ist, um mit der Spannungsquelle verbunden zu werden;

eine Schaltung (108) zur galvanischen Trennung, die einen galvanisch getrennten Eingang und einen galvanisch getrennten Ausgang aufweist; wobei

der galvanisch getrennte Eingang der Schaltung (108) zur galvanischen Trennung zwischen die Source des Verarmungsmodus-FET (210) und das Widerstandsnetzwerk (214, 216) geschaltet ist,

die Kathode des einstellbaren Nebenschlussreglers (218) mit dem Gate des Verarmungsmodus-FET (210) verbunden ist,

die Anode des einstellbaren Nebenschlussreglers (218) und das Widerstandsnetzwerk (214, 216) konfiguriert sind, um mit einem gemeinsamen Knoten der Spannungsquelle verbunden zu werden,

das Widerstandsnetzwerk ein Paar von in Reihe geschalteten Widerständen (214, 216) umfasst, die zwischen eine Eingangsrückführung der Schaltung (108) zur galvanischen Trennung und den gemeinsamen Knoten geschaltet sind, wobei das Paar von in Reihe geschalteten Widerständen (214, 216) einen Spannungsteiler bildet, der einen Abzweig dazwischen aufweist, der mit dem Referenzeingang (220) des einstellbaren Nebenschlussreglers (218) verbunden ist, und

wobei das Widerstandsnetzwerk einen dritten Widerstand (212) umfasst, der einen hohen Widerstandswert aufweist, wobei der dritte Widerstand (212) zwischen das Gate des Verarmungsmodus-FET (210) und die Eingangsrückkopplung der Schaltung (108) zur galvanischen Trennung geschaltet ist;

wodurch der einstellbare Nebenschlussregler (218) konfiguriert ist, um den Verarmungsmodus-FET (210) zu veranlassen, einen im Wesentlichen konstanten Strom, der aus der Spannungsquelle entnommen wird, über einen breiten Bereich von Eingangsspannungen davon aufrechtzuerhalten.

2. Vorrichtung nach Anspruch 1, ferner umfassend einen Vollwellenbrückengleichrichter (420), der einen Eingang aufweist, der konfiguriert ist, um mit der Spannungsquelle verbunden zu werden, wobei der Vollwellenbrückengleichrichter (420) ferner einen Ausgang aufweist, der zwischen den Drain des Verarmungsmodus-FET (210) und die Anode des einstellbaren Nebenschlussreglers (218) geschaltet ist, wobei die Eingangsspannung von der Spannungsquelle eines aus Wechselstrom, AC, positivem Gleichstrom, DC, und negativem DC ist.

3. Vorrichtung nach Anspruch 1, wobei der breite Eingangsspannungsbereich der Spannungsquelle von weniger als etwa sieben (7) Volt bis etwa 1000 Volt beträgt.

4. Vorrichtung nach Anspruch 1, ferner umfassend eine Anzeigevorrichtung (319) zum Anzeigen, wann eine Spannung von der Spannungsquelle an dem Drain des Verarmungsmodus-FET vorliegt.

5. Vorrichtung nach Anspruch 4, wobei die Anzeigevorrichtung (319) eine Leuchtdiode, LED, ist.

6. Vorrichtung nach Anspruch 1, wobei die Schaltung (108) zur galvanischen Trennung ein Optokoppler ist, der eine Leuchtdiode, LED, für den galvanisch getrennten Eingang und einen Fototransistor für den galvanisch getrennten Ausgang aufweist.

7. Vorrichtung nach Anspruch 6, ferner umfassend einen Pull-up-Widerstand (426), der konfiguriert ist, um von dem galvanisch getrennten Ausgang der Schaltung (108) zur galvanischen Trennung zu einer Spannung einer Digitalschaltung verbunden zu werden, wobei der Pull-up-Widerstand (426) verwendet wird, um ein Logik-High zu erzeugen, wenn der Fototransistor ausgeschaltet ist.

8. Vorrichtung nach Anspruch 1, wobei die Schaltung (108) zur galvanischen Trennung ein elektromechanisches Relais ist, das eine Spule für den galvanisch getrennten Eingang und einen Kontakt für den galvanisch getrennten Ausgang aufweist.

9. Vorrichtung nach Anspruch 1, wobei die Schaltung (108) zur galvanischen Trennung ein transformatorgekoppelter digitaler Trenner ist.

10. Vorrichtung nach Anspruch 1, wobei, wenn die Eingangsspannung von der Spannungsquelle einen ausreichenden Wert aufweist, der galvanisch getrennte Ausgang der Schaltung (108) zur galvanischen Trennung konfiguriert ist, um eingeschaltet zu werden, andernfalls ist der galvanisch getrennte Ausgang ausgeschaltet.

11. Vorrichtung nach Anspruch 2, ferner umfassend eine Anzeigevorrichtung (319) zum Anzeigen, wann eine Spannung von dem Vollwellenbrückengleichrichter (420) an dem Drain des Verarmungsmodus-FET (210) vorliegt.

12. Vorrichtung nach Anspruch 11, wobei die Anzeigevorrichtung (319) eine Leuchtdiode, LED, ist.

13. Verfahren zum Steuern einer digitalen Niederspannungsschaltung mit einer Spannung, die einen breiten Bereich von Spannungswerten aufweist, wobei das Verfahren die Schritte umfasst:

Bereitstellen einen einstellbaren Nebenschlussregler, der eine Anode, eine Kathode und einen Referenzeingang aufweist;

gekennzeichnet durch:

Bereitstellen eines Verarmungsmodus-Feldeffekttransistors, FET, der einen Drain, ein Gate und eine Source aufweist, wobei dessen Drain ausgelegt ist, um mit der Spannungsquelle verbunden zu werden;

Bereitstellen einer Schaltung zur galvanischen Trennung, die einen galvanisch getrennten Eingang und einen galvanisch getrennten Ausgang aufweist;

Bereitstellen eines Widerstandsnetzwerks (214, 216), das ein Paar von in Reihe geschalteten Widerständen (214, 216) und einen dritten Widerstand (212) aufweist, wobei der dritte Widerstand (212) einen hohen Widerstandswert aufweist,

Verbinden des Paares von in Reihe geschalteten Widerständen (214, 216) zwischen einer Eingangsrückführung der Schaltung (108) zur galvanischen Trennung und einen gemeinsamen Knoten der Spannungsquelle, wobei das Paar von in Reihe geschalteten Widerständen (214, 216) einen Spannungsteiler bildet, der einen Abzweig dazwischen aufweist, der mit dem Referenzeingang (220) des einstellbaren Nebenschlussreglers (218) verbunden ist, wobei die Referenzspannung einen Strom durch das Widerstandsnetzwerk darstellt;

Verbinden des dritten Widerstands (212) mit dem Gate des Verarmungsmodus-FET (210) und der Eingangsrückkopplung der Schaltung (108) zur galvanischen Trennung;

Verbinden des galvanisch getrennten Eingangs der Schaltung zur galvanischen Trennung zwischen der Source des Verarmungsmodus-FET und dem Widerstandsnetzwerk;

Verbinden der Kathode des einstellbaren Nebenschlussreglers mit dem Gate des Verarmungsmodus-FET;

Verbinden der Anode des einstellbaren Nebenschlussreglers mit dem gemeinsamen Knoten der Spannungsquelle; und

Aufrechterhalten eines im Wesentlichen konstanten Stroms, der aus der Spannungsquelle über einen breiten Bereich von Eingangsspannungen entnommen wird, durch Steuern einer Gate-Spannung des Verarmungsmodus-FET mit dem einstellbaren Nebenschlussregler.

Revendications

1. Appareil (200, 200a, 200b) pour commander un circuit numérique basse tension avec une source de tension ayant une plage étendue de valeurs de tension, ledit appareil comprenant :

un régulateur shunt ajustable (218) ayant une anode, une cathode et une entrée de référence (220) ;

un réseau de résistances (214, 216) pour fournir une tension de référence à l'entrée de référence (220) du régulateur shunt ajustable (218), dans lequel la tension de référence est représentative d'un courant à travers le réseau de résistances (214, 216) ;

caractérisé en ce que l'appareil (200, 200a, 200b) comprend en outre :

un transistor à effet de champ, FET, à mode d'appauvrissement (210) ayant un drain, une grille et une source, dans lequel le drain de celui-ci est conçu pour être couplé à la source de tension ;

un circuit d'isolation (108) ayant une entrée isolée et une sortie isolée ; dans lequel

l'entrée isolée du circuit d'isolation (108) est couplée entre la source du FET à mode d'appauvrissement (210) et le réseau de résistances (214, 216),

la cathode du régulateur shunt ajustable (218) est couplée à la grille du FET à mode d'appauvrissement (210),

l'anode du régulateur shunt ajustable (218) et le réseau de résistances (214, 216) sont configurés pour être couplés à un nœud commun de la source de tension,

le réseau de résistances comprend une paire de résistances connectées en série (214, 216) couplées entre un retour d'entrée du circuit d'isolation (108) et le nœud commun, la paire de résistances connectées en série (214, 216) formant un diviseur de tension ayant une jonction entre elles couplée à l'entrée de référence (220) du régulateur shunt ajustable (218), et le réseau de résistances comprenant une troisième résistance (212) ayant une valeur de résistance élevée, la troisième résistance (212) connectée entre la grille du FET à mode d'appauvrissement (210) et le retour d'entrée du circuit d'isolation (108) ;

moyennant quoi le régulateur shunt ajustable (218) est configuré pour amener le FET à mode d'appauvrissement (210) à maintenir un courant sensiblement constant tiré de la source de tension sur une plage étendue de tensions d'entrée à partir de celle-ci.

2. Appareil selon la revendication 1, comprenant en outre un redresseur en pont à double alternance (420) ayant une entrée configurée pour être couplée à la source de tension, le redresseur en pont à double alternance (420) ayant en outre une sortie couplée entre le drain du FET à mode d'appauvrissement (210) et l'anode du régulateur shunt ajustable (218), dans lequel la tension d'entrée provenant de la source de tension est un parmi un courant alternatif, CA, un courant continu, CC, positif, et un CC négatif.

3. Appareil selon la revendication 1, dans lequel la plage étendue de tension d'entrée de la source de tension va de moins d'environ sept (7) volts à environ 1000 volts.

4. Appareil selon la revendication 1, comprenant en outre un dispositif d'indication (319) pour indiquer lorsqu'une tension provenant de la source de tension est présente au niveau du drain du FET à mode d'appauvrissement.

5. Appareil selon la revendication 4, dans lequel le dispositif d'indication (319) est une diode électroluminescente, DEL.

6. Appareil selon la revendication 1, dans lequel le circuit d'isolation (108) est un optocoupleur ayant une diode électroluminescente, DEL, pour l'entrée isolée et un phototransistor pour la sortie isolée.

7. Appareil selon la revendication 6, comprenant en outre une résistance d'excursion haute (426) configurée pour être couplée de la sortie isolée du circuit d'isolation (108) jusqu'à une tension de circuit numérique, dans lequel la résistance d'excursion haute (426) est utilisée pour générer une logique élevée lorsque le phototransistor est désactivé.

8. Appareil selon la revendication 1, dans lequel le circuit d'isolation (108) est un relais électromécanique ayant une bobine pour l'entrée isolée et un contact pour la sortie isolée.

9. Appareil selon la revendication 1, dans lequel le circuit d'isolation (108) est un isolateur numérique couplé à un transformateur.

10. Appareil selon la revendication 1, dans lequel lorsque la tension d'entrée provenant de la source de tension est d'une valeur suffisante la sortie isolée du circuit d'isolation (108) est configurée pour s'activer, autrement la sortie isolée est désactivée.

11. Appareil selon la revendication 2, comprenant en outre un dispositif d'indication (319) pour indiquer lorsqu'une tension provenant du redresseur en pont à double alternance (420) est présente au niveau du drain du FET à mode d'appauvrissement (210).

12. Appareil selon la revendication 11, dans lequel le dispositif d'indication (319) est une diode électroluminescente, DEL.

13. Procédé de commande d'un circuit numérique basse tension avec une tension ayant une plage étendue de valeurs de tension, ledit procédé comprenant les étapes consistant à :

fournir un régulateur shunt ajustable ayant une anode, une cathode et une entrée de référence ;

caractérisé par :

la fourniture d'un transistor à effet de champ, FET, à mode d'appauvrissement, ayant un drain, une grille et une source, dans lequel le drain de celui-ci est conçu pour un couplage à la source de tension ;

la fourniture d'un circuit d'isolation ayant une entrée isolée et une sortie isolée ;

la fourniture d'un réseau de résistances (214, 216) comprenant une paire de résistances connectées en série (214, 216) et une troisième résistance (212), la troisième résistance (212) ayant une valeur de résistance élevée,

le couplage de la paire de résistances connectées en série (214, 216) entre un retour d'entrée du circuit d'isolation (108) et un nœud commun de la source de tension, la paire de résistances connectées en série (214, 216) formant un diviseur de tension ayant une jonction entre elles couplée à l'entrée de référence (220) du régulateur shunt ajustable (218), dans lequel la tension de référence représente un courant à travers le réseau de résistances ;

le couplage de la troisième résistance (212) entre la grille du FET à mode d'appauvrissement (210) et le retour d'entrée du circuit d'isolation (108) ;

le couplage de l'entrée isolée du circuit d'isolation entre la source du FET à mode d'appauvrissement et le réseau de résistances ;

le couplage de la cathode du régulateur shunt ajustable à la grille du FET à mode d'appauvrissement ;

le couplage de l'anode du régulateur shunt ajustable au nœud commun de la source de tension ; et

le maintien d'un courant sensiblement constant tiré de la source de tension sur une plage étendue de tensions d'entrée à partir de celle-ci en commandant une tension de grille du FET à mode d'appauvrissement avec le régulateur shunt ajustable.

Drawing