(19)
(11)EP 2 629 322 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
03.10.2018 Bulletin 2018/40

(21)Application number: 13155575.7

(22)Date of filing:  18.02.2013
(51)Int. Cl.: 
H01L 21/304  (2006.01)
H01L 29/66  (2006.01)
H01L 21/225  (2006.01)

(54)

Power device manufacture on the recessed side of a thinned wafer

Leistungsvorrichtungshersteller auf der ausgesparten Seite eines ausgedünnten Wafers

Fabrication de dispositif de puissance sur la face en retrait d'une plaquette amincie


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 20.02.2012 US 201213400569

(43)Date of publication of application:
21.08.2013 Bulletin 2013/34

(73)Proprietor: IXYS, LLC
Milpitas CA 95035 (US)

(72)Inventors:
  • Wisotzki, Elmar
    64285 Darmstadt (DE)
  • Ingram, Peter
    69502 Hemsbach (DE)

(74)Representative: Winter, Brandl, Fürniss, Hübner, Röss, Kaiser, Polte - Partnerschaft mbB 
Patent- und Rechtsanwaltskanzlei Alois-Steinecker-Strasse 22
85354 Freising
85354 Freising (DE)


(56)References cited: : 
WO-A1-2010/140666
US-A1- 2009 102 020
US-A1- 2008 090 391
US-A1- 2011 260 296
  
      
    Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


    Description


    [0001] The described embodiments relate to the manufacture of semiconductor devices on thinned wafers.

    [0002] Vertical power devices, such as power field effect transistors and insulated gate bipolar transistors and power diodes, are sometimes manufactured on thinned wafers. In one exemplary manufacturing process, the front side of an ordinary monocrystalline silicon wafer of uniform thickness undergoes semiconductor fabrication processing such that the device sides of the power devices are formed into the front side of the wafer. One or more metallization layers are generally formed on the front side of the wafer to serve as front side electrodes of the power devices. In the case of a power field effect transistor or an insulated gate bipolar transistor, the control electrode is on the front side of the wafer. In the case of a power diode, the anode is on the front side of the wafer.

    [0003] After this device formation has occurred, including all diffusion processing steps involved in the formation of the devices, the wafer is flipped over and a central portion of the back side of the wafer is thinned in what is often referred to as the Taiko grinding process. The outer peripheral rim portion of the back side of the wafer is, however, not thinned. As a result, a thicker peripheral edge support portion of the wafer is left surrounding a thinner central portion of the wafer. The thicker peripheral edge support portion provides mechanical stiffening such that the thinner central portion can be handled without cracking of the wafer. The thicker peripheral edge support portion also reduces wafer warpage in later processing steps.

    [0004] After back side grinding, a back side metallization layer is formed on the thinner central portion of the back side of the wafer. This metallization forms electrodes on the back sides of the power devices. The peripheral edge support portion of the wafer is then cut off, and the thinner central portion of the wafer is diced to form individual power device dice.

    [0005] In such a vertical power device die, on-state power loss generally occurs in the bulk of the device when current flows vertically from one side of the die, through the bulk of the device, and to the other side of the die. Reducing the resistance through the bulk of the die reduces on-state power loss. Accordingly, it is normally the goal of the device design engineer to reduce wafer thickness as much as possible as long as the required breakdown voltage of the power device is maintained. Vertical power devices are made in commercial processes on five inch wafers with suitable yields where the thin central portions of the Taiko wafers are as thin as about 200 microns.

    [0006] Document WO 2010/140666 A1 describes a semiconductor substrate having a semiconductor device formable region, wherein a reinforcing section which is thicker than the semiconductor device formable region and has a top portion having a flat surface is formed on the outer circumferential portion of the semiconductor substrate, and the inner side surface, which connects the top portion of the reinforcing section and the semiconductor device formable region has a cross-section shape wherein the inner diameter is reduced toward the semiconductor device formable region.

    [0007] Document US 2008/090391 A1 describes a method for manufacturing a semiconductor device from a semiconductor wafer having a first major surface, a recess provided inside a periphery on opposite side of the first major surface and surrounded by the periphery, and a second major surface provided at bottom of the recess. The method comprises: fitting into the recess a doping mask having selectively formed openings to selectively cover the second major surface with the doping mask; and selectively introducing dopant into the second major surface.

    [0008] Document US 2011/260296 A1 describes a semiconductor wafer with a thinned central portion, which has a first side and a second side and at least one reinforcement structure for increasing the radial bending resistance of the semiconductor wafer. The reinforcement structure provides at least one passage for a fluid flow between an inner face of said one reinforcement structure towards an outer face of the reinforcement structure. The passages are manufactured in a z-direction coming from above the semiconductor wafer in a direction which is essentially perpendicular to the surface, e.g. to the first side, of the semiconductor wafer.

    [0009] The invention is defined by the features of independent claim 1. The dependent claims are directed to preferred embodiments of the invention.

    [0010] According to a first aspect of the present invention there is provided a method as defined in claim 1.

    [0011] The one of the semiconductor devices may be a vertical power device taken from the group consisting of: a power diode, and a power bipolar transistor.

    [0012] The first side of the thinner central portion may have a planar surface, wherein the planar surface may have a disc-shape with a substantially circular circumference, and wherein the planar surface may be more than three inches wide.

    [0013] The second side of the wafer opposite the first side may extend substantially entirely in a plane.

    [0014] The obtaining of the wafer in (a) may be accomplished by an action taken from the group consisting of: purchasing the thinned wafer, and manufacturing the thinned wafer.

    [0015] The glassivation layer may be at least ten microns thick.

    [0016] Step (e) may involve removing the thicker peripheral edge support portion and dicing the thinner central portion.

    [0017] The thicker peripheral edge support portion may have a plurality of radially extending slits.

    [0018] The thinner central portion of the wafer may be not greater than two hundred microns thick.

    [0019] The thicker peripheral edge support portion may have a cylindrical sidewall.

    [0020] The method may further comprise: (c) forming a cathode diffusion region into the thinner central portion.

    [0021] The method may further comprise: (g) forming a cathode metal electrode over the cathode diffusion region.

    [0022] The method may further comprise: (e) forming an anode metal electrode on the second side of the wafer.

    [0023] In one example, a first commercial entity manufactures a thinned wafer, and a second commercial entity obtains the thinned wafer and performs subsequent semiconductor fabrication processing on the wafer to manufacture the vertical power devices. The thinned wafer has a recess formed into a first side of the wafer such that a thinned central portion of the wafer is surrounded by a thicker peripheral edge support portion, and such that a second side of the wafer is substantially entirely planar. All high temperature diffusion steps involved in the manufacture of the vertical power devices are performed after thinning of the central portions of the thinned wafer. Formation of the device sides of the vertical power devices on the first side of the central portion of the wafer allows the planar second side of the wafer to lie on a supporting planar surface during most of the semiconductor processing steps, thereby reducing the likelihood of wafer breakage and allowing the thickness of the thin central portion to be made thinner while maintaining acceptable yield. The thinner central portion is made to have a thickness not greater than 200 microns, and in one specific example the thickness of the thinner central portion is 175 microns. The reduced thickness of the thin central portion reduces on-state resistance through the vertical power devices and thereby reduces on-state power losses in the power devices.

    [0024] Further details and embodiments and techniques are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.

    [0025] The accompanying drawings, where like numerals indicate like components, illustrate embodiments of the invention.

    FIGS. 1-4 set forth a problem that has been recognized with a prior art method making of vertical power devices.

    FIGS. 5A and 5B are diagrams of a starting wafer used in a method in accordance with one novel aspect.

    FIG. 6 is a top-down diagram that shows how a recess is formed into a first side of the starting wafer of FIGS. 5A and 5B, thereby forming a so-called Taiko wafer.

    FIG. 7 is a side-view diagram of the grinding process illustrated in FIG. 6.

    FIGS. 8A and 8B are diagrams of an etching step used in manufacturing the Taiko wafer of FIG. 6.

    FIGS. 9A and 9B are diagrams of the completed Taiko wafer.

    FIGS. 10A and 10B are diagrams that illustrate the forming of a photoresist mask used in forming isolation zones from the back side into the thin central portion of the Taiko wafer.

    FIGS. 11A and 11B are diagrams that illustrate diffusion occurring through the diffusion mask of FIGS. 10A and 10B.

    FIGS. 12A and 12B are diagrams that illustrate the removal of the diffusion mask of FIGS. 10A and 10B.

    FIGS. 13A and 13B are diagrams that illustrate the formation of an anode diffusion region into the front side of the wafer.

    FIGS. 14A and 14B are diagrams that illustrate the formation of cathode regions into the back side of the thin central portion of the wafer.

    FIGS. 15A and 15B are diagrams that illustrate the deposition of a liquid onto the back side of the thin central portion of the wafer, where the liquid includes a suspension of glass particles.

    FIGS. 16A and 16B are diagrams that illustrate the evaporation of the liquid of the liquid deposited in FIGS. 15A and 15B.

    FIGS. 17A and 17B are diagrams that illustrate the melting of the glass particles of FIGS. 16A and 16B to form a glass layer on the back side of the thin central portion of the wafer.

    FIGS. 18A and 18B are diagrams that illustrate the etching of windows into the glass formed in FIGS. 17A and 17B.

    FIGS. 19A and 19B are diagrams that illustrate the formation of cathode metal on the back side of the thin central portion of the wafer.

    FIGS. 20A and 20B are diagrams that illustrate the formation of anode metal on the front side of the thin central portion of the wafer.

    FIG. 21 is a simplified cross-sectional diagram of one of the power device dice formed by dicing the structure of FIGS. 20A and 20B.

    FIG. 22 is a flowchart of a method 100 not in accordance with the invention.

    FIG. 23 is a flowchart of a method 200 in accordance with one novel aspect.



    [0026] Reference will now be made in detail to background examples and some embodiments of the invention, examples of which are illustrated in the accompanying drawings. In the description and claims below, when a first object is referred to as being disposed "over" or "on" a second object, it is to be understood that the first object can be directly on the second object, or an intervening object may be present between the first and second objects. Similarly, terms such as "front" and "back" are used herein to describe relative orientations between different parts of the structure being described, and it is to be understood that the overall structure being described can actually be oriented in any way in three-dimensional space.

    [0027] FIGS. 1-4 set forth a problem that has been recognized with a conventional method making of vertical power devices. A wafer 1 has a front side 2 and a back side 3. The wafer 1 undergoes front side processing as illustrated in the cross-sectional view of FIG. 1. The type of power device being manufactured is a power diode. All diffusion steps that will cause diffusion into the front side of the wafer are performed, and then front side metallization layers are formed. This front side metal is patterned to form the cathode electrodes 4 of the diodes. Next, the central portion 5 of the back side 3 of the wafer is thinned as illustrated in FIG. 2. Block 6 represents the grinding wheel used. The peripheral portion 7 of the wafer is not thinned but rather is left at its original thickness to serve a stiffening function. Next, back side metallization is performed. This back side metal is patterned to form the anode electrodes 8 of the diodes. The resulting wafer structure is shown in cross-section in FIG. 3. In later processing steps, the thinned wafer is often made to rest front side up on a surface 9 as illustrated in FIG. 4. If the wafer is thinned to be smaller than about 200 microns, then wafer breakage is seen to occur to such a degree that production yield decreases to unacceptably low levels. The minimum thickness of the thinned central portion of the wafer is limited to be about 200 microns.

    [0028] FIGS. 5A-21 are a sequence of diagrams that sets forth a method of manufacturing vertical power devices in accordance with one novel aspect. FIG. 5A is a cross-sectional diagram of a starting wafer 10 having a front side 12 and a back side 11. FIG. 5B is an enlarged view of the section of the wafer of FIG. 5A between lines 13 and 14. In the present example, wafer 10 is a wafer of monocrystalline silicon having a slight N-type phosphorous doping concentration. Wafer 10 is 500 microns thick, and has a diameter of 5 inches.

    [0029] Next, back side wafer thinning is performed. In the present example, Taiko grinding is employed to form a circular recess into the central portion of the back side 11 of wafer 10. A grinding wheel 17 is used. As a result of the formation of this recess, a thinner central portion 15 of the wafer is formed. A thicker peripheral edge support portion 16 of the original thickness of the starting wafer is left to surround the thinner central portion 15 of the wafer. In the present example, peripheral edge support portion 16 has a cylindrical inside wall 16A. The back side surface of the thinner central portion 15 is planar, has a circular periphery, and is more than three inches in diameter.

    [0030] FIG. 7 is a cross-sectional diagram of the thinned wafer. Thinner central portion 15 has a thickness less than 200 microns. In the present example, the thickness of thinner central portion 15 is 175 microns. Thicker peripheral edge support portion 16 has a thickness of 500 microns. The width of thicker peripheral edge support portion 16 is about 3 millimeters. Thicker peripheral edge support portion 16 in some cases has radial slits and is not a single contiguous ring structure, but rather is a ring structure made up of numerous ring sections with open radially extending slits between the ring sections. In the present example, the front side 12 of wafer 10 is unprocessed and remains entirely planar. In other examples, the front side of the wafer is not entirely planar, but rather the front side also has one or more recesses extending into the front side of the wafer.

    [0031] Next, an etching step is performed to remove grinding debris and to remove silicon on the surface of the thinner central portion 15 that was damaged during the Taiko grinding process. Dry etching involving a plasma is employed to make the thinner central portion 15 another 15 microns thinner. The result of this dry etching step is illustrated in FIG. 8A. FIG. 8B is an enlarged view of a section of the wafer of FIG. 5A between lines 13 and 14. Dry etching need not be used, but rather another suitable processing technique may be employed to remove damage from the Taiko grinding processor.

    [0032] FIGS. 9A and 9B show the finished thinned wafer wherein Fig. 9B specifically shows the central part of the wafer. This thinned wafer is sometimes referred to as a Taiko wafer. In one example, the processing steps illustrated in FIGS. 5A-9B are performed by a first commercial entity that makes the thinned wafer, and the thinned wafer of FIGS. 9A and 9B is then sold and supplied to a second commercial entity that then carries out the remaining steps illustrated in FIGS. 10A-21. The first entity may be a manufacturer of Taiko wafers such as illustrated in FIG. 9A and 9B. The second entity may be a semiconductor fabrication company that obtains wafers from the first entity, and that then performs semiconductor processing on the wafers to make finished semiconductor devices.

    [0033] As shown in FIGS. 10A and 10B, by standard semiconductor fabrication technology a layer of a diffusion mask is then formed over the thinner central portion 15 of the back side of the wafer, to form pattern 18. A ring of silicon around the periphery of what will become each power device is left exposed by the mask.

    [0034] Next, a P-type dopant (for example aluminum) is diffused through the openings in mask 18 to later form isolation zones as illustrated in FIGS. 11A and 11B. Reference numeral 19 identifies one such ring-shaped isolation zone. The isolation zone extends in a ring around what will become a power device.

    [0035] Mask 18 is then removed, leaving the structure illustrated in FIGS. 12A and 12B.

    [0036] Next, the wafer structure is flipped over and a P-type dopant (for example, boron) is diffused from the front side 12 of the wafer to form an anode diffusion region 20. Simultaneously with the diffusion of the P-type anode dopant into the wafer from the front side, the P-type dopants of the isolation zones diffuse deeper into the wafer from the back side. As illustrated in FIGS. 13A and 13B, the resulting isolation regions extend from the back side of the wafer and overlap with (extends into) the P-type anode diffusion region that extends from the front side. Reference numeral 21 identifies one such ring-shaped isolation region. The P-type anode region 20 need not extend laterally all the way out to the peripheral edge of the wafer. Photomasking steps are therefore involved in forming the anode region. These photomasking steps are not illustrated here.

    [0037] Next, additional photomasking and diffusion steps are performed to form N-type cathode diffusion regions. These N-type cathode diffusion regions extend into the back side of the wafer. Reference number 22 identifies one such cathode diffusion region. All diffusion steps involve high temperatures in excess of 1000 degrees Celsius. The resulting wafer structure 10 involving the cathode diffusion regions is shown in FIGS. 14A and 14B.

    [0038] Because the main blocking PN junction extends to the upper semiconductor surface, this PN junction needs protection from high humidity and contamination conditions. A glass passivation layer is therefore provided over the PN junction at the semiconductor surface. A layer 23 of a liquid having glass particles suspended in it is deposited onto the thinner central portion 15 of the back side of the wafer as illustrated in FIGS. 15A and 15B. Peripheral portion 16 forms a dam for the liquid material. A heated chuck 24 or other surface is then used to heat layer 23 homogeneously such that the liquid evaporates evenly, leaving an even thickness of glass particles distributed across the surface of thin central portion 15 as illustrated in FIGS. 16A and 16B. Even uniform heating of the wafer in this evaporation step is facilitated due to good contact between the planar front side 12 of the wafer and the corresponding planar top side of heated chuck 24.

    [0039] In another high temperature step illustrated in FIGS. 17A and 17B, the glass particles are melted at about 700 degrees Celsius, thereby forming a thick and dense glassivation layer 25 over the thin central portion of the wafer. The glassivation layer 25 is more than ten microns thick and in one specific example is 20 microns thick.

    [0040] Next, windows are etched into glass layer 25 as illustrated in FIGS. 18A and 18B. In the area of each power device, one such window exposes the area that will be covered with a cathode electrode. The photomasking steps involved in forming these windows are not represented in the drawings. Reference numeral 26 of FIGS. 18A and 18B identifies the window over the power device being formed between lines 13 and 14.

    [0041] Next, as illustrated in FIGS. 19A and 19B, back side metallization is deposited by physical vapor deposition or sputtering, and is patterned to form a cathode metal electrode for each power device being formed. Reference numeral 27 identifies the cathode metal electrode for the power device being formed between lines 13 and 14.

    [0042] Wafer structure 10 is then flipped over, and front side anode metallization 28 is deposited as illustrated in FIGS. 20A and 20B. Photomasking steps associated with forming the anode metallization 28 are not illustrated.

    [0043] The thicker peripheral edge support portion 16 is then cut off, and the remaining thinner central portion 15 is diced to form individual power device dice. Dicing can be performed by any suitable method, including saw cutting and pulsed laser cutting.

    [0044] FIG. 21 is an enlarged diagram of one of the resulting power device dice. The power device 29 is a power diode having a blocking voltage of 1700 volts.

    [0045] The method of FIGS. 5-21 is advantageous in that it reduces the number of processing steps in which the thinned wafer being processed is not laying front side 12 down on a supporting surface. In the steps illustrated in FIGS. 5-21, only the anode diffusion of FIGS. 13A and 13B and the anode metallization of FIGS. 20A and 20B occur with the front side 12 of the wafer 10 not laying face down on a supporting surface.

    [0046] FIG. 22 is a flowchart of a method 100 which is not covered by the present application. A thinned wafer is obtained (step 101), where the thinned wafer has a recess formed into a first side (the back side) of the wafer such that the wafer has a thinner central portion and a thicker peripheral edge support portion. A second side (the front side) of the wafer opposite the first side extends substantially entirely in a plane. In one example, the wafer of step 101 is wafer 10 illustrated in FIG. 9A. At the conclusion of step 101, no diffusion region extends from the first side (the back side) into the thinner central portion of the wafer. Next, after the formation of the recess that forms the thinner central portion, a plurality of doped regions is formed (step 102) from the first side (the back side) into the thinner central portion of the wafer. In one example, these doped regions are the doped regions 20, 21 and 22 of FIG. 14A. Further processing is then performed on the wafer (step 103) thereby forming a plurality of semiconductor devices. Each of the doped regions formed in step 102 is a part of a corresponding one of the semiconductor devices. In one example, the semiconductor devices are vertical power devices.

    [0047] FIG. 23 is a flowchart of a method 200 in accordance with one novel aspect. A plurality of thinned disc-shaped semiconductors wafers are formed (step 201). A recess is formed into a first side (the back side) of each of the wafers such that: 1) each wafer has a thinner central portion and a thicker peripheral edge support portion, 2) a second side (the front side) of each of the wafers extends substantially entirely in a plane, and 3) each wafer has no diffusion region that extends from the back side into the thinner central portion of the wafer. The manufacturing of step 201 is performed by a first commercial entity (for example, a Taiko wafer manufacturing company). After the manufacturing of step 201 by the first commercial entity, the wafers are sold (step 202) to a second commercial entity (for example, a semiconductor fabrication house) that then processes the wafers to form vertical power devices from the wafers according to the claims.


    Claims

    1. A method of manufacturing a semiconductor device, comprising the following steps:

    (a) obtaining a thinned disc-shaped semiconductor wafer (10), wherein a recess extends into a first side (11) of the wafer (10) such that the wafer (10) has a thinner central portion (15) and a thicker peripheral edge support portion (16);

    (b) forming a plurality of P-type isolation zones (19) in the thinner central portion (15) of the first side (11) of the wafer (10);

    (c) forming a P-type diffusion region (20) in a second side (12) of the wafer opposite the first side (11) such that the P-type isolation zones extend into the P-type diffusion region (20), wherein the thicker peripheral edge support portion (16) is a part of the wafer (10) at the time of the forming of step (b) and the forming of step (c);

    (d) forming a glassivation layer (25) over the P-type isolation zone (21) on the first side (11) of the thinner central portion (15) of the wafer (10); wherein the thicker peripheral edge support portion (16) is a part of the wafer (10) at the time of forming of the glassivation layer (25) and

    (e) further processing the wafer (10) after steps (b), (c), and (d) and thereby forming a plurality of semiconductor devices, wherein the P-type isolation zone formed in step (b), the P-type diffusion region (20) formed in step (c), and the glassivation layer (25) formed in step (d) are parts of one of the semiconductor devices.


     
    2. The method of Claim 1, wherein the one of the semiconductor devices is a vertical power device taken from the group consisting of: a power diode, and a power bipolar transistor.
     
    3. The method of Claim 1 or 2, wherein the first side (11) of the thinner central portion (15) has a planar surface, wherein the planar surface has a disc-shape with a substantially circular circumference, and wherein the planar surface is more than three inches wide.
     
    4. The method of any one of Claims 1 to 3, wherein the second side of the wafer (10) opposite the first side (11) extends substantially entirely in a plane.
     
    5. The method of any one of Claims 1 to 4, wherein the obtaining of the wafer (10) in step (a) is accomplished by an action taken from the group consisting of: a) purchasing the thinned wafer (10), and b) manufacturing the thinned wafer (10).
     
    6. The method of any one of Claims 1 to 5, wherein the glassivation layer (25) is at least ten microns thick.
     
    7. The method of any of Claims 1 to 6, wherein step (e) involves removing the thicker peripheral edge support portion (16) and dicing the thinner central portion (15).
     
    8. The method of any one of Claims 1 to 7, wherein the thicker peripheral edge support portion (16) has a plurality of radially extending slits.
     
    9. The method of any one of Claims 1 to 8, wherein the thinner central portion (15) of the wafer (10) is not greater than two hundred microns thick.
     
    10. The method of any one of Claims 1 to 8, wherein the thicker peripheral edge support portion (16) has a cylindrical sidewall.
     
    11. The method of any one of Claims 1 to 10, further comprising:
    (f) forming a cathode diffusion region (22) into the thinner central portion (15).
     
    12. The method of Claim 11 , further comprising:
    (g) forming a cathode metal electrode (27) over the cathode diffusion region.
     
    13. The method of any one of Claims 1 to 12, further comprising:
    (h) forming an anode metal electrode (28) on the second side of the wafer (10).
     


    Ansprüche

    1. Verfahren zum Herstellen einer Halbleitervorrichtung, das die folgenden Schritte aufweist:

    (a) Erhalten eines ausgedünnten scheibenförmigen Halbleiterwafers (10), wobei sich eine Vertiefung in eine erste Seite (11) des Wafers (10) derart erstreckt, dass der Wafer (10) einen dünneren mittleren Abschnitt (15) und einen dickeren Umfangskantenträgerabschnitt (16) aufweist;

    (b) Ausbilden von mehreren Isolationszonen vom P-Typ (19) in dem dünneren mittleren Abschnitt (15) der ersten Seite (11) des Wafers (10);

    (c) Ausbilden eines Diffusionsbereichs vom P-Typ (20) in einer zweiten Seite (12) des Wafers, die der ersten Seite (11) gegenüberliegt, derart, dass die Isolationszonen vom P-Typ sich in den Diffusionsbereich vom P-Typ (20) erstrecken, wobei der dickere Umfangskantenträgerabschnitt (16) ein Teil des Wafers (10) zu dem Zeitpunkt der Ausbildung in Schritt (b) und der Ausbildung in Schritt (c) ist;

    (d) Ausbilden einer Glaspassivierungsschicht (25) über der Isolationszone vom P-Typ (21) auf der ersten Seite (11) des dünneren mittleren Abschnitts (15) des Wafers (10);
    wobei der Umfangskantenträgerabschnitt (16) ein Teil des Wafers (10) zu dem Zeitpunkt der Ausbildung der Glaspassivierungsschicht (25) ist; und

    (e) weiteres Verarbeiten des Wafers (10) nach den Schritten (b), (c) und (d) und dadurch Ausbilden von mehreren Halbleitervorrichtungen, wobei die Isolationszone vom P-Typ, die im Schritt (b) ausgebildet wird, der Diffusionsbereich vom P-Typ (20), der in Schritt (c) ausgebildet wird, und die Glaspassivierungsschicht (25), die in Schritt (d) ausgebildet wird, Teile von einer der Halbleitervorrichtungen sind.


     
    2. Verfahren nach Anspruch 1, wobei die eine der Halbleitervorrichtungen eine vertikale Leistungsvorrichtung aus der Gruppe ist, die aus folgenden besteht: einer Leistungsdiode und einem Leistungsbipolartransistor.
     
    3. Verfahren nach Anspruch 1 oder 2, wobei die erste Seite (11) des dünneren mittleren Abschnitts (15) eine ebene Oberfläche aufweist, wobei die ebene Oberfläche eine Scheibengestalt mit einem im Wesentlichen kreisförmigen Umfang aufweist, und wobei die ebene Oberfläche mehr als drei Zoll breit ist.
     
    4. Verfahren nach einem der Ansprüche 1 bis 3, wobei die zweite Seite des Wafers (10), die der ersten Seite (11) gegenüberliegt, sich im Wesentlichen vollständig in einer Ebene erstreckt.
     
    5. Verfahren nach einem der Ansprüche 1 bis 4, wobei das Erhalten des Wafers (10) in Schritt (a) durch eine Tätigkeit aus der Gruppe erreicht wird, die besteht aus: (a) Kaufen des ausgedünnten Wafers (10), und (b) Herstellen des ausgedünnten Wafers (10).
     
    6. Verfahren nach einem der Ansprüche 1 bis 5, wobei die Glaspassivierungsschicht (25) mindestens 10 Mikrometer dick ist.
     
    7. Verfahren nach einem der Ansprüche 1 bis 6, wobei Schritt (e) ein Entfernen des dickeren Umfangskantenträgerabschnitts (16) und ein Dicen des dünneren mittleren Abschnitts (15) enthält.
     
    8. Verfahren nach einem der Ansprüche 1 bis 7, wobei der dickere Umfangskantenträgerabschnitt (16) mehrere sich radial erstreckende Schlitze aufweist.
     
    9. Verfahren nach einem der Ansprüche 1 bis 8, wobei der dünnere mittlere Abschnitt (15) des Wafers (10) nicht mehr als 200 Mikrometer dick ist.
     
    10. Verfahren nach einem der Ansprüche 1 bis 8, wobei der dickere Umfangskantenträgerabschnitt (16) eine zylindrische Seitenwand aufweist.
     
    11. Verfahren nach einem der Ansprüche 1 bis 10, das außerdem aufweist:
    (f) Ausbilden eines Kathodendiffusionsbereichs (22) in dem dünneren mittleren Abschnitt (15).
     
    12. Verfahren nach Anspruch 11, das außerdem aufweist:
    (g) Ausbilden einer Kathodenmetallelektrode (27) über dem Kathodendiffusionsbereich.
     
    13. Verfahren nach einem der Ansprüche 1 bis 12, das außerdem aufweist:
    (h) Ausbilden einer Anodenmetallelektrode (28) auf der zweiten Seite des Wafers (10).
     


    Revendications

    1. Procédé de fabrication d'un dispositif à semi-conducteur, comprenant les étapes suivantes :

    (a) l'obtention d'une tranche amincie de semi-conducteur en forme de disque (10), dans lequel un évidement s'étend dans un premier côté (11) de la tranche (10) de sorte que la tranche (10) ait une portion centrale plus mince (15) et une portion de support de côté périphérique plus épaisse (16) ;

    (b) la formation d'une pluralité de zones d'isolement de type P (19) dans la portion centrale plus mince (15) du premier côté (11) de la tranche (10) ;

    (c) la formation d'une région de diffusion de type P (20) dans un second côté (12) de la tranche opposé au premier côté (11) de sorte que les zones d'isolement de type P s'étendent dans la région de diffusion de type P (20), dans lequel la portion de support de bord périphérique plus épaisse (16) fait partie de la tranche (10) au moment de la formation de l'étape (b) et de la formation de l'étape (c) ;

    (d) la formation d'une couche de vitrification (25) par-dessus la zone d'isolement de type P (21) sur le premier côté (11) de la portion centrale plus mince (15) de la tranche (10); dans lequel la portion de support de bord périphérique plus épaisse (16) fait partie de la tranche (10) au moment de la formation de la couche de vitrification (25) et

    (e) le traitement supplémentaire de la tranche (10) après les étapes (b), (c) et (d) et la formation ainsi d'une pluralité de dispositifs à semi-conducteur, dans lequel la zone d'isolement de type P formée à l'étape (b), la région de diffusion de type P (20) formée à l'étape (c) et la couche de vitrification (25) formée à l'étape (d) font partie de l'un des dispositifs à semi-conducteur.


     
    2. Procédé selon la revendication 1, dans lequel l'un des dispositifs à semi-conducteur est un dispositif de puissance vertical pris dans le groupe consistant en : une diode de puissance et un transistor bipolaire de puissance.
     
    3. Procédé selon la revendication 1 ou 2, dans lequel le premier côté (11) de la portion centrale plus mince (15) a une surface plane, dans lequel la surface plane a une forme de disque avec une circonférence sensiblement circulaire, et dans lequel la surface plane a une largeur de plus de trois pouces.
     
    4. Procédé selon l'une quelconque des revendications 1 à 3, dans lequel le second côté de la tranche (10) opposé au premier côté (11) s'étend sensiblement totalement dans un plan.
     
    5. Procédé selon l'une quelconque des revendications 1 à 4, dans lequel l'obtention de la tranche (10) à l'étape (a) est accomplie par une mesure prise dans le groupe consistant en : a) l'achat de la tranche amincie (10), et b) la fabrication de la tranche amincie (10).
     
    6. Procédé selon l'une quelconque des revendications 1 à 5, dans lequel la couche de vitrification (25) a une épaisseur d'au moins dix microns.
     
    7. Procédé selon l'une quelconque des revendications 1 à 6, dans lequel l'étape (e) implique l'élimination de la portion de support de bord périphérique plus épaisse (16) et le découpage en dés de la portion centrale plus mince (15).
     
    8. Procédé selon l'une quelconque des revendications 1 à 7, dans lequel la portion de support de bord périphérique plus épaisse (16) a une pluralité de fentes s'étendant radialement.
     
    9. Procédé selon l'une quelconque des revendications 1 à 8, dans lequel la portion centrale plus mince (15) de la tranche (10) a une épaisseur non supérieure à deux cents microns.
     
    10. Procédé selon l'une quelconque des revendications 1 à 8, dans lequel la portion de support de bord périphérique plus épaisse (16) a une paroi latérale cylindrique.
     
    11. Procédé selon l'une quelconque des revendications 1 à 10, comprenant en outre :
    (f) la formation d'une région de diffusion de cathode (22) dans la portion centrale plus mince (15).
     
    12. Procédé selon la revendication 11, comprenant en outre :
    (g) la formation d'une électrode métallique de cathode (27) par-dessus la région de diffusion de cathode.
     
    13. Procédé selon l'une quelconque des revendications 1 à 12, comprenant en outre :
    (h) la formation d'une électrode métallique d'anode (28) sur le second côté de la tranche (10).
     




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    REFERENCES CITED IN THE DESCRIPTION



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    Patent documents cited in the description