(19)
(11)EP 2 629 411 B1

(12)EUROPEAN PATENT SPECIFICATION

(45)Mention of the grant of the patent:
09.09.2020 Bulletin 2020/37

(21)Application number: 13000787.5

(22)Date of filing:  15.02.2013
(51)International Patent Classification (IPC): 
H02M 7/219(2006.01)

(54)

Active bridge rectification

Aktive Brückengleichrichtung

Redressement actif en pont


(84)Designated Contracting States:
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

(30)Priority: 16.02.2012 US 201213398046

(43)Date of publication of application:
21.08.2013 Bulletin 2013/34

(73)Proprietor: Linear Technology Corporation
Milpitas, CA 95035-7417 (US)

(72)Inventors:
  • Heath, Jeffrey Lynn
    Santa Barbara, CA 93105 (US)
  • Su, Kirk
    Santa Barbara, CA 93111 (US)
  • Stineman, John
    Carpinteria, CA 93013 (US)

(74)Representative: Müller-Boré & Partner Patentanwälte PartG mbB 
Friedenheimer Brücke 21
80639 München
80639 München (DE)


(56)References cited: : 
DE-A1-102008 058 760
US-B1- 7 791 914
US-A1- 2009 257 259
  
  • Davide Giacomini ET AL: "A novel high efficient approach to input bridges", PCIM Europe May 27-29, 2008 Nuremberg, Germany, 29 May 2008 (2008-05-29), XP055066353, Retrieved from the Internet: URL:http://www.irf.com/technical-info/whit epaper/TP-080527.pdf [retrieved on 2013-06-12]
  
Note: Within nine months from the publication of the mention of the grant of the European patent, any person may give notice to the European Patent Office of opposition to the European patent granted. Notice of opposition shall be filed in a written reasoned statement. It shall not be deemed to have been filed until the opposition fee has been paid. (Art. 99(1) European Patent Convention).


Description

Technical Field



[0001] This disclosure relates to power supply systems, and more particularly, to an active bridge rectifier circuit including two pairs of transistors controlled based on different criteria.

Background Art



[0002] An AC electrical power delivery system is the predominant energy delivery system between the locations where power is generated and where it is consumed. On the other hand, most electronic systems require DC power. The most common method for converting AC power into DC power is rectification using diode half-wave bridge rectification schemes or diode full-wave bridge rectification schemes.

[0003] In any of the diode bridge rectification schemes used to convert an AC voltage to a DC voltage, power is lost and waste heat is generated because of the inherent voltage drop in the diodes. MOSFET transistors coupled to appropriate control circuits are an attractive alternative to diodes in full bridge rectifier systems to reduce wasted energy. However, such factors as system noise make it very difficult to control switching of transistors in a rectifier circuit so as to achieve efficient rectification. Mistakenly turning on transistors that should not be turned on can cause catastrophic failure of the transistors, controller, and input AC power supply, as well as the circuits supplied with the output DC power. As a result, there are no commercially available MOSFET bridge controllers on the market.

[0004] There is a need for a new technique to provide active control of transistors in a rectifier circuit for converting an AC input voltage into a DC output voltage.

[0005] DE 10 2008 058760 A1 relates to a circuit having a first input and a second input which are adapted to apply an AC voltage, a first output and a second output which are configured to provide a rectified and regulated voltage, a rectifier bridge circuit connected to a power return circuit, a third transistor, a fourth transistor, and a controller adapted to control the voltage between the first and the second output at a constant value.

[0006] US 7,791,914 B1 relates to a system for converting alternating electrical current into direct electrical current including an input supply for supplying alternative electrical current which is connected to a rectifier.

[0007] US 2009/257259 A1 relates to a circuit-triggered synchro-rectifier comprising an electronic switch configured to be in its ON setting when the current flowing through its cathode exceeds a predetermined thrshold.

[0008] Davide Giacomini et al.: "A novel high efficient approach to input bridges" relates to an approach to implementing an input bridge using a self-driven synchronous rectification technique that allows the realization of a simple device with only four pins, as a direct high-efficient replacement of existing standard input rectification devices.

[0009] In the following description the term "embodiment" may have been used for subject-matter that is not part of the invention as defined by the appended claims. Only those examples that comprise all the features of the independent claims are part of the invention and thus embodiments of the invention. Parts of the subject-matter of the description not covered by the claims constitutes background art or examples useful for understanding the invention.

Summary of the Disclosure



[0010] In accordance with one aspect, the present disclosure suggests a method of controlling a circuit for converting an AC input voltage into a DC output voltage that has first and second transistors arranged in a first transistor pair, and third and fourth transistors arranged in a second transistor pair. The method involves controlling a transistor of the first pair in accordance with polarity of the AC input voltage, and controlling a transistor of the second pair based on a difference between the AC input voltage and the DC output voltage.

[0011] In particular, a transistor of the second pair may be turned on when the difference between the AC input voltage and the DC output voltage exceeds a turn on threshold value, and may be turned off when the difference between the AC input voltage and the DC output voltage falls below a turn off threshold value, which is lower than the turn on threshold value.

[0012] In accordance with another aspect of the disclosure, a system for converting an AC input voltage into a DC output voltage, comprises first and second transistors arranged in a first transistor pair, third and fourth transistors arranged in a second transistor pair, and a controller responsive to the input voltage and the output voltage to control switching of the first, second, third and fourth transistors. The controller includes an AC polarity detect circuit for determining polarity of the AC input voltage to produce a first enabling signal that enables the first transistor to turn on.

[0013] Also, the AC polarity detect circuit may determine polarity of the AC input voltage to produce a second enabling signal that enables the second transistor to turn on. The AC polarity detect circuit is configured to prevent the second transistor from turning on when the first transistor is on.

[0014] The controller may further comprise a transistor control circuit responsive to the first enabling signal to enable control of the third transistor, and responsive to the second enabling signal to enable control of the fourth transistor.

[0015] The transistor control circuit may sense the AC input voltage and the DC output voltage to determine a voltage across the third transistor and a voltage across the fourth transistors based on a difference between the AC input voltage and the DC output voltage.

[0016] In particular, the transistor control circuit may adjust a control voltage applied to the third transistor when the difference between the AC input voltage and the DC output voltage exceeds a regulate threshold value

[0017] Further, the transistor control circuit may turn on the third transistor when the difference between the AC input voltage and the DC output voltage exceeds a turn on threshold value, which may be higher than the regulate threshold value.

[0018] The transistor control circuit may turn off the third transistor when the difference between the AC input voltage and the DC output voltage falls below a turn off threshold value, which may be lower than the regulate threshold value.

[0019] Also, the transistor control circuit may produce a lock out signal for preventing the fourth transistor from turning on when the third transistor is on. The lock out signal may be produced when the difference between the AC input voltage and the DC output voltage exceeds a lock out threshold value, which may be lower than the regulate threshold value.

[0020] In an exemplary embodiment, the first to fourth transistors may be MOSFETs, preferably, N-channel MOSFETs.

[0021] In accordance with a further aspect of the disclosure, a system for converting an AC input voltage into a DC output voltage comprises first and second transistors arranged in a first transistor pair, third and fourth transistors arranged in a second transistor pair, and a controller responsive to the AC input voltage and the DC output voltage to control switching of the first, second, third and fourth transistors. The controller may include a transistor control circuit for turning on the third transistor based on a difference between the AC input voltage and the DC output voltage. The transistor control circuit is configured for producing a first lock out signal asserted to prevent the fourth transistor from turning on when the third transistor is on.

[0022] Also, the transistor control circuit may produce a second lock out signal asserted to prevent the third transistor from turning on when the fourth transistor is on.

[0023] The transistor control circuit may turn on the third transistor when a difference between the AC input voltage and the DC output voltage exceeds a turn on threshold value, and may produce the first lock out signal when the difference between the AC input voltage and the DC output voltage exceeds a lock out threshold value which is lower than the turn on threshold value.

[0024] The controller may further comprise an AC polarity detect circuit for producing first and second enabling signals based on the polarity of the AC input signal, the first and second enabling signals are generated to respectively turn on the first and second transistors.

[0025] The AC polarity detect circuit may be configured to produce the first enabling signal so as to prevent the second transistor from turning on when the first transistor is on, and to produce the second enabling signal so as to prevent the first transistor from turning on when the second transistor is on.

[0026] Additional advantages and aspects of the disclosure will become readily apparent to those skilled in the art from the following detailed description, wherein embodiments of the present disclosure are shown and described, simply by way of illustration of the best mode contemplated for practicing the present disclosure. As will be described, the disclosure is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as limitative.

Brief Description of the Drawings



[0027] The following detailed description of the embodiments of the present disclosure can best be understood when read in conjunction with the following drawings, in which the features are not necessarily drawn to scale but rather are drawn as to best illustrate the pertinent features, wherein:

FIG. 1 shows an exemplary embodiment of a system for converting an AC voltage into a DC voltage in accordance with the present disclosure.

FIG. 2 shows an exemplary embodiment of the active bridge controller in FIG. 1.

FIG. 3 shows an exemplary embodiment of the AC polarity detect circuit in FIG. 2.

FIGS. 4A-4G are timing diagrams illustrating control operations based on the AC polarity detection in accordance with the present disclosure.

FIG. 5 shows an exemplary embodiment of each top-side MOSFET control circuit in FIG. 2.

FIGS. 6A-6E are timing diagrams illustrating control of each top-side MOSFET in FIG. 1.

FIG. 7 is an exemplary embodiment of each top-side gate drive circuit in FIG. 2.

FIG. 8 is an exemplary embodiment of the Under Voltage Lock Out (UVLO) circuit in FIG. 2.


Detailed Disclosure of the Embodiments



[0028] The present disclosure will be made using specific examples presented below. It will become apparent, however, that the concept of the disclosure is applicable to any rectifier circuit having elements actively controlled for converting an AC signal to a DC signal.

[0029] FIG. 1 shows an exemplary active bridge rectifier circuit 10 of a present disclosure. The active bridge rectifier circuit 10 converts an AC input voltage from an AC power source 12 to produce DC output voltages V+ and V- delivered to a load 14 represented in FIG. 1 by resistance RLOAD. The resistance of the power source 12 is represented in FIG. 1 by resistance RSOURCE. System noise is represented in FIG. 1 by noise voltage VNOISE shown at the output of the AC power source 12.

[0030] The active bridge rectifier circuit 10 includes an active bridge composed of "top-side" MOSFETs 16 and 18, and "bottom-side" MOSFETs 20 and 22. In an example described in the present disclosure, the MOSFETs 16, 18, 20 and 22 are N-type MOSFETs. However, P-type MOSFETs, NPN BJT transistors, and PNP transistors also can be used. An output capacitor 24 is coupled in parallel to RLOAD.

[0031] An active bridge controller 26 is connected to gates of the MOSFETs 16, 18, 20 and 22 to turn them on and off so as to achieve efficient rectification. As disclosed in more detail below, input AC voltages VA and VB developed across the AC source 12 are applied to inputs of the active bridge controller 26. Also, output DC voltages V+ and V- produced by the rectifier circuit 10 are supplied to inputs of the active bridge controller 26. Top-side gate control signals GATE T1 and GATE T2 are produced by the controller 26 to control the gates of the top-side MOSFETs 16 and 18, respectively. Bottom-side gate control signals GATE B1 and GATE B2 are produced by the controller 26 to control the gates of the bottom-side MOSFETs 20 and 22, respectively.

[0032] Switching of the top-side MOSFETs 16, 18 may be controlled in accordance with conditions different from conditions determined to control switching of the bottom-side MOSFETs 20, 22. Also, a linear regulation scheme may be implemented to control the transition between the two top-side MOSFETs 16 and 18. Additionally, a lockout procedure may be carried out to ensure that opposing MOSFETs are never on at the same time, providing efficiency and ruggedness benefits.

[0033] As shown in FIG. 2, an exemplary arrangement of the active bridge controller 26 includes a pair of top-side MOSFET control circuits 102 and 104, and a pair of top-side drive circuits 106 and 108. The top-side MOSFET control circuit 102 monitors the voltages VA and V+, an Under Voltage Lock Out (UVLO) signal, and a top-side enabling signal ENA. The top-side MOSFET control circuit 104 monitors the voltages VB and V+, the UVLO signal, and a bottom-side enabling signal ENB. Also, the control circuit 104 monitors LOCK OUT 1 signal produced by the control circuit 102, whereas the control circuit 102 monitors LOCK OUT 2 signal produced by the control circuit 104. As discussed in more detail later, the LOCK OUT 1 and LOCK OUT 2 signals are asserted to ensure that both top-side MOSFETs 16 and 18 are never on at the same time.

[0034] Each of the control circuits 102 and 104 produces respective control signals FAST OFF, FAST ON and REGULATE for controlling each of the top-side gate drive circuits 106 and 108, respectively. The top-side gate drive circuit 106 is controlled to produce the gate control signal GATE T1 supplied to the gate of the MOSFET 16, and the top-side gate drive circuit 108 is controlled to produce the gate control signal GATE T2 supplied to the gate of the MOSFET 16. To provide high voltage gate control signals for controlling N-type MOSFETs, the gate drive circuits 106 and 108 are supplied with charge pump voltage CPUMP produced by a charge pump 110. Also, the gate drive circuits 106 and 108 are provided with the voltages VA and VB, respectively.

[0035] Further, the controller 26 includes a UVLO circuit 112 that asserts the UVLO signal based on the DC output voltages V+ and V-. In particular, the UVLO signal is asserted when a difference between the voltages V+ and V- is greater than a predetermined reference voltage VREF. The UVLO signal ensures that any one of the MOSFETs 16, 18, 20 and 22 is not allowed to be turned on until there is enough voltage available for each of the other MOSFETs to operate properly.

[0036] Also, the controller 26 includes an AC polarity detect circuit 114 that produces the enabling signals ENA and ENB based on the input AC voltages VA and VB, and the UVLO signal. The controller 26 further includes bottom-side gate drive circuits 116 and 118 respectively responsive to the ENA and ENB signals for producing gate control signals GATE B1 and GATE B2 supplied to the gates of the bottom-side MOSFETs 20 and 22. The bottom-side gate drive circuits 116 and 118 may include buffer circuits for forming the GATE B1 and GATE B2 signals based on the respective ENA and ENB signals so as to turn on the appropriate bottom-side MOSFET at a predetermined value of the AC input voltage and at a predetermined polarity, and to prevent both bottom-side MOSFETs 20 and 22 from turning on at the same time due to the system noise or other reasons.

[0037] Also, the enabling signals ENA and ENB are respectively supplied to the top-side MOSFET control circuits 102 and 104 to enable the MOSFET control circuits to control the respective MOSFET in a pair of top-side MOSFETs 16, 18 so as to prevent one MOSFET in the pair from turning on when the other MOSFET in the pair is turned on.

[0038] As shown in FIG. 3, an exemplary AC polarity detect circuit 114 includes comparators 202 and 204, and AND gates 206 and 208. The comparator 202 compares a difference between VA and VB with an AC polarity detect threshold defined by a threshold setting element 210. The comparator 204 compares a difference between VB and VA with an AC polarity detect threshold defined by a threshold setting element 212. The AC polarity detect thresholds defined by elements 210 and 212 may be set at the same level. The inverting input of the comparator 202 receives the voltage VB increased by the AC polarity detect threshold value and the inverting input of the comparator 204 receives the voltage VA increased by the AC polarity detect threshold value. The non-inverting inputs of the comparators 202 and 204 are supplied with the voltages VA and VB, respectively. The AC polarity detect circuit 114 also includes AND gates 206 and 208, each of which has a pair of non-inverting inputs and one inverting input. The output of the comparator 202 is supplied to the non-inverting input of the AND gate 206 and to the inverting input of the AND gate 208. The output of the comparator 204 is supplied to the non-inverting input of the AND gate 208 and to the inverting input of the AND gate 206. The UVLO signal is supplied to the remaining non-inverting inputs of the AND gates 206 and 208. The outputs of the AND gates 206 and 208 produce the enabling signals ENA and ENB, respectively.

[0039] Timing diagrams in FIGS. 4A-4G illustrate operation of the AC polarity detect circuit 114. It is noted that the diagrams illustrate signals produced when VA is greater than VB, and when VB is greater than VA. The signals corresponding to the case when VB is greater than VA are shown in FIGS. 4A-4G in parentheses.

[0040] In particular, as shown in FIG. 4A, the AC polarity detect circuit compares values of (VA - VB) and (VB - VA) with the AC polarity detect threshold. As shown in FIG. 4B, when (VA - VB) rises to the threshold level, the ENA signal is asserted to produce the GATE B1 signal that turns on the bottom-side MOSFET 20. The ENA signal remains asserted until (VA - VB) falls below the level of the AC polarity detect threshold.

[0041] When (VB - VA) rises to the threshold level, the ENB signal is asserted to produce the GATE B2 signal that turns on the bottom-side MOSFET 22. The ENB signal remains asserted until (VB - VA) falls below the level of the AC polarity detect threshold.

[0042] As illustrated in FIG. 4C, when the ENA and GATE B1 signals are not asserted, the gate of the MOSFET 20 is controlled to keep the MOSFET 20 in an off-state. Similarly, when the ENB and GATE B2 signals are not asserted, the gate of the MOSFET 22 is controlled to keep the MOSFET 22 in an off state.

[0043] FIG. 4D illustrates voltage (GATE T1 - VA) corresponding to a difference between the voltage GATE T1 and the voltage VA, and voltage (GATE T2 - VB) corresponding to a difference between the voltage GATE T2 and the voltage VB. The voltage (GATE T1 - VA) developed across the MOSFET 16 and the voltage (GATE T2 - VB) developed across the MOSFET 18 respectively control gates of the MOSFETs 16 and 18 to turn the respective MOSFET on and off in accordance with MOSFET control procedures discussed later.

[0044] As illustrated in FIG. 4E, when the GATE T1 signal is not asserted, the gate of the MOSFET 16 is controlled by the voltage value (GATE T1 - VA) to keep the MOSFET 16 in an off-state. When the GATE T2 signal is not asserted, the gate of the MOSFET 18 is controlled by the voltage value (GATE T2 - VB) to keep the MOSFET 18 in an off-state.

[0045] As illustrated in FIGS. 4F-4G, when the value (VA - VB) reaches the level of the AC polarity detect threshold, the LOCK OUT 1 signal is asserted by the top-side MOSFET control circuit 102 to prevent the top-side MOSFET 18 from turning on, when the MOSFET 16 is on. The LOCK OUT 1 signal remains asserted until the value (VA - VB) falls below the level of the AC polarity detect threshold.

[0046] Similarly, when the value (VB - VA) reaches the level of the AC polarity detect threshold, the LOCK OUT 2 signal is produced by the top-side MOSFET control circuit 104 to prevent the top-side MOSFET 16 from turning on, when the MOSFET 18 is on. The LOCK OUT 2 signal is asserted until the value (VB - VA) exceeds the level of the AC polarity detect threshold.

[0047] As shown in FIG. 5, an exemplary arrangement of each top-side MOSFET control circuit 102 or 104 may include comparators 302, 304 and 308, an operational amplifier 306 and an OR gate 310. Each of the comparators 302, 304, and 308 and the operational amplifier 306 compares a difference (Vs - V+) between voltages Vs and V+, with a threshold voltage set to control the top-side gate drive 106 and 108, where the voltage Vs corresponds to the voltage VA for the top-side MOSFET control circuit 102, and corresponds to the voltage VB for the top-side MOSFET control circuit 104.

[0048] In particular, the comparator 302 compares the (Vs - V+) value with a threshold voltage VFOFF set by a threshold setting element 312 to produce a signal supplied to non-inverting input of the OR gate 310 when the (Vs - V+) value is below the threshold voltage VFOFF. The inverting input of the comparator 302 is receives the voltage V+, whereas the non-inverting input receives the Vs voltage increased by the VFOFF value.

[0049] The UVLO and LOCK OUT signals are supplied to other non-inverting inputs of the OR gate 310, and the EN signal is supplied to the inverting input of the OR gate 310, where the LOCK OUT and EN signals correspond to the LOCK OUT 2 and ENA signals for the top-side MOSFET control circuit 102, and correspond to the LOCK OUT 1 and ENB signals for the top-side MOSFET control circuit 104. The FAST OFF signal is asserted at the output of the OR gate 310.

[0050] The comparator 304 compares (Vs - V+) with a threshold voltage VFON set by a threshold setting element 314 to produce the FAST ON signal when the (Vs - V+) value exceeds the threshold voltage VFON. The non-inverting input of the comparator 304 is responsive to the voltage V+, whereas the inverting input receives the Vs voltage increased by the VFON value.

[0051] The operational amplifier 306 compares (Vs - V+) with a threshold voltage VREG set by a threshold setting element 316 to produce the REGULATE signal when the (Vs - V+) value exceeds the threshold voltage VREG. One input of the operational amplifier 306 is responsive to the voltage V+, whereas the other input receives the Vs voltage increased by the VREG value.

[0052] The comparator 308 compares (Vs - V+) with a threshold voltage VLOCKOUT set by a threshold setting element 318 to produce the LOCK OUT 1 or LOCK OUT 2 signal when the (Vs - V+) value exceeds the threshold voltage VLOCKOUT. The non-inverting input of the comparator 302 is responsive to the voltage V+, whereas the inverting input receives the Vs voltage increased by the VLOCKOUT value.

[0053] The FAST OFF signal is asserted if there is a UVLO condition, the respective topside MOSFET control circuit is not enabled, the other top-side MOSFET control circuit is asserting the LOCKOUT signal, or the voltage (Vs - V+) is below a predetermined threshold voltage VFOFF. If the respective top-side gate drive circuit 108 or 108 receives this signal, it will rapidly turn off the respective topside MOSFET 16 or 18.

[0054] The FAST ON signal is asserted if the voltage (Vs - V+) exceeds a predetermined threshold voltage VFON to control the respective top-side gate drive circuit 106 and 108 to rapidly turn on the respective topside MOSFET 16 or 18. The REGULATE signal is an analog signal that adjusts the gate voltage of the respective topside MOSFET 16 or 18 so that the drain-source voltage across the MOSFET 16 or 18 is maintained at a pre-determined voltage level VREG, which is set low enough to maintain the power loss across the respective MOSFET 16 or 18 at a minimal level, but high enough to reliably detect when the drain-source voltage Vds of the respective MOSFET 16 or 18 is less than zero.

[0055] The LOCKOUT 1 or LOCKOUT 2 signal is asserted at a predetermined level of the respective MOSFET drain-source voltage Vds selected using the VLOCKOUT threshold value. The LOCKOUT 1 or LOCKOUT 2 signal is sent from one top-side MOSFET control circuit to the other top-side MOSFET control circuit to ensure that both topside MOSFETs 16 and 18 are never on at the same time.

[0056] Timing diagrams in FIGS. 6A-6E illustrate operations of the top-side MOSFET control circuit 102 that controls the MOSFET 16. The top-side MOSFET control circuit 104 operates in a similar manner. In particular, FIG. 6A illustrates drain current flowing through the MOSFET 16. FIG. 6B shows voltages Vs and V+. FIG. 6C illustrates correspondence between the voltage value (Vs - V+) and the threshold voltages VFON, VFOFF, VREG and VLOCKOUT. FIG. 6D shows logic values corresponding to the signals REGULATE, FAST ON, FAST OFF and LOCK OUT asserted by the top-side MOSFET control circuit 102 in response to a change in the voltage (Vs - V+).

[0057] In particular, as shown in FIG. 6D, the REGULATE signal is proportional to the voltage (Vs - V+) attempting to maintain the VREG level. The FAST ON signal is asserted when the voltage (Vs - V+) exceeds the VFON level and deasserted when the voltage (Vs - V+) is below the VFON level. The FAST OFF signal may be asserted when the voltage (Vs - V+) is below the VFOFF level. The LOCK OUT signal is asserted when the voltage (Vs - V+) exceeds the VLOCKOUT level and deasserted when the voltage (Vs - V+) falls below the VLOCKOUT level, where the LOCK OUT signal corresponds to the LOCK OUT 1 signal produced by the MOSFET control circuit 102 or to the LOCK OUT 2 signal produced by the MOSFET control circuit 104.

[0058] FIG. 6E illustrates the GATE T1 voltage produced by the top-side gate drive 106 based on the signals REGULATE, FAST ON, FAST OFF and LOCK OUT asserted by the respective top-side MOSFET control circuit 102.

[0059] The VREG voltage may be lower than the VFON voltage but greater than the VFOFF voltage, which is greater that the VLOCKOUT voltage. The VREG voltage may be choosen to be much less than a voltage drop on the body diode of the respective MOSFET.

[0060] The VFOFF voltage may be chosen to be greater than 0 V by an amount sufficient to allow the respective MOSFET to be turned off before the polarity across the MOSFET goes negative i.e. V+ becomes greater than VS. This prevents any reverse current that can cause the waste of energy.

[0061] The VFON voltage may chosen to be higher than the VREG voltage by an amount sufficient to allow the operational amplifier 306 that operates in the linear region to control the respective MOSFET in the saturated region so as to prevent the active bridge circuitry from oscillating at the beginning and at the end of the conduction cycle of the MOSFET. The range between VFON and VFOFF is selected to provide a relatively low gain of the operational amplifier 306 to enable the amplifier 306 to operate under normal noise conditions.

[0062] The VLOCKOUT voltage may be chosen to be below the VFOFF value so as to ensure that when one top-side MOSFET control circuit 102 or 104 begins to turn on its respective top-side MOSFET, the other top-side MOSFET control circuit can not turn on its respective top-side MOSFET. This lockout can prevent the catastrophic event when both top-side MOSFETs are on at the same time.

[0063] As shown in FIG. 7, an exemplary top-side MOSFET control circuit 102 or 104 may include an AND gates 400 and 402, buffers 404 and 406 and switches S1, S2 and S3. The AND gate 400 has a non-inverting input supplied with the FAST ON signal, and inverting input supplied with the FAST OFF signal. The AND gate 402 has inverting inputs responsive to the FAST ON and FAST OFF signals. Only one of the switches S1, S2 or S3 can be on at the same time. The analog signal REGULATE passes to the respective MOSFET gate through the switch S1 when S1 is closed by the output of the AND gate 402 and the switches S2 and S3 are open by signals buffered by the buffers 404 and 406. The switch S2 is controlled by the output of the AND gate 400 via the buffer 404 to apply the CPUMP voltage produced by the charge pump 110 to the MOSFET gate. The CPUMP voltage is applied to operate the gates of the respective MOSFET 16 or 18 above their sources voltages, so as to support operations of N-channel MOSFETS. The switch S3 is controlled by the FAST OFF signal via the buffer 406 to apply the FAST OFF signal to the MOSFET gate.

[0064] FIG. 8 illustrates an exemplary UVLO circuit 112 that produces the UVLO signal when a difference between the voltages V+ and V- is greater than a predetermined reference voltage VREF. In particular, the UVLO circuit 112 may include a comparator 502 having an inverting input supplied by the V+ voltage, and a non-inverting input supplied with the V-value increased by the VREF value set by a reference voltage setting element 504.

[0065] The foregoing description illustrates and describes aspects of the present invention. Additionally, the disclosure shows and describes only preferred embodiments, but as aforementioned, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or the skill or knowledge of the relevant art.

[0066] The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein.


Claims

1. A system (10) for converting an AC input voltage into a rectified output voltage, comprising:

first and second transistors (20, 22) arranged in a first transistor pair,

third and fourth transistors (16, 18) arranged in a second transistor pair, and

a controller (26) responsive to the input voltage and the output voltage to control switching of the first, second, third and fourth transistors (20, 22, 16, 18),

the controller (26) being configured to control transistors in the first transistor pair (20, 22) in accordance with polarity of the AC input signal, and to control the third transistor (16) based on a voltage across the third transistor (16) and to control the fourth transistor (18) based on a voltage across the fourth transistor (18),

the controller (26) including an AC polarity detect circuit (114) for determining the polarity of the AC input voltage to produce a first enabling signal (ENA) that enables the first transistor (20) to turn on,

wherein the AC polarity detect circuit is further configured to produce a second enabling signal (ENB) that enables the second transistor to turn on, the controller being configured to prevent the second transistor from turning on when the first transistor is on.


 
2. The system (10) of claim 1, wherein the controller further comprises a transistor control circuit (102,104) responsive to the first enabling signal (ENA) to enable control of the third transistor (16), and, optionally,
wherein the transistor control circuit (102,104) is further responsive to the second enabling signal (ENB) to enable control of the fourth transistor (18).
 
3. The system (10) of claim 2, wherein the transistor control circuit (102,104) is further configured to adjust a control voltage applied to the third transistor (16) when a difference between the AC input voltage and the DC output voltage exceeds a regulate threshold value.
 
4. The system (10) of claim 2, wherein the transistor control circuit (102,104) is further configured to turn on the third transistor (16) when the difference between the AC input voltage and the DC output voltage exceeds a turn on threshold value, which is higher than the regulate threshold value, and, optionally,
wherein the transistor control circuit (102,104) is further configured to turn off the third transistor (16) when the difference between the AC input voltage and the DC output voltage falls below a turn off threshold value, which is lower than the regulate threshold value.
 
5. The system (10) of claim 2, wherein the transistor control circuit (102) is configured to produce a lock out signal (LOCKOUT 1) for preventing the fourth transistor (18) from turning on when the third transistor (16) is on, and, optionally,
wherein the transistor control circuit (102,104) is configured to produce the lock out signal (LOCK OUT 1) when the difference between the AC input voltage and the DC output voltage exceeds a lock out threshold value,
wherein, optionally, the lock out threshold value is lower than the regulate threshold value.
 
6. The system (10) of any of the preceding claims, wherein the transistors (20, 22, 16, 18) are MOSFETs.
 
7. The system (10) of claim 2 , wherein
the transistor control circuit (102,104) is further configured for producing a first lock out signal (LOCK OUT 1) asserted to prevent the fourth transistor (18) from turning on when the third transistor (16) is on.
 
8. The system (10) of claim 2, wherein the transistor control circuit (102,104) is configured for producing a second lock out signal (LOCK OUT 2) asserted to prevent the third transistor (16) from turning on when the fourth transistor (18) is on.
 
9. The system (10) of one or both of claims 7 and 8, wherein the transistor control circuit (102,104) is configured for turning on the third transistor (16) when a difference between the AC input voltage and the DC output voltage exceeds a turn on threshold value, and the transistor control circuit (102,104) is further configured for producing the first lock out signal (LOCK OUT 1) when the difference between the AC input voltage and the DC output voltage exceeds a lock out threshold value which is lower than the turn on threshold value.
 
10. A method of rectifying an AC input voltage provided at first and second input nodes (VA, VB), using first and second transistors (20, 22) arranged in a first transistor pair, and third and fourth transistors (16, 18) arranged in a second transistor pair,
the method comprising the steps of:

producing a first turn on signal for turning on the third transistor (16) coupled to the first input node (VA) when a difference between a first voltage developed at the first input node (VA) and the output voltage (V+, V-) exceeds a first turn on value,

producing a first regulate signal for controlling the third transistor (16) to maintain the difference between the first voltage and the output voltage at a first regulate value lower than the first turn on value, and

producing a first turn off signal for turning off the third transistor (16) when the difference between the first voltage and the output voltage falls below a first turn off value lower than the first regulate value, and

controlling the third transistor (16) based on a voltage across the third transistor (16) and controlling the fourth transistor (18) based on a voltage across the fourth transistor (18),
the method further comprising the step of controlling the first and second transistors (20, 22) in accordance with polarity of the AC input voltage, the method further comprising the steps of: producing first and second enabling signals (ENA, ENB) based on polarity of the AC input signal to respectively turn on the first and second transistors (20, 22), the first enabling signal (ENA) being produced so as to prevent the second transistor (22) from turning on when the first transistor (20) is on, and the second enabling signal (ENB) being produced so as to prevent the first transistor (20) from turning on when the second transistor (22) is on.
 
11. The method of claim 10 , further comprising the steps of:

producing a second turn on signal for turning on the fourth transistor (18) coupled to the second input node (VB) when a difference between a second voltage developed at the second input node (VB) and the output voltage exceeds a second turn on value,

producing a second regulate signal for controlling the fourth transistor (18) to maintain the difference between the first voltage and the output voltage at a regulate value lower than the second turn on value,

producing a second turn off signal for turning off the fourth transistor (18) when the difference between the second voltage and the output voltage falls below a second turn off value lower than the second regulate value, and, optionally,

wherein the first turn on value is substantially equal to the second turn on value, the first regulate value is substantially equal to the second regulate value and the first turn off value is substantially equal to the second turn off value.


 


Ansprüche

1. Ein System (10) zum Umwandeln eines Wechselstrom-Eingangssignals in eine gleichgerichtete Ausgangsspannung, das Folgendes umfasst:

einen ersten und zweiten Transistor (20, 22), die in einem ersten Transistorpaar angeordnet sind,

einen dritten und vierten Transistor (16, 18), die in einem zweiten Transistorpaar angeordnet sind, und

eine Steuerung (26), der auf die Eingangsspannung und die Ausgangsspannung anspricht, um das Schalten des ersten, zweiten, dritten und vierten Transistors (20, 22, 16, 18) zu steuern,

wobei die Steuerung (26) so konfiguriert ist, dass sie Transistoren im ersten Transistorpaar (20, 22) gemäß der Polarität des Wechselstrom-Eingangssignals steuert, und dass sie den dritten Transistor (16) auf der Grundlage einer Spannung am dritten Transistor (16) steuert, und dass sie den vierten Transistor (18) auf der Grundlage einer Spannung am vierten Transistor (18) steuert,

wobei die Steuerung (26) eine Wechselstrom-Polaritätserfassungsschaltung (114) zum Bestimmen der Polarität der Wechselstrom-Eingangsspannung enthält, um ein erstes Freigabesignal (enabling signal) (ENA) zu erzeugen, das den ersten Transistor (20) zum Einschalten freigibt,

wobei die Wechselstrom-Polaritätserfassungsschaltung ferner so konfiguriert ist, dass sie ein zweites Freigabesignal (ENB) erzeugt, das den zweiten Transistor zum Einschalten freigibt, wobei die Steuerung so konfiguriert ist, dass sie verhindert, dass der zweite Transistor eingeschaltet wird, wenn der erste Transistor eingeschaltet ist.


 
2. Das System (10) nach Anspruch 1, wobei die Steuerung ferner eine Transistor-Steuerschaltung (102, 104) umfasst, die auf das erste Freigabesignal (ENA) anspricht, um die Steuerung des dritten Transistors (16) freizugeben, und wobei optional die Transistor-Steuerschaltung (102, 104) ferner auf das zweite Freigabesignal (ENB) anspricht, um die Steuerung des vierten Transistors (18) freizugeben.
 
3. Das System (10) nach Anspruch 2, wobei die Transistor-Steuerschaltung (102, 104) ferner so konfiguriert ist, dass sie eine an den dritten Transistor (16) angelegte Steuerspannung einstellt, wenn eine Differenz zwischen der Wechselstrom-Eingangsspannung und der Gleichstrom-Ausgangsspannung einen Regel-Schwellenwert überschreitet.
 
4. Das System (10) nach Anspruch 2, wobei die Transistor-Steuerschaltung (102, 104) ferner so konfiguriert ist, dass sie den dritten Transistor (16) einschaltet, wenn die Differenz zwischen der Wechselstrom-Eingangsspannung und der Gleichstrom-Ausgangsspannung einen Einschalt-Schwellenwert überschreitet, der höher ist als der Regel-Schwellenwert, und optional,
wobei die Transistor-Steuerschaltung (102, 104) ferner so konfiguriert ist, dass sie den dritten Transistor (16) ausschaltet, wenn die Differenz zwischen der Wechselstrom-Eingangsspannung und der Gleichstrom-Ausgangsspannung unter einen Ausschalt-Schwellenwert fällt, der niedriger als der Regel-Schwellenwert ist.
 
5. Das System (10) nach Anspruch 2, wobei die Transistor-Steuerschaltung (102) so konfiguriert ist, dass sie ein Sperrsignal (lock out signal) (LOCK OUT 1) erzeugt, um zu verhindern, dass der vierte Transistor (18) einschaltet, wenn der dritte Transistor (16) eingeschaltet ist, und optional,
wobei die Transistor-Steuerschaltung (102, 104) so konfiguriert ist, dass sie das Sperrsignal (LOCK OUT 1) erzeugt, wenn die Differenz zwischen der Wechselstrom-Eingangsspannung und der Gleichstrom-Ausgangsspannung einen Sperr-Schwellenwert überschreitet,
wobei optional der Sperr-Schwellenwert niedriger ist als der Regel-Schwellenwert.
 
6. Das System (10) nach irgendeinem der vorhergehenden Ansprüche, wobei die Transistoren (20, 22, 16, 18) MOSFETs sind.
 
7. Das System (10) nach Anspruch 2, wobei die Transistor-Steuerschaltung (102, 104) ferner so konfiguriert ist, dass sie ein erstes Sperrsignal (LOCK OUT 1) erzeugt, das gesetzt wird (asserted), um das Einschalten des vierten Transistors (18) zu verhindern, wenn der dritte Transistor (16) eingeschaltet ist.
 
8. Das System (10) nach Anspruch 2, wobei die Transistor-Steuerschaltung (102, 104) so konfiguriert ist, dass sie ein zweites Sperrsignal (LOCK OUT 2) erzeugt, das gesetzt wird, um ein Einschalten des dritten Transistors (16) zu verhindern, wenn der vierte Transistor (18) eingeschaltet ist.
 
9. Das System (10) nach einem oder beiden Ansprüchen 7 und 8, wobei die Transistor-Steuerschaltung (102, 104) so konfiguriert ist, dass sie den dritten Transistor (16) einschaltet, wenn eine Differenz zwischen der Wechselstrom-Eingangsspannung und der Gleichstrom-Ausgangsspannung einen Einschalt-Schwellenwert überschreitet, und wobei die Transistor-Steuerschaltung (102, 104) ferner so konfiguriert ist, dass sie das erste Sperrsignal (LOCK OUT 1) erzeugt, wenn die Differenz zwischen der Wechselstrom-Eingangsspannung und der Gleichstrom-Ausgangsspannung einen Sperr-Schwellenwert überschreitet, der niedriger als der Einschalt-Schwellenwert ist.
 
10. Ein Verfahren zum Gleichrichten einer Wechselstrom-Eingangsspannung, die an einem ersten und einem zweiten Eingangsknoten (VA, VB) bereitgestellt wird, unter Verwendung eines ersten und eines zweiten Transistors (20, 22), die in einem ersten Transistorpaar angeordnet sind, und eines dritten und eines vierten Transistors (16, 18), die in einem zweiten Transistorpaar angeordnet sind,
wobei das Verfahren die folgenden Schritte umfasst:

Erzeugen eines ersten Einschaltsignals zum Einschalten des mit dem ersten Eingangsknoten (VA) gekoppelten dritten Transistors (16), wenn eine Differenz zwischen einer am ersten Eingangsknoten (VA) entwickelten ersten Spannung und der Ausgangsspannung (V+, V-) einen ersten Einschaltwert überschreitet,

Erzeugen eines ersten Regelsignals zur Steuerung des dritten Transistors (16), um die Differenz zwischen der ersten Spannung und der Ausgangsspannung auf einem ersten Regelwert zu halten, der niedriger ist als der erste Einschaltwert, und

Erzeugen eines ersten Ausschaltsignals zum Ausschalten des dritten Transistors (16), wenn die Differenz zwischen der ersten Spannung und der Ausgangsspannung unter einen ersten Ausschaltwert fällt, der niedriger ist als der erste Regelwert, und

Steuern des dritten Transistors (16) auf der Grundlage einer Spannung am dritten Transistor (16) und Steuern des vierten Transistors (18) auf der Grundlage einer Spannung am vierten Transistor (18),

wobei das Verfahren ferner den folgenden Schritt umfasst: Steuern des ersten und zweiten Transistors (20, 22) entsprechend der Polarität der Wechselstrom-Eingangsspannung, wobei das Verfahren ferner die folgenden Schritte umfasst: Erzeugen eines ersten und eines zweiten Freigabesignals (ENA, ENB) basierend auf der Polarität des Wechselstrom-Eingangssignals, um den ersten bzw. den zweiten Transistor (20, 22) einzuschalten, wobei das erste Freigabesignal (ENA) so erzeugt wird, dass verhindert wird, dass der zweite Transistor (22) einschaltet, wenn der erste Transistor (20) eingeschaltet ist, und wobei das zweite Freigabesignal (ENB) so erzeugt wird, dass verhindert wird, dass der erste Transistor (20) einschaltet, wenn der zweite Transistor (22) eingeschaltet ist.
 
11. Das Verfahren nach Anspruch 10, das ferner die folgenden Schritte umfasst:

Erzeugen eines zweiten Einschaltsignals zum Einschalten des mit dem zweiten Eingangsknoten (VB) gekoppelten vierten Transistors (18), wenn eine Differenz zwischen einer am zweiten Eingangsknoten (VB) entwickelten zweiten Spannung und der Ausgangsspannung einen zweiten Einschaltwert überschreitet,

Erzeugen eines zweiten Regelsignals zur Steuerung des vierten Transistors (18), um die Differenz zwischen der ersten Spannung und der Ausgangsspannung auf einem Regelwert zu halten, der niedriger ist als der zweite Einschaltwert,

Erzeugen eines zweiten Ausschaltsignals zum Ausschalten des vierten Transistors (18), wenn die Differenz zwischen der zweiten Spannung und der Ausgangsspannung unter einen zweiten Ausschaltwert fällt, der niedriger ist als der zweite Regelwert, und optional

wobei der erste Einschaltwert im Wesentlichen gleich dem zweiten Einschaltwert ist, der erste Regelwert im Wesentlichen gleich dem zweiten Regelwert ist und der erste Ausschaltwert im Wesentlichen gleich dem zweiten Ausschaltwert ist.


 


Revendications

1. Un système (10) pour convertir une tension d'entrée CA en une tension de sortie redressée, comprenant :

des transistors premier et deuxième (20, 22) agencés dans une première paire de transistors,

des transistors troisième et quatrième (16, 18) agencés dans une deuxième paire de transistors, et

une commande (26) réagissant à la tension d'entrée et à la tension de sortie pour commander la commutation des transistors premier, deuxième, troisième et quatrième (20, 22, 16, 18),

la commande (26) étant configurée pour commander les transistors de la première paire de transistors (20, 22) conformément à la polarité du signal d'entrée CA, et pour commander le troisième transistor (16) conformément à une tension à travers le troisième transistor (16) et pour commander le quatrième transistor (18) conformément à une tension à travers le quatrième transistor (18),

la commande (26) incluant un circuit de détection de polarité CA (114) pour déterminer la polarité de la tension d'entrée CA afin de produire un premier signal de validation (ENA) qui permet au premier transistor (20) d'être mis en marche (turned on),

sachant que le circuit de détection de polarité CA est en outre configuré pour produire un deuxième signal de validation (ENB) qui permet au deuxième transistor d'être mis en marche, la commande étant configurée pour empêcher le deuxième transistor d'être mis en marche lorsque le premier transistor est mis en marche.


 
2. Le système (10) d'après la revendication 1, sachant que la commande comprend en outre un circuit de commande de transistor (102, 104) réagissant au premier signal de validation (ENA) pour activer la commande du troisième transistor (16), et, facultativement,
sachant que le circuit de commande de transistor (102, 104) réagit en outre au deuxième signal de validation (ENB) pour activer la commande du quatrième transistor (18).
 
3. Le système (10) d'après la revendication 2, sachant que le circuit de commande de transistor (102, 104) est en outre configuré pour ajuster une tension de commande appliquée au troisième transistor (16) lorsqu'une différence entre la tension d'entrée CA et la tension de sortie CC dépasse une valeur de seuil de régulation.
 
4. Le système (10) d'après la revendication 2, sachant que le circuit de commande de transistor (102, 104) est en outre configuré pour mettre en marche le troisième transistor (16) lorsque la différence entre la tension d'entrée CA et la tension de sortie CC dépasse une valeur de seuil de mise en marche, qui est supérieure à la valeur de seuil de régulation, et, facultativement,
sachant que le circuit de commande de transistor (102, 104) est en outre configuré pour mettre à l'arrêt (turn off) le troisième transistor (16) lorsque la différence entre la tension d'entrée CA et la tension de sortie CC tombe en dessous d'une valeur de seuil de mise à l'arrêt, qui est inférieure à la valeur de seuil de régulation.
 
5. Le système (10) d'après la revendication 2, sachant que le circuit de commande de transistor (102) est configuré pour produire un signal de verrouillage (LOCK OUT 1) pour empêcher le quatrième transistor (18) de se mettre en marche lorsque le troisième transistor (16) est en marche, et, facultativement,
sachant que le circuit de commande du transistor (102,104) est configuré pour produire le signal de verrouillage (LOCK OUT 1) lorsque la différence entre la tension d'entrée CA et la tension de sortie CC dépasse une valeur de seuil de verrouillage,
sachant que, facultativement, la valeur de seuil de verrouillage est inférieure à la valeur de seuil de régulation.
 
6. Le système (10) d'après l'une quelconque des revendications précédentes, sachant que les transistors (20, 22, 16, 18) sont des MOSFETs.
 
7. Le système (10) d'après la revendication 2, sachant que le circuit de commande des transistors (102, 104) est en outre configuré pour produire un premier signal de verrouillage (LOCK OUT 1) excité (asserted) pour empêcher le quatrième transistor (18) d'être mis en marche lorsque le troisième transistor (16) est mis en marche.
 
8. Le système (10) d'après la revendication 2, sachant que le circuit de commande de transistor (102, 104) est configuré pour produire un deuxième signal de verrouillage (LOCK OUT 2) excité pour empêcher le troisième transistor (16) de se mettre en marche lorsque le quatrième transistor (18) est en marche.
 
9. Le système (10) d'après l'une ou les deux revendications 7 et 8, sachant que le circuit de commande de transistor (102, 104) est configuré pour mettre en marche le troisième transistor (16) lorsqu'une différence entre la tension d'entrée CA et la tension de sortie CC dépasse une valeur de seuil de mise en marche, et que le circuit de commande de transistor (102, 104) est en outre configuré pour produire le premier signal de verrouillage (LOCK OUT 1) lorsque la différence entre la tension d'entrée CA et la tension de sortie CC dépasse une valeur de seuil de verrouillage qui est inférieure à la valeur de seuil de mise en marche.
 
10. Un procédé de redressement d'une tension d'entrée CA fournie à des nœuds d'entrée premier et deuxième (VA, VB), en utilisant des transistors premier et deuxième (20, 22) agencés dans une première paire de transistors, et des troisième et quatrième transistors (16, 18) agencés dans une deuxième paire de transistors, le procédé comprenant les étapes consistant à :

produire un premier signal de mise en marche pour mettre en marche le troisième transistor (16) couplé au premier nœud d'entrée (VA) lorsqu'une différence entre une première tension développée au premier nœud d'entrée (VA) et la tension de sortie (V+, V-) dépasse une première valeur de mise en marche,

produire un premier signal de régulation pour commander le troisième transistor (16) afin de maintenir la différence entre la première tension et la tension de sortie à une première valeur de régulation inférieure à la première valeur de mise en marche, et à

produire un premier signal de mise à l'arrêt pour mettre à l'arrêt le troisième transistor (16) lorsque la différence entre la première tension et la tension de sortie tombe en dessous d'une première valeur de mise à l'arrêt inférieure à la première valeur de régulation, et à

commander le troisième transistor (16) sur la base d'une tension à travers le troisième transistor (16) et à commander le quatrième transistor (18) sur la base d'une tension à travers le quatrième transistor (18),

le procédé comprenant en outre l'étape consistant à commander les transistors premier et deuxième (20, 22) conformément à la polarité de la tension d'entrée CA, le procédé comprenant en outre les étapes consistant à : produire des signaux de validation premier et deuxième (ENA, ENB) sur la base de la polarité du signal d'entrée CA pour mettre respectivement en marche les transistors premier et deuxième (20, 22), le premier signal de validation (ENA) étant produit de manière à empêcher le deuxième transistor (22) de se mettre en marche lorsque le premier transistor (20) est en marche, et le deuxième signal de validation (ENB) étant produit de manière à empêcher le premier transistor (20) de se mettre en marche lorsque le deuxième transistor (22) est en marche.


 
11. Le procédé d'après la revendication 10, comprenant en outre les étapes consistant à :

produire un deuxième signal de mise en marche pour mettre en marche le quatrième transistor (18) couplé au deuxième nœud d'entrée (VB) lorsqu'une différence entre une deuxième tension, développée au deuxième nœud d'entrée (VB), et la tension de sortie dépasse une deuxième valeur de mise en marche,

produire un deuxième signal de régulation pour commander le quatrième transistor (18) afin de maintenir la différence entre la première tension et la tension de sortie à une valeur de régulation inférieure à la deuxième valeur de mise en marche,

produire un deuxième signal de mise à l'arrêt pour mettre à l'arrêt le quatrième transistor (18) lorsque la différence entre la deuxième tension et la tension de sortie tombe en dessous d'une deuxième valeur de mise à l'arrêt inférieure à la deuxième valeur de régulation, et, facultativement,

sachant que la première valeur de mise en marche est essentiellement égale à la deuxième valeur de mise en marche, que la première valeur de régulation est essentiellement égale à la deuxième valeur de régulation et que la première valeur de mise à l'arrêt est essentiellement égale à la deuxième valeur de mise à l'arrêt.


 




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Cited references

REFERENCES CITED IN THE DESCRIPTION



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Patent documents cited in the description